From Michal Simek: arm: Xilinx Zynq clock changes for v3.11 Change Xilinx Zynq DT clock description which reflects logical abstraction of Zynq's clock tree. - Refactor PLL driver - Use new clock controller driver - Change timer and uart drivers * tag 'zynq-clk-for-3.11' of git://git.xilinx.com/linux-xlnx: clk: zynq: Remove deprecated clock code arm: zynq: Migrate platform to clock controller clk: zynq: Add clock controller driver clk: zynq: Factor out PLL driver Signed-off-by: Olof Johansson <olof@lixom.net>tirimbino
Olof Johansson
12 years ago
commit
e56c60c374
@ -1,378 +0,0 @@ |
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/*
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* Copyright (c) 2012 National Instruments |
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* |
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* Josh Cartwright <josh.cartwright@ni.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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* |
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* You should have received a copy of the GNU General Public License along with |
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/slab.h> |
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#include <linux/kernel.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clk/zynq.h> |
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static void __iomem *slcr_base; |
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struct zynq_pll_clk { |
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struct clk_hw hw; |
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void __iomem *pll_ctrl; |
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void __iomem *pll_cfg; |
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}; |
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#define to_zynq_pll_clk(hw) container_of(hw, struct zynq_pll_clk, hw) |
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#define CTRL_PLL_FDIV(x) ((x) >> 12) |
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static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct zynq_pll_clk *pll = to_zynq_pll_clk(hw); |
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return parent_rate * CTRL_PLL_FDIV(ioread32(pll->pll_ctrl)); |
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} |
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static const struct clk_ops zynq_pll_clk_ops = { |
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.recalc_rate = zynq_pll_recalc_rate, |
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}; |
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static void __init zynq_pll_clk_setup(struct device_node *np) |
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{ |
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struct clk_init_data init; |
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struct zynq_pll_clk *pll; |
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const char *parent_name; |
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struct clk *clk; |
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u32 regs[2]; |
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int ret; |
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ret = of_property_read_u32_array(np, "reg", regs, ARRAY_SIZE(regs)); |
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if (WARN_ON(ret)) |
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return; |
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pll = kzalloc(sizeof(*pll), GFP_KERNEL); |
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if (WARN_ON(!pll)) |
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return; |
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pll->pll_ctrl = slcr_base + regs[0]; |
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pll->pll_cfg = slcr_base + regs[1]; |
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of_property_read_string(np, "clock-output-names", &init.name); |
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init.ops = &zynq_pll_clk_ops; |
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parent_name = of_clk_get_parent_name(np, 0); |
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init.parent_names = &parent_name; |
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init.num_parents = 1; |
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pll->hw.init = &init; |
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clk = clk_register(NULL, &pll->hw); |
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if (WARN_ON(IS_ERR(clk))) |
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return; |
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ret = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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if (WARN_ON(ret)) |
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return; |
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} |
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CLK_OF_DECLARE(zynq_pll, "xlnx,zynq-pll", zynq_pll_clk_setup); |
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struct zynq_periph_clk { |
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struct clk_hw hw; |
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struct clk_onecell_data onecell_data; |
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struct clk *gates[2]; |
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void __iomem *clk_ctrl; |
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spinlock_t clkact_lock; |
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}; |
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#define to_zynq_periph_clk(hw) container_of(hw, struct zynq_periph_clk, hw) |
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static const u8 periph_clk_parent_map[] = { |
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0, 0, 1, 2 |
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}; |
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#define PERIPH_CLK_CTRL_SRC(x) (periph_clk_parent_map[((x) & 0x30) >> 4]) |
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#define PERIPH_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) |
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static unsigned long zynq_periph_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); |
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return parent_rate / PERIPH_CLK_CTRL_DIV(ioread32(periph->clk_ctrl)); |
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} |
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static u8 zynq_periph_get_parent(struct clk_hw *hw) |
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{ |
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struct zynq_periph_clk *periph = to_zynq_periph_clk(hw); |
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return PERIPH_CLK_CTRL_SRC(ioread32(periph->clk_ctrl)); |
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} |
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static const struct clk_ops zynq_periph_clk_ops = { |
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.recalc_rate = zynq_periph_recalc_rate, |
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.get_parent = zynq_periph_get_parent, |
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}; |
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static void __init zynq_periph_clk_setup(struct device_node *np) |
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{ |
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struct zynq_periph_clk *periph; |
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const char *parent_names[3]; |
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struct clk_init_data init; |
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int clk_num = 0, err; |
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const char *name; |
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struct clk *clk; |
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u32 reg; |
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int i; |
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err = of_property_read_u32(np, "reg", ®); |
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if (WARN_ON(err)) |
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return; |
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periph = kzalloc(sizeof(*periph), GFP_KERNEL); |
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if (WARN_ON(!periph)) |
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return; |
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periph->clk_ctrl = slcr_base + reg; |
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spin_lock_init(&periph->clkact_lock); |
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init.name = np->name; |
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init.ops = &zynq_periph_clk_ops; |
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for (i = 0; i < ARRAY_SIZE(parent_names); i++) |
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parent_names[i] = of_clk_get_parent_name(np, i); |
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init.parent_names = parent_names; |
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init.num_parents = ARRAY_SIZE(parent_names); |
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periph->hw.init = &init; |
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clk = clk_register(NULL, &periph->hw); |
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if (WARN_ON(IS_ERR(clk))) |
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return; |
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err = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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if (WARN_ON(err)) |
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return; |
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err = of_property_read_string_index(np, "clock-output-names", 0, |
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&name); |
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if (WARN_ON(err)) |
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return; |
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periph->gates[0] = clk_register_gate(NULL, name, np->name, 0, |
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periph->clk_ctrl, 0, 0, |
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&periph->clkact_lock); |
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if (WARN_ON(IS_ERR(periph->gates[0]))) |
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return; |
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clk_num++; |
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/* some periph clks have 2 downstream gates */ |
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err = of_property_read_string_index(np, "clock-output-names", 1, |
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&name); |
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if (err != -ENODATA) { |
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periph->gates[1] = clk_register_gate(NULL, name, np->name, 0, |
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periph->clk_ctrl, 1, 0, |
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&periph->clkact_lock); |
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if (WARN_ON(IS_ERR(periph->gates[1]))) |
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return; |
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clk_num++; |
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} |
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periph->onecell_data.clks = periph->gates; |
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periph->onecell_data.clk_num = clk_num; |
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err = of_clk_add_provider(np, of_clk_src_onecell_get, |
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&periph->onecell_data); |
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if (WARN_ON(err)) |
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return; |
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} |
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CLK_OF_DECLARE(zynq_periph, "xlnx,zynq-periph-clock", zynq_periph_clk_setup); |
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/* CPU Clock domain is modelled as a mux with 4 children subclks, whose
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* derivative rates depend on CLK_621_TRUE |
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*/ |
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struct zynq_cpu_clk { |
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struct clk_hw hw; |
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struct clk_onecell_data onecell_data; |
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struct clk *subclks[4]; |
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void __iomem *clk_ctrl; |
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spinlock_t clkact_lock; |
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}; |
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#define to_zynq_cpu_clk(hw) container_of(hw, struct zynq_cpu_clk, hw) |
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static const u8 zynq_cpu_clk_parent_map[] = { |
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1, 1, 2, 0 |
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}; |
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#define CPU_CLK_SRCSEL(x) (zynq_cpu_clk_parent_map[(((x) & 0x30) >> 4)]) |
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#define CPU_CLK_CTRL_DIV(x) (((x) & 0x3F00) >> 8) |
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static u8 zynq_cpu_clk_get_parent(struct clk_hw *hw) |
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{ |
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); |
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return CPU_CLK_SRCSEL(ioread32(cpuclk->clk_ctrl)); |
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} |
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static unsigned long zynq_cpu_clk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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struct zynq_cpu_clk *cpuclk = to_zynq_cpu_clk(hw); |
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return parent_rate / CPU_CLK_CTRL_DIV(ioread32(cpuclk->clk_ctrl)); |
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} |
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static const struct clk_ops zynq_cpu_clk_ops = { |
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.get_parent = zynq_cpu_clk_get_parent, |
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.recalc_rate = zynq_cpu_clk_recalc_rate, |
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}; |
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struct zynq_cpu_subclk { |
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struct clk_hw hw; |
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void __iomem *clk_621; |
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enum { |
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CPU_SUBCLK_6X4X, |
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CPU_SUBCLK_3X2X, |
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CPU_SUBCLK_2X, |
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CPU_SUBCLK_1X, |
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} which; |
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}; |
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#define CLK_621_TRUE(x) ((x) & 1) |
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#define to_zynq_cpu_subclk(hw) container_of(hw, struct zynq_cpu_subclk, hw); |
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static unsigned long zynq_cpu_subclk_recalc_rate(struct clk_hw *hw, |
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unsigned long parent_rate) |
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{ |
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unsigned long uninitialized_var(rate); |
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struct zynq_cpu_subclk *subclk; |
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bool is_621; |
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subclk = to_zynq_cpu_subclk(hw) |
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is_621 = CLK_621_TRUE(ioread32(subclk->clk_621)); |
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switch (subclk->which) { |
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case CPU_SUBCLK_6X4X: |
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rate = parent_rate; |
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break; |
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case CPU_SUBCLK_3X2X: |
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rate = parent_rate / 2; |
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break; |
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case CPU_SUBCLK_2X: |
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rate = parent_rate / (is_621 ? 3 : 2); |
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break; |
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case CPU_SUBCLK_1X: |
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rate = parent_rate / (is_621 ? 6 : 4); |
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break; |
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}; |
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return rate; |
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} |
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static const struct clk_ops zynq_cpu_subclk_ops = { |
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.recalc_rate = zynq_cpu_subclk_recalc_rate, |
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}; |
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static struct clk *zynq_cpu_subclk_setup(struct device_node *np, u8 which, |
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void __iomem *clk_621) |
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{ |
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struct zynq_cpu_subclk *subclk; |
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struct clk_init_data init; |
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struct clk *clk; |
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int err; |
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err = of_property_read_string_index(np, "clock-output-names", |
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which, &init.name); |
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if (WARN_ON(err)) |
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goto err_read_output_name; |
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subclk = kzalloc(sizeof(*subclk), GFP_KERNEL); |
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if (!subclk) |
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goto err_subclk_alloc; |
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subclk->clk_621 = clk_621; |
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subclk->which = which; |
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init.ops = &zynq_cpu_subclk_ops; |
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init.parent_names = &np->name; |
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init.num_parents = 1; |
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subclk->hw.init = &init; |
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clk = clk_register(NULL, &subclk->hw); |
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if (WARN_ON(IS_ERR(clk))) |
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goto err_clk_register; |
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return clk; |
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err_clk_register: |
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kfree(subclk); |
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err_subclk_alloc: |
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err_read_output_name: |
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return ERR_PTR(-EINVAL); |
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} |
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static void __init zynq_cpu_clk_setup(struct device_node *np) |
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{ |
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struct zynq_cpu_clk *cpuclk; |
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const char *parent_names[3]; |
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struct clk_init_data init; |
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void __iomem *clk_621; |
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struct clk *clk; |
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u32 reg[2]; |
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int err; |
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int i; |
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err = of_property_read_u32_array(np, "reg", reg, ARRAY_SIZE(reg)); |
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if (WARN_ON(err)) |
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return; |
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cpuclk = kzalloc(sizeof(*cpuclk), GFP_KERNEL); |
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if (WARN_ON(!cpuclk)) |
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return; |
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cpuclk->clk_ctrl = slcr_base + reg[0]; |
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clk_621 = slcr_base + reg[1]; |
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spin_lock_init(&cpuclk->clkact_lock); |
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init.name = np->name; |
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init.ops = &zynq_cpu_clk_ops; |
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for (i = 0; i < ARRAY_SIZE(parent_names); i++) |
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parent_names[i] = of_clk_get_parent_name(np, i); |
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init.parent_names = parent_names; |
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init.num_parents = ARRAY_SIZE(parent_names); |
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cpuclk->hw.init = &init; |
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clk = clk_register(NULL, &cpuclk->hw); |
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if (WARN_ON(IS_ERR(clk))) |
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return; |
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err = of_clk_add_provider(np, of_clk_src_simple_get, clk); |
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if (WARN_ON(err)) |
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return; |
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for (i = 0; i < 4; i++) { |
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cpuclk->subclks[i] = zynq_cpu_subclk_setup(np, i, clk_621); |
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if (WARN_ON(IS_ERR(cpuclk->subclks[i]))) |
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return; |
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} |
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cpuclk->onecell_data.clks = cpuclk->subclks; |
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cpuclk->onecell_data.clk_num = i; |
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err = of_clk_add_provider(np, of_clk_src_onecell_get, |
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&cpuclk->onecell_data); |
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if (WARN_ON(err)) |
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return; |
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} |
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CLK_OF_DECLARE(zynq_cpu, "xlnx,zynq-cpu-clock", zynq_cpu_clk_setup); |
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void __init xilinx_zynq_clocks_init(void __iomem *slcr) |
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{ |
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slcr_base = slcr; |
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of_clk_init(NULL); |
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} |
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@ -0,0 +1,3 @@ |
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# Zynq clock specific Makefile
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obj-$(CONFIG_ARCH_ZYNQ) += clkc.o pll.o
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@ -0,0 +1,533 @@ |
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/*
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* Zynq clock controller |
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* |
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* Copyright (C) 2012 - 2013 Xilinx |
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* |
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* Sören Brinkmann <soren.brinkmann@xilinx.com> |
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* |
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* This program is free software: you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License v2 as published by |
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* the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/ |
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#include <linux/clk/zynq.h> |
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#include <linux/clk-provider.h> |
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#include <linux/of.h> |
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#include <linux/slab.h> |
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#include <linux/string.h> |
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#include <linux/io.h> |
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static void __iomem *zynq_slcr_base_priv; |
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#define SLCR_ARMPLL_CTRL (zynq_slcr_base_priv + 0x100) |
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#define SLCR_DDRPLL_CTRL (zynq_slcr_base_priv + 0x104) |
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#define SLCR_IOPLL_CTRL (zynq_slcr_base_priv + 0x108) |
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#define SLCR_PLL_STATUS (zynq_slcr_base_priv + 0x10c) |
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#define SLCR_ARM_CLK_CTRL (zynq_slcr_base_priv + 0x120) |
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#define SLCR_DDR_CLK_CTRL (zynq_slcr_base_priv + 0x124) |
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#define SLCR_DCI_CLK_CTRL (zynq_slcr_base_priv + 0x128) |
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#define SLCR_APER_CLK_CTRL (zynq_slcr_base_priv + 0x12c) |
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#define SLCR_GEM0_CLK_CTRL (zynq_slcr_base_priv + 0x140) |
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#define SLCR_GEM1_CLK_CTRL (zynq_slcr_base_priv + 0x144) |
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#define SLCR_SMC_CLK_CTRL (zynq_slcr_base_priv + 0x148) |
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#define SLCR_LQSPI_CLK_CTRL (zynq_slcr_base_priv + 0x14c) |
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#define SLCR_SDIO_CLK_CTRL (zynq_slcr_base_priv + 0x150) |
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#define SLCR_UART_CLK_CTRL (zynq_slcr_base_priv + 0x154) |
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#define SLCR_SPI_CLK_CTRL (zynq_slcr_base_priv + 0x158) |
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#define SLCR_CAN_CLK_CTRL (zynq_slcr_base_priv + 0x15c) |
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#define SLCR_CAN_MIOCLK_CTRL (zynq_slcr_base_priv + 0x160) |
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#define SLCR_DBG_CLK_CTRL (zynq_slcr_base_priv + 0x164) |
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#define SLCR_PCAP_CLK_CTRL (zynq_slcr_base_priv + 0x168) |
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#define SLCR_FPGA0_CLK_CTRL (zynq_slcr_base_priv + 0x170) |
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#define SLCR_621_TRUE (zynq_slcr_base_priv + 0x1c4) |
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#define SLCR_SWDT_CLK_SEL (zynq_slcr_base_priv + 0x304) |
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|
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#define NUM_MIO_PINS 54 |
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|
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enum zynq_clk { |
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armpll, ddrpll, iopll, |
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cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x, |
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ddr2x, ddr3x, dci, |
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lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1, |
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sdio0, sdio1, uart0, uart1, spi0, spi1, dma, |
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usb0_aper, usb1_aper, gem0_aper, gem1_aper, |
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sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper, |
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i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper, |
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smc_aper, swdt, dbg_trc, dbg_apb, clk_max}; |
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|
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static struct clk *ps_clk; |
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static struct clk *clks[clk_max]; |
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static struct clk_onecell_data clk_data; |
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|
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static DEFINE_SPINLOCK(armpll_lock); |
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static DEFINE_SPINLOCK(ddrpll_lock); |
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static DEFINE_SPINLOCK(iopll_lock); |
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static DEFINE_SPINLOCK(armclk_lock); |
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static DEFINE_SPINLOCK(ddrclk_lock); |
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static DEFINE_SPINLOCK(dciclk_lock); |
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static DEFINE_SPINLOCK(gem0clk_lock); |
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static DEFINE_SPINLOCK(gem1clk_lock); |
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static DEFINE_SPINLOCK(canclk_lock); |
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static DEFINE_SPINLOCK(canmioclk_lock); |
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static DEFINE_SPINLOCK(dbgclk_lock); |
||||
static DEFINE_SPINLOCK(aperclk_lock); |
||||
|
||||
static const char dummy_nm[] __initconst = "dummy_name"; |
||||
|
||||
static const char *armpll_parents[] __initdata = {"armpll_int", "ps_clk"}; |
||||
static const char *ddrpll_parents[] __initdata = {"ddrpll_int", "ps_clk"}; |
||||
static const char *iopll_parents[] __initdata = {"iopll_int", "ps_clk"}; |
||||
static const char *gem0_mux_parents[] __initdata = {"gem0_div1", dummy_nm}; |
||||
static const char *gem1_mux_parents[] __initdata = {"gem1_div1", dummy_nm}; |
||||
static const char *can0_mio_mux2_parents[] __initdata = {"can0_gate", |
||||
"can0_mio_mux"}; |
||||
static const char *can1_mio_mux2_parents[] __initdata = {"can1_gate", |
||||
"can1_mio_mux"}; |
||||
static const char *dbg_emio_mux_parents[] __initdata = {"dbg_div", |
||||
dummy_nm}; |
||||
|
||||
static const char *dbgtrc_emio_input_names[] __initdata = {"trace_emio_clk"}; |
||||
static const char *gem0_emio_input_names[] __initdata = {"gem0_emio_clk"}; |
||||
static const char *gem1_emio_input_names[] __initdata = {"gem1_emio_clk"}; |
||||
static const char *swdt_ext_clk_input_names[] __initdata = {"swdt_ext_clk"}; |
||||
|
||||
static void __init zynq_clk_register_fclk(enum zynq_clk fclk, |
||||
const char *clk_name, void __iomem *fclk_ctrl_reg, |
||||
const char **parents) |
||||
{ |
||||
struct clk *clk; |
||||
char *mux_name; |
||||
char *div0_name; |
||||
char *div1_name; |
||||
spinlock_t *fclk_lock; |
||||
spinlock_t *fclk_gate_lock; |
||||
void __iomem *fclk_gate_reg = fclk_ctrl_reg + 8; |
||||
|
||||
fclk_lock = kmalloc(sizeof(*fclk_lock), GFP_KERNEL); |
||||
if (!fclk_lock) |
||||
goto err; |
||||
fclk_gate_lock = kmalloc(sizeof(*fclk_gate_lock), GFP_KERNEL); |
||||
if (!fclk_gate_lock) |
||||
goto err; |
||||
spin_lock_init(fclk_lock); |
||||
spin_lock_init(fclk_gate_lock); |
||||
|
||||
mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name); |
||||
div0_name = kasprintf(GFP_KERNEL, "%s_div0", clk_name); |
||||
div1_name = kasprintf(GFP_KERNEL, "%s_div1", clk_name); |
||||
|
||||
clk = clk_register_mux(NULL, mux_name, parents, 4, 0, |
||||
fclk_ctrl_reg, 4, 2, 0, fclk_lock); |
||||
|
||||
clk = clk_register_divider(NULL, div0_name, mux_name, |
||||
0, fclk_ctrl_reg, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, fclk_lock); |
||||
|
||||
clk = clk_register_divider(NULL, div1_name, div0_name, |
||||
CLK_SET_RATE_PARENT, fclk_ctrl_reg, 20, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
||||
fclk_lock); |
||||
|
||||
clks[fclk] = clk_register_gate(NULL, clk_name, |
||||
div1_name, CLK_SET_RATE_PARENT, fclk_gate_reg, |
||||
0, CLK_GATE_SET_TO_DISABLE, fclk_gate_lock); |
||||
kfree(mux_name); |
||||
kfree(div0_name); |
||||
kfree(div1_name); |
||||
|
||||
return; |
||||
|
||||
err: |
||||
clks[fclk] = ERR_PTR(-ENOMEM); |
||||
} |
||||
|
||||
static void __init zynq_clk_register_periph_clk(enum zynq_clk clk0, |
||||
enum zynq_clk clk1, const char *clk_name0, |
||||
const char *clk_name1, void __iomem *clk_ctrl, |
||||
const char **parents, unsigned int two_gates) |
||||
{ |
||||
struct clk *clk; |
||||
char *mux_name; |
||||
char *div_name; |
||||
spinlock_t *lock; |
||||
|
||||
lock = kmalloc(sizeof(*lock), GFP_KERNEL); |
||||
if (!lock) |
||||
goto err; |
||||
spin_lock_init(lock); |
||||
|
||||
mux_name = kasprintf(GFP_KERNEL, "%s_mux", clk_name0); |
||||
div_name = kasprintf(GFP_KERNEL, "%s_div", clk_name0); |
||||
|
||||
clk = clk_register_mux(NULL, mux_name, parents, 4, 0, |
||||
clk_ctrl, 4, 2, 0, lock); |
||||
|
||||
clk = clk_register_divider(NULL, div_name, mux_name, 0, clk_ctrl, 8, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, lock); |
||||
|
||||
clks[clk0] = clk_register_gate(NULL, clk_name0, div_name, |
||||
CLK_SET_RATE_PARENT, clk_ctrl, 0, 0, lock); |
||||
if (two_gates) |
||||
clks[clk1] = clk_register_gate(NULL, clk_name1, div_name, |
||||
CLK_SET_RATE_PARENT, clk_ctrl, 1, 0, lock); |
||||
|
||||
kfree(mux_name); |
||||
kfree(div_name); |
||||
|
||||
return; |
||||
|
||||
err: |
||||
clks[clk0] = ERR_PTR(-ENOMEM); |
||||
if (two_gates) |
||||
clks[clk1] = ERR_PTR(-ENOMEM); |
||||
} |
||||
|
||||
static void __init zynq_clk_setup(struct device_node *np) |
||||
{ |
||||
int i; |
||||
u32 tmp; |
||||
int ret; |
||||
struct clk *clk; |
||||
char *clk_name; |
||||
const char *clk_output_name[clk_max]; |
||||
const char *cpu_parents[4]; |
||||
const char *periph_parents[4]; |
||||
const char *swdt_ext_clk_mux_parents[2]; |
||||
const char *can_mio_mux_parents[NUM_MIO_PINS]; |
||||
|
||||
pr_info("Zynq clock init\n"); |
||||
|
||||
/* get clock output names from DT */ |
||||
for (i = 0; i < clk_max; i++) { |
||||
if (of_property_read_string_index(np, "clock-output-names", |
||||
i, &clk_output_name[i])) { |
||||
pr_err("%s: clock output name not in DT\n", __func__); |
||||
BUG(); |
||||
} |
||||
} |
||||
cpu_parents[0] = clk_output_name[armpll]; |
||||
cpu_parents[1] = clk_output_name[armpll]; |
||||
cpu_parents[2] = clk_output_name[ddrpll]; |
||||
cpu_parents[3] = clk_output_name[iopll]; |
||||
periph_parents[0] = clk_output_name[iopll]; |
||||
periph_parents[1] = clk_output_name[iopll]; |
||||
periph_parents[2] = clk_output_name[armpll]; |
||||
periph_parents[3] = clk_output_name[ddrpll]; |
||||
|
||||
/* ps_clk */ |
||||
ret = of_property_read_u32(np, "ps-clk-frequency", &tmp); |
||||
if (ret) { |
||||
pr_warn("ps_clk frequency not specified, using 33 MHz.\n"); |
||||
tmp = 33333333; |
||||
} |
||||
ps_clk = clk_register_fixed_rate(NULL, "ps_clk", NULL, CLK_IS_ROOT, |
||||
tmp); |
||||
|
||||
/* PLLs */ |
||||
clk = clk_register_zynq_pll("armpll_int", "ps_clk", SLCR_ARMPLL_CTRL, |
||||
SLCR_PLL_STATUS, 0, &armpll_lock); |
||||
clks[armpll] = clk_register_mux(NULL, clk_output_name[armpll], |
||||
armpll_parents, 2, 0, SLCR_ARMPLL_CTRL, 4, 1, 0, |
||||
&armpll_lock); |
||||
|
||||
clk = clk_register_zynq_pll("ddrpll_int", "ps_clk", SLCR_DDRPLL_CTRL, |
||||
SLCR_PLL_STATUS, 1, &ddrpll_lock); |
||||
clks[ddrpll] = clk_register_mux(NULL, clk_output_name[ddrpll], |
||||
ddrpll_parents, 2, 0, SLCR_DDRPLL_CTRL, 4, 1, 0, |
||||
&ddrpll_lock); |
||||
|
||||
clk = clk_register_zynq_pll("iopll_int", "ps_clk", SLCR_IOPLL_CTRL, |
||||
SLCR_PLL_STATUS, 2, &iopll_lock); |
||||
clks[iopll] = clk_register_mux(NULL, clk_output_name[iopll], |
||||
iopll_parents, 2, 0, SLCR_IOPLL_CTRL, 4, 1, 0, |
||||
&iopll_lock); |
||||
|
||||
/* CPU clocks */ |
||||
tmp = readl(SLCR_621_TRUE) & 1; |
||||
clk = clk_register_mux(NULL, "cpu_mux", cpu_parents, 4, 0, |
||||
SLCR_ARM_CLK_CTRL, 4, 2, 0, &armclk_lock); |
||||
clk = clk_register_divider(NULL, "cpu_div", "cpu_mux", 0, |
||||
SLCR_ARM_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &armclk_lock); |
||||
|
||||
clks[cpu_6or4x] = clk_register_gate(NULL, clk_output_name[cpu_6or4x], |
||||
"cpu_div", CLK_SET_RATE_PARENT | CLK_IGNORE_UNUSED, |
||||
SLCR_ARM_CLK_CTRL, 24, 0, &armclk_lock); |
||||
|
||||
clk = clk_register_fixed_factor(NULL, "cpu_3or2x_div", "cpu_div", 0, |
||||
1, 2); |
||||
clks[cpu_3or2x] = clk_register_gate(NULL, clk_output_name[cpu_3or2x], |
||||
"cpu_3or2x_div", CLK_IGNORE_UNUSED, |
||||
SLCR_ARM_CLK_CTRL, 25, 0, &armclk_lock); |
||||
|
||||
clk = clk_register_fixed_factor(NULL, "cpu_2x_div", "cpu_div", 0, 1, |
||||
2 + tmp); |
||||
clks[cpu_2x] = clk_register_gate(NULL, clk_output_name[cpu_2x], |
||||
"cpu_2x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, |
||||
26, 0, &armclk_lock); |
||||
|
||||
clk = clk_register_fixed_factor(NULL, "cpu_1x_div", "cpu_div", 0, 1, |
||||
4 + 2 * tmp); |
||||
clks[cpu_1x] = clk_register_gate(NULL, clk_output_name[cpu_1x], |
||||
"cpu_1x_div", CLK_IGNORE_UNUSED, SLCR_ARM_CLK_CTRL, 27, |
||||
0, &armclk_lock); |
||||
|
||||
/* Timers */ |
||||
swdt_ext_clk_mux_parents[0] = clk_output_name[cpu_1x]; |
||||
for (i = 0; i < ARRAY_SIZE(swdt_ext_clk_input_names); i++) { |
||||
int idx = of_property_match_string(np, "clock-names", |
||||
swdt_ext_clk_input_names[i]); |
||||
if (idx >= 0) |
||||
swdt_ext_clk_mux_parents[i + 1] = |
||||
of_clk_get_parent_name(np, idx); |
||||
else |
||||
swdt_ext_clk_mux_parents[i + 1] = dummy_nm; |
||||
} |
||||
clks[swdt] = clk_register_mux(NULL, clk_output_name[swdt], |
||||
swdt_ext_clk_mux_parents, 2, CLK_SET_RATE_PARENT, |
||||
SLCR_SWDT_CLK_SEL, 0, 1, 0, &gem0clk_lock); |
||||
|
||||
/* DDR clocks */ |
||||
clk = clk_register_divider(NULL, "ddr2x_div", "ddrpll", 0, |
||||
SLCR_DDR_CLK_CTRL, 26, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); |
||||
clks[ddr2x] = clk_register_gate(NULL, clk_output_name[ddr2x], |
||||
"ddr2x_div", 0, SLCR_DDR_CLK_CTRL, 1, 0, &ddrclk_lock); |
||||
clk_prepare_enable(clks[ddr2x]); |
||||
clk = clk_register_divider(NULL, "ddr3x_div", "ddrpll", 0, |
||||
SLCR_DDR_CLK_CTRL, 20, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &ddrclk_lock); |
||||
clks[ddr3x] = clk_register_gate(NULL, clk_output_name[ddr3x], |
||||
"ddr3x_div", 0, SLCR_DDR_CLK_CTRL, 0, 0, &ddrclk_lock); |
||||
clk_prepare_enable(clks[ddr3x]); |
||||
|
||||
clk = clk_register_divider(NULL, "dci_div0", "ddrpll", 0, |
||||
SLCR_DCI_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &dciclk_lock); |
||||
clk = clk_register_divider(NULL, "dci_div1", "dci_div0", |
||||
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 20, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
||||
&dciclk_lock); |
||||
clks[dci] = clk_register_gate(NULL, clk_output_name[dci], "dci_div1", |
||||
CLK_SET_RATE_PARENT, SLCR_DCI_CLK_CTRL, 0, 0, |
||||
&dciclk_lock); |
||||
clk_prepare_enable(clks[dci]); |
||||
|
||||
/* Peripheral clocks */ |
||||
for (i = fclk0; i <= fclk3; i++) |
||||
zynq_clk_register_fclk(i, clk_output_name[i], |
||||
SLCR_FPGA0_CLK_CTRL + 0x10 * (i - fclk0), |
||||
periph_parents); |
||||
|
||||
zynq_clk_register_periph_clk(lqspi, 0, clk_output_name[lqspi], NULL, |
||||
SLCR_LQSPI_CLK_CTRL, periph_parents, 0); |
||||
|
||||
zynq_clk_register_periph_clk(smc, 0, clk_output_name[smc], NULL, |
||||
SLCR_SMC_CLK_CTRL, periph_parents, 0); |
||||
|
||||
zynq_clk_register_periph_clk(pcap, 0, clk_output_name[pcap], NULL, |
||||
SLCR_PCAP_CLK_CTRL, periph_parents, 0); |
||||
|
||||
zynq_clk_register_periph_clk(sdio0, sdio1, clk_output_name[sdio0], |
||||
clk_output_name[sdio1], SLCR_SDIO_CLK_CTRL, |
||||
periph_parents, 1); |
||||
|
||||
zynq_clk_register_periph_clk(uart0, uart1, clk_output_name[uart0], |
||||
clk_output_name[uart1], SLCR_UART_CLK_CTRL, |
||||
periph_parents, 1); |
||||
|
||||
zynq_clk_register_periph_clk(spi0, spi1, clk_output_name[spi0], |
||||
clk_output_name[spi1], SLCR_SPI_CLK_CTRL, |
||||
periph_parents, 1); |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gem0_emio_input_names); i++) { |
||||
int idx = of_property_match_string(np, "clock-names", |
||||
gem0_emio_input_names[i]); |
||||
if (idx >= 0) |
||||
gem0_mux_parents[i + 1] = of_clk_get_parent_name(np, |
||||
idx); |
||||
} |
||||
clk = clk_register_mux(NULL, "gem0_mux", periph_parents, 4, 0, |
||||
SLCR_GEM0_CLK_CTRL, 4, 2, 0, &gem0clk_lock); |
||||
clk = clk_register_divider(NULL, "gem0_div0", "gem0_mux", 0, |
||||
SLCR_GEM0_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &gem0clk_lock); |
||||
clk = clk_register_divider(NULL, "gem0_div1", "gem0_div0", |
||||
CLK_SET_RATE_PARENT, SLCR_GEM0_CLK_CTRL, 20, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
||||
&gem0clk_lock); |
||||
clk = clk_register_mux(NULL, "gem0_emio_mux", gem0_mux_parents, 2, 0, |
||||
SLCR_GEM0_CLK_CTRL, 6, 1, 0, &gem0clk_lock); |
||||
clks[gem0] = clk_register_gate(NULL, clk_output_name[gem0], |
||||
"gem0_emio_mux", CLK_SET_RATE_PARENT, |
||||
SLCR_GEM0_CLK_CTRL, 0, 0, &gem0clk_lock); |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(gem1_emio_input_names); i++) { |
||||
int idx = of_property_match_string(np, "clock-names", |
||||
gem1_emio_input_names[i]); |
||||
if (idx >= 0) |
||||
gem1_mux_parents[i + 1] = of_clk_get_parent_name(np, |
||||
idx); |
||||
} |
||||
clk = clk_register_mux(NULL, "gem1_mux", periph_parents, 4, 0, |
||||
SLCR_GEM1_CLK_CTRL, 4, 2, 0, &gem1clk_lock); |
||||
clk = clk_register_divider(NULL, "gem1_div0", "gem1_mux", 0, |
||||
SLCR_GEM1_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &gem1clk_lock); |
||||
clk = clk_register_divider(NULL, "gem1_div1", "gem1_div0", |
||||
CLK_SET_RATE_PARENT, SLCR_GEM1_CLK_CTRL, 20, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
||||
&gem1clk_lock); |
||||
clk = clk_register_mux(NULL, "gem1_emio_mux", gem1_mux_parents, 2, 0, |
||||
SLCR_GEM1_CLK_CTRL, 6, 1, 0, &gem1clk_lock); |
||||
clks[gem1] = clk_register_gate(NULL, clk_output_name[gem1], |
||||
"gem1_emio_mux", CLK_SET_RATE_PARENT, |
||||
SLCR_GEM1_CLK_CTRL, 0, 0, &gem1clk_lock); |
||||
|
||||
tmp = strlen("mio_clk_00x"); |
||||
clk_name = kmalloc(tmp, GFP_KERNEL); |
||||
for (i = 0; i < NUM_MIO_PINS; i++) { |
||||
int idx; |
||||
|
||||
snprintf(clk_name, tmp, "mio_clk_%2.2d", i); |
||||
idx = of_property_match_string(np, "clock-names", clk_name); |
||||
if (idx >= 0) |
||||
can_mio_mux_parents[i] = of_clk_get_parent_name(np, |
||||
idx); |
||||
else |
||||
can_mio_mux_parents[i] = dummy_nm; |
||||
} |
||||
kfree(clk_name); |
||||
clk = clk_register_mux(NULL, "can_mux", periph_parents, 4, 0, |
||||
SLCR_CAN_CLK_CTRL, 4, 2, 0, &canclk_lock); |
||||
clk = clk_register_divider(NULL, "can_div0", "can_mux", 0, |
||||
SLCR_CAN_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &canclk_lock); |
||||
clk = clk_register_divider(NULL, "can_div1", "can_div0", |
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 20, 6, |
||||
CLK_DIVIDER_ONE_BASED | CLK_DIVIDER_ALLOW_ZERO, |
||||
&canclk_lock); |
||||
clk = clk_register_gate(NULL, "can0_gate", "can_div1", |
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 0, 0, |
||||
&canclk_lock); |
||||
clk = clk_register_gate(NULL, "can1_gate", "can_div1", |
||||
CLK_SET_RATE_PARENT, SLCR_CAN_CLK_CTRL, 1, 0, |
||||
&canclk_lock); |
||||
clk = clk_register_mux(NULL, "can0_mio_mux", |
||||
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, |
||||
SLCR_CAN_MIOCLK_CTRL, 0, 6, 0, &canmioclk_lock); |
||||
clk = clk_register_mux(NULL, "can1_mio_mux", |
||||
can_mio_mux_parents, 54, CLK_SET_RATE_PARENT, |
||||
SLCR_CAN_MIOCLK_CTRL, 16, 6, 0, &canmioclk_lock); |
||||
clks[can0] = clk_register_mux(NULL, clk_output_name[can0], |
||||
can0_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, |
||||
SLCR_CAN_MIOCLK_CTRL, 6, 1, 0, &canmioclk_lock); |
||||
clks[can1] = clk_register_mux(NULL, clk_output_name[can1], |
||||
can1_mio_mux2_parents, 2, CLK_SET_RATE_PARENT, |
||||
SLCR_CAN_MIOCLK_CTRL, 22, 1, 0, &canmioclk_lock); |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(dbgtrc_emio_input_names); i++) { |
||||
int idx = of_property_match_string(np, "clock-names", |
||||
dbgtrc_emio_input_names[i]); |
||||
if (idx >= 0) |
||||
dbg_emio_mux_parents[i + 1] = of_clk_get_parent_name(np, |
||||
idx); |
||||
} |
||||
clk = clk_register_mux(NULL, "dbg_mux", periph_parents, 4, 0, |
||||
SLCR_DBG_CLK_CTRL, 4, 2, 0, &dbgclk_lock); |
||||
clk = clk_register_divider(NULL, "dbg_div", "dbg_mux", 0, |
||||
SLCR_DBG_CLK_CTRL, 8, 6, CLK_DIVIDER_ONE_BASED | |
||||
CLK_DIVIDER_ALLOW_ZERO, &dbgclk_lock); |
||||
clk = clk_register_mux(NULL, "dbg_emio_mux", dbg_emio_mux_parents, 2, 0, |
||||
SLCR_DBG_CLK_CTRL, 6, 1, 0, &dbgclk_lock); |
||||
clks[dbg_trc] = clk_register_gate(NULL, clk_output_name[dbg_trc], |
||||
"dbg_emio_mux", CLK_SET_RATE_PARENT, SLCR_DBG_CLK_CTRL, |
||||
0, 0, &dbgclk_lock); |
||||
clks[dbg_apb] = clk_register_gate(NULL, clk_output_name[dbg_apb], |
||||
clk_output_name[cpu_1x], 0, SLCR_DBG_CLK_CTRL, 1, 0, |
||||
&dbgclk_lock); |
||||
|
||||
/* One gated clock for all APER clocks. */ |
||||
clks[dma] = clk_register_gate(NULL, clk_output_name[dma], |
||||
clk_output_name[cpu_2x], 0, SLCR_APER_CLK_CTRL, 0, 0, |
||||
&aperclk_lock); |
||||
clks[usb0_aper] = clk_register_gate(NULL, clk_output_name[usb0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 2, 0, |
||||
&aperclk_lock); |
||||
clks[usb1_aper] = clk_register_gate(NULL, clk_output_name[usb1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 3, 0, |
||||
&aperclk_lock); |
||||
clks[gem0_aper] = clk_register_gate(NULL, clk_output_name[gem0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 6, 0, |
||||
&aperclk_lock); |
||||
clks[gem1_aper] = clk_register_gate(NULL, clk_output_name[gem1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 7, 0, |
||||
&aperclk_lock); |
||||
clks[sdio0_aper] = clk_register_gate(NULL, clk_output_name[sdio0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 10, 0, |
||||
&aperclk_lock); |
||||
clks[sdio1_aper] = clk_register_gate(NULL, clk_output_name[sdio1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 11, 0, |
||||
&aperclk_lock); |
||||
clks[spi0_aper] = clk_register_gate(NULL, clk_output_name[spi0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 14, 0, |
||||
&aperclk_lock); |
||||
clks[spi1_aper] = clk_register_gate(NULL, clk_output_name[spi1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 15, 0, |
||||
&aperclk_lock); |
||||
clks[can0_aper] = clk_register_gate(NULL, clk_output_name[can0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 16, 0, |
||||
&aperclk_lock); |
||||
clks[can1_aper] = clk_register_gate(NULL, clk_output_name[can1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 17, 0, |
||||
&aperclk_lock); |
||||
clks[i2c0_aper] = clk_register_gate(NULL, clk_output_name[i2c0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 18, 0, |
||||
&aperclk_lock); |
||||
clks[i2c1_aper] = clk_register_gate(NULL, clk_output_name[i2c1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 19, 0, |
||||
&aperclk_lock); |
||||
clks[uart0_aper] = clk_register_gate(NULL, clk_output_name[uart0_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 20, 0, |
||||
&aperclk_lock); |
||||
clks[uart1_aper] = clk_register_gate(NULL, clk_output_name[uart1_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 21, 0, |
||||
&aperclk_lock); |
||||
clks[gpio_aper] = clk_register_gate(NULL, clk_output_name[gpio_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 22, 0, |
||||
&aperclk_lock); |
||||
clks[lqspi_aper] = clk_register_gate(NULL, clk_output_name[lqspi_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 23, 0, |
||||
&aperclk_lock); |
||||
clks[smc_aper] = clk_register_gate(NULL, clk_output_name[smc_aper], |
||||
clk_output_name[cpu_1x], 0, SLCR_APER_CLK_CTRL, 24, 0, |
||||
&aperclk_lock); |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(clks); i++) { |
||||
if (IS_ERR(clks[i])) { |
||||
pr_err("Zynq clk %d: register failed with %ld\n", |
||||
i, PTR_ERR(clks[i])); |
||||
BUG(); |
||||
} |
||||
} |
||||
|
||||
clk_data.clks = clks; |
||||
clk_data.clk_num = ARRAY_SIZE(clks); |
||||
of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); |
||||
} |
||||
|
||||
CLK_OF_DECLARE(zynq_clkc, "xlnx,ps7-clkc", zynq_clk_setup); |
||||
|
||||
void __init zynq_clock_init(void __iomem *slcr_base) |
||||
{ |
||||
zynq_slcr_base_priv = slcr_base; |
||||
of_clk_init(NULL); |
||||
} |
||||
@ -0,0 +1,235 @@ |
||||
/*
|
||||
* Zynq PLL driver |
||||
* |
||||
* Copyright (C) 2013 Xilinx |
||||
* |
||||
* Sören Brinkmann <soren.brinkmann@xilinx.com> |
||||
* |
||||
* This program is free software: you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License v2 as published by |
||||
* the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program. If not, see <http://www.gnu.org/licenses/>.
|
||||
* |
||||
*/ |
||||
#include <linux/clk/zynq.h> |
||||
#include <linux/clk-provider.h> |
||||
#include <linux/slab.h> |
||||
#include <linux/io.h> |
||||
|
||||
/**
|
||||
* struct zynq_pll |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* @pll_ctrl: PLL control register |
||||
* @pll_status: PLL status register |
||||
* @lock: Register lock |
||||
* @lockbit: Indicates the associated PLL_LOCKED bit in the PLL status |
||||
* register. |
||||
*/ |
||||
struct zynq_pll { |
||||
struct clk_hw hw; |
||||
void __iomem *pll_ctrl; |
||||
void __iomem *pll_status; |
||||
spinlock_t *lock; |
||||
u8 lockbit; |
||||
}; |
||||
#define to_zynq_pll(_hw) container_of(_hw, struct zynq_pll, hw) |
||||
|
||||
/* Register bitfield defines */ |
||||
#define PLLCTRL_FBDIV_MASK 0x7f000 |
||||
#define PLLCTRL_FBDIV_SHIFT 12 |
||||
#define PLLCTRL_BPQUAL_MASK (1 << 3) |
||||
#define PLLCTRL_PWRDWN_MASK 2 |
||||
#define PLLCTRL_PWRDWN_SHIFT 1 |
||||
#define PLLCTRL_RESET_MASK 1 |
||||
#define PLLCTRL_RESET_SHIFT 0 |
||||
|
||||
/**
|
||||
* zynq_pll_round_rate() - Round a clock frequency |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* @rate: Desired clock frequency |
||||
* @prate: Clock frequency of parent clock |
||||
* Returns frequency closest to @rate the hardware can generate. |
||||
*/ |
||||
static long zynq_pll_round_rate(struct clk_hw *hw, unsigned long rate, |
||||
unsigned long *prate) |
||||
{ |
||||
u32 fbdiv; |
||||
|
||||
fbdiv = DIV_ROUND_CLOSEST(rate, *prate); |
||||
if (fbdiv < 13) |
||||
fbdiv = 13; |
||||
else if (fbdiv > 66) |
||||
fbdiv = 66; |
||||
|
||||
return *prate * fbdiv; |
||||
} |
||||
|
||||
/**
|
||||
* zynq_pll_recalc_rate() - Recalculate clock frequency |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* @parent_rate: Clock frequency of parent clock |
||||
* Returns current clock frequency. |
||||
*/ |
||||
static unsigned long zynq_pll_recalc_rate(struct clk_hw *hw, |
||||
unsigned long parent_rate) |
||||
{ |
||||
struct zynq_pll *clk = to_zynq_pll(hw); |
||||
u32 fbdiv; |
||||
|
||||
/*
|
||||
* makes probably sense to redundantly save fbdiv in the struct |
||||
* zynq_pll to save the IO access. |
||||
*/ |
||||
fbdiv = (readl(clk->pll_ctrl) & PLLCTRL_FBDIV_MASK) >> |
||||
PLLCTRL_FBDIV_SHIFT; |
||||
|
||||
return parent_rate * fbdiv; |
||||
} |
||||
|
||||
/**
|
||||
* zynq_pll_is_enabled - Check if a clock is enabled |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* Returns 1 if the clock is enabled, 0 otherwise. |
||||
* |
||||
* Not sure this is a good idea, but since disabled means bypassed for |
||||
* this clock implementation we say we are always enabled. |
||||
*/ |
||||
static int zynq_pll_is_enabled(struct clk_hw *hw) |
||||
{ |
||||
unsigned long flags = 0; |
||||
u32 reg; |
||||
struct zynq_pll *clk = to_zynq_pll(hw); |
||||
|
||||
spin_lock_irqsave(clk->lock, flags); |
||||
|
||||
reg = readl(clk->pll_ctrl); |
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags); |
||||
|
||||
return !(reg & (PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK)); |
||||
} |
||||
|
||||
/**
|
||||
* zynq_pll_enable - Enable clock |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* Returns 0 on success |
||||
*/ |
||||
static int zynq_pll_enable(struct clk_hw *hw) |
||||
{ |
||||
unsigned long flags = 0; |
||||
u32 reg; |
||||
struct zynq_pll *clk = to_zynq_pll(hw); |
||||
|
||||
if (zynq_pll_is_enabled(hw)) |
||||
return 0; |
||||
|
||||
pr_info("PLL: enable\n"); |
||||
|
||||
/* Power up PLL and wait for lock */ |
||||
spin_lock_irqsave(clk->lock, flags); |
||||
|
||||
reg = readl(clk->pll_ctrl); |
||||
reg &= ~(PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK); |
||||
writel(reg, clk->pll_ctrl); |
||||
while (!(readl(clk->pll_status) & (1 << clk->lockbit))) |
||||
; |
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/**
|
||||
* zynq_pll_disable - Disable clock |
||||
* @hw: Handle between common and hardware-specific interfaces |
||||
* Returns 0 on success |
||||
*/ |
||||
static void zynq_pll_disable(struct clk_hw *hw) |
||||
{ |
||||
unsigned long flags = 0; |
||||
u32 reg; |
||||
struct zynq_pll *clk = to_zynq_pll(hw); |
||||
|
||||
if (!zynq_pll_is_enabled(hw)) |
||||
return; |
||||
|
||||
pr_info("PLL: shutdown\n"); |
||||
|
||||
/* shut down PLL */ |
||||
spin_lock_irqsave(clk->lock, flags); |
||||
|
||||
reg = readl(clk->pll_ctrl); |
||||
reg |= PLLCTRL_RESET_MASK | PLLCTRL_PWRDWN_MASK; |
||||
writel(reg, clk->pll_ctrl); |
||||
|
||||
spin_unlock_irqrestore(clk->lock, flags); |
||||
} |
||||
|
||||
static const struct clk_ops zynq_pll_ops = { |
||||
.enable = zynq_pll_enable, |
||||
.disable = zynq_pll_disable, |
||||
.is_enabled = zynq_pll_is_enabled, |
||||
.round_rate = zynq_pll_round_rate, |
||||
.recalc_rate = zynq_pll_recalc_rate |
||||
}; |
||||
|
||||
/**
|
||||
* clk_register_zynq_pll() - Register PLL with the clock framework |
||||
* @np Pointer to the DT device node |
||||
*/ |
||||
struct clk *clk_register_zynq_pll(const char *name, const char *parent, |
||||
void __iomem *pll_ctrl, void __iomem *pll_status, u8 lock_index, |
||||
spinlock_t *lock) |
||||
{ |
||||
struct zynq_pll *pll; |
||||
struct clk *clk; |
||||
u32 reg; |
||||
const char *parent_arr[1] = {parent}; |
||||
unsigned long flags = 0; |
||||
struct clk_init_data initd = { |
||||
.name = name, |
||||
.parent_names = parent_arr, |
||||
.ops = &zynq_pll_ops, |
||||
.num_parents = 1, |
||||
.flags = 0 |
||||
}; |
||||
|
||||
pll = kmalloc(sizeof(*pll), GFP_KERNEL); |
||||
if (!pll) { |
||||
pr_err("%s: Could not allocate Zynq PLL clk.\n", __func__); |
||||
return ERR_PTR(-ENOMEM); |
||||
} |
||||
|
||||
/* Populate the struct */ |
||||
pll->hw.init = &initd; |
||||
pll->pll_ctrl = pll_ctrl; |
||||
pll->pll_status = pll_status; |
||||
pll->lockbit = lock_index; |
||||
pll->lock = lock; |
||||
|
||||
spin_lock_irqsave(pll->lock, flags); |
||||
|
||||
reg = readl(pll->pll_ctrl); |
||||
reg &= ~PLLCTRL_BPQUAL_MASK; |
||||
writel(reg, pll->pll_ctrl); |
||||
|
||||
spin_unlock_irqrestore(pll->lock, flags); |
||||
|
||||
clk = clk_register(NULL, &pll->hw); |
||||
if (WARN_ON(IS_ERR(clk))) |
||||
goto free_pll; |
||||
|
||||
return clk; |
||||
|
||||
free_pll: |
||||
kfree(pll); |
||||
|
||||
return clk; |
||||
} |
||||
Loading…
Reference in new issue