The high-speed phy on qcom SoCs is controlled via the ULPI viewport. Cc: Kishon Vijay Abraham I <kishon@ti.com> Cc: <devicetree@vger.kernel.org> Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Stephen Boyd <stephen.boyd@linaro.org> Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>tirimbino
Stephen Boyd
8 years ago
committed by
Kishon Vijay Abraham I
parent
605b8652f7
commit
e2427b09ba
@ -0,0 +1,84 @@ |
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Qualcomm's USB HS PHY |
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|
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PROPERTIES |
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|
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- compatible: |
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Usage: required |
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Value type: <string> |
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Definition: Should contain "qcom,usb-hs-phy" and more specifically one of the |
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following: |
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|
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"qcom,usb-hs-phy-apq8064" |
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"qcom,usb-hs-phy-msm8916" |
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"qcom,usb-hs-phy-msm8974" |
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|
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- #phy-cells: |
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Usage: required |
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Value type: <u32> |
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Definition: Should contain 0 |
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|
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- clocks: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Should contain clock specifier for the reference and sleep |
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clocks |
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|
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- clock-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Should contain "ref" and "sleep" for the reference and sleep |
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clocks respectively |
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|
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- resets: |
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Usage: required |
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Value type: <prop-encoded-array> |
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Definition: Should contain the phy and POR resets |
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|
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- reset-names: |
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Usage: required |
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Value type: <stringlist> |
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Definition: Should contain "phy" and "por" for the phy and POR resets |
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respectively |
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|
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- v3p3-supply: |
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Usage: required |
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Value type: <phandle> |
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Definition: Should contain a reference to the 3.3V supply |
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|
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- v1p8-supply: |
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Usage: required |
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Value type: <phandle> |
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Definition: Should contain a reference to the 1.8V supply |
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|
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- extcon: |
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Usage: optional |
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Value type: <prop-encoded-array> |
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Definition: Should contain the vbus extcon |
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|
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- qcom,init-seq: |
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Usage: optional |
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Value type: <u8 array> |
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Definition: Should contain a sequence of ULPI address and value pairs to |
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program into the ULPI_EXT_VENDOR_SPECIFIC area. This is related |
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to Device Mode Eye Diagram test. The addresses are offsets |
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from the ULPI_EXT_VENDOR_SPECIFIC address, for example, |
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<0x1 0x53> would mean "write the value 0x53 to address 0x81". |
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|
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EXAMPLE |
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otg: usb-controller { |
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ulpi { |
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phy { |
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compatible = "qcom,usb-hs-phy-msm8974", "qcom,usb-hs-phy"; |
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#phy-cells = <0>; |
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clocks = <&xo_board>, <&gcc GCC_USB2A_PHY_SLEEP_CLK>; |
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clock-names = "ref", "sleep"; |
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resets = <&gcc GCC_USB2A_PHY_BCR>, <&otg 0>; |
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reset-names = "phy", "por"; |
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v3p3-supply = <&pm8941_l24>; |
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v1p8-supply = <&pm8941_l6>; |
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extcon = <&smbb>; |
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qcom,init-seq = /bits/ 8 <0x1 0x63>; |
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}; |
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}; |
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}; |
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@ -0,0 +1,296 @@ |
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/**
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* Copyright (C) 2016 Linaro Ltd |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <linux/module.h> |
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#include <linux/ulpi/driver.h> |
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#include <linux/ulpi/regs.h> |
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#include <linux/clk.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/of_device.h> |
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#include <linux/reset.h> |
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#include <linux/extcon.h> |
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#include <linux/notifier.h> |
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#include "ulpi_phy.h" |
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#define ULPI_PWR_CLK_MNG_REG 0x88 |
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# define ULPI_PWR_OTG_COMP_DISABLE BIT(0) |
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#define ULPI_MISC_A 0x96 |
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# define ULPI_MISC_A_VBUSVLDEXTSEL BIT(1) |
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# define ULPI_MISC_A_VBUSVLDEXT BIT(0) |
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|
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struct ulpi_seq { |
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u8 addr; |
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u8 val; |
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}; |
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|
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struct qcom_usb_hs_phy { |
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struct ulpi *ulpi; |
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struct phy *phy; |
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struct clk *ref_clk; |
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struct clk *sleep_clk; |
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struct regulator *v1p8; |
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struct regulator *v3p3; |
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struct reset_control *reset; |
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struct ulpi_seq *init_seq; |
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struct extcon_dev *vbus_edev; |
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struct notifier_block vbus_notify; |
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}; |
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static int qcom_usb_hs_phy_set_mode(struct phy *phy, enum phy_mode mode) |
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{ |
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struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy); |
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u8 addr; |
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int ret; |
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if (!uphy->vbus_edev) { |
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u8 val = 0; |
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switch (mode) { |
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case PHY_MODE_USB_OTG: |
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case PHY_MODE_USB_HOST: |
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val |= ULPI_INT_IDGRD; |
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case PHY_MODE_USB_DEVICE: |
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val |= ULPI_INT_SESS_VALID; |
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default: |
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break; |
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} |
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ret = ulpi_write(uphy->ulpi, ULPI_USB_INT_EN_RISE, val); |
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if (ret) |
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return ret; |
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ret = ulpi_write(uphy->ulpi, ULPI_USB_INT_EN_FALL, val); |
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} else { |
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switch (mode) { |
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case PHY_MODE_USB_OTG: |
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case PHY_MODE_USB_DEVICE: |
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addr = ULPI_SET(ULPI_MISC_A); |
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break; |
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case PHY_MODE_USB_HOST: |
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addr = ULPI_CLR(ULPI_MISC_A); |
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break; |
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default: |
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return -EINVAL; |
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} |
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ret = ulpi_write(uphy->ulpi, ULPI_SET(ULPI_PWR_CLK_MNG_REG), |
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ULPI_PWR_OTG_COMP_DISABLE); |
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if (ret) |
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return ret; |
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ret = ulpi_write(uphy->ulpi, addr, ULPI_MISC_A_VBUSVLDEXTSEL); |
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} |
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return ret; |
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} |
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static int |
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qcom_usb_hs_phy_vbus_notifier(struct notifier_block *nb, unsigned long event, |
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void *ptr) |
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{ |
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struct qcom_usb_hs_phy *uphy; |
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u8 addr; |
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uphy = container_of(nb, struct qcom_usb_hs_phy, vbus_notify); |
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if (event) |
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addr = ULPI_SET(ULPI_MISC_A); |
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else |
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addr = ULPI_CLR(ULPI_MISC_A); |
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return ulpi_write(uphy->ulpi, addr, ULPI_MISC_A_VBUSVLDEXT); |
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} |
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static int qcom_usb_hs_phy_power_on(struct phy *phy) |
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{ |
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struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy); |
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struct ulpi *ulpi = uphy->ulpi; |
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const struct ulpi_seq *seq; |
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int ret, state; |
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ret = clk_prepare_enable(uphy->ref_clk); |
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if (ret) |
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return ret; |
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ret = clk_prepare_enable(uphy->sleep_clk); |
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if (ret) |
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goto err_sleep; |
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ret = regulator_set_load(uphy->v1p8, 50000); |
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if (ret < 0) |
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goto err_1p8; |
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ret = regulator_enable(uphy->v1p8); |
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if (ret) |
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goto err_1p8; |
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ret = regulator_set_voltage_triplet(uphy->v3p3, 3050000, 3300000, |
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3300000); |
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if (ret) |
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goto err_3p3; |
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ret = regulator_set_load(uphy->v3p3, 50000); |
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if (ret < 0) |
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goto err_3p3; |
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ret = regulator_enable(uphy->v3p3); |
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if (ret) |
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goto err_3p3; |
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for (seq = uphy->init_seq; seq->addr; seq++) { |
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ret = ulpi_write(ulpi, ULPI_EXT_VENDOR_SPECIFIC + seq->addr, |
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seq->val); |
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if (ret) |
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goto err_ulpi; |
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} |
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if (uphy->reset) { |
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ret = reset_control_reset(uphy->reset); |
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if (ret) |
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goto err_ulpi; |
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} |
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if (uphy->vbus_edev) { |
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state = extcon_get_cable_state_(uphy->vbus_edev, EXTCON_USB); |
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/* setup initial state */ |
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qcom_usb_hs_phy_vbus_notifier(&uphy->vbus_notify, state, |
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uphy->vbus_edev); |
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ret = extcon_register_notifier(uphy->vbus_edev, EXTCON_USB, |
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&uphy->vbus_notify); |
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if (ret) |
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goto err_ulpi; |
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} |
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return 0; |
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err_ulpi: |
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regulator_disable(uphy->v3p3); |
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err_3p3: |
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regulator_disable(uphy->v1p8); |
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err_1p8: |
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clk_disable_unprepare(uphy->sleep_clk); |
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err_sleep: |
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clk_disable_unprepare(uphy->ref_clk); |
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return ret; |
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} |
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static int qcom_usb_hs_phy_power_off(struct phy *phy) |
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{ |
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int ret; |
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struct qcom_usb_hs_phy *uphy = phy_get_drvdata(phy); |
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if (uphy->vbus_edev) { |
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ret = extcon_unregister_notifier(uphy->vbus_edev, EXTCON_USB, |
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&uphy->vbus_notify); |
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if (ret) |
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return ret; |
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} |
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regulator_disable(uphy->v3p3); |
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regulator_disable(uphy->v1p8); |
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clk_disable_unprepare(uphy->sleep_clk); |
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clk_disable_unprepare(uphy->ref_clk); |
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return 0; |
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} |
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static const struct phy_ops qcom_usb_hs_phy_ops = { |
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.power_on = qcom_usb_hs_phy_power_on, |
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.power_off = qcom_usb_hs_phy_power_off, |
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.set_mode = qcom_usb_hs_phy_set_mode, |
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.owner = THIS_MODULE, |
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}; |
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static int qcom_usb_hs_phy_probe(struct ulpi *ulpi) |
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{ |
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struct qcom_usb_hs_phy *uphy; |
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struct phy_provider *p; |
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struct clk *clk; |
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struct regulator *reg; |
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struct reset_control *reset; |
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int size; |
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int ret; |
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uphy = devm_kzalloc(&ulpi->dev, sizeof(*uphy), GFP_KERNEL); |
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if (!uphy) |
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return -ENOMEM; |
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ulpi_set_drvdata(ulpi, uphy); |
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uphy->ulpi = ulpi; |
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size = of_property_count_u8_elems(ulpi->dev.of_node, "qcom,init-seq"); |
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if (size < 0) |
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size = 0; |
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uphy->init_seq = devm_kmalloc_array(&ulpi->dev, (size / 2) + 1, |
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sizeof(*uphy->init_seq), GFP_KERNEL); |
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if (!uphy->init_seq) |
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return -ENOMEM; |
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ret = of_property_read_u8_array(ulpi->dev.of_node, "qcom,init-seq", |
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(u8 *)uphy->init_seq, size); |
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if (ret && size) |
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return ret; |
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/* NUL terminate */ |
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uphy->init_seq[size / 2].addr = uphy->init_seq[size / 2].val = 0; |
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uphy->ref_clk = clk = devm_clk_get(&ulpi->dev, "ref"); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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uphy->sleep_clk = clk = devm_clk_get(&ulpi->dev, "sleep"); |
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if (IS_ERR(clk)) |
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return PTR_ERR(clk); |
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uphy->v1p8 = reg = devm_regulator_get(&ulpi->dev, "v1p8"); |
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if (IS_ERR(reg)) |
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return PTR_ERR(reg); |
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uphy->v3p3 = reg = devm_regulator_get(&ulpi->dev, "v3p3"); |
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if (IS_ERR(reg)) |
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return PTR_ERR(reg); |
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uphy->reset = reset = devm_reset_control_get(&ulpi->dev, "por"); |
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if (IS_ERR(reset)) { |
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if (PTR_ERR(reset) == -EPROBE_DEFER) |
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return PTR_ERR(reset); |
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uphy->reset = NULL; |
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} |
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uphy->phy = devm_phy_create(&ulpi->dev, ulpi->dev.of_node, |
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&qcom_usb_hs_phy_ops); |
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if (IS_ERR(uphy->phy)) |
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return PTR_ERR(uphy->phy); |
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uphy->vbus_edev = extcon_get_edev_by_phandle(&ulpi->dev, 0); |
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if (IS_ERR(uphy->vbus_edev)) { |
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if (PTR_ERR(uphy->vbus_edev) != -ENODEV) |
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return PTR_ERR(uphy->vbus_edev); |
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uphy->vbus_edev = NULL; |
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} |
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uphy->vbus_notify.notifier_call = qcom_usb_hs_phy_vbus_notifier; |
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phy_set_drvdata(uphy->phy, uphy); |
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p = devm_of_phy_provider_register(&ulpi->dev, of_phy_simple_xlate); |
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return PTR_ERR_OR_ZERO(p); |
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} |
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static const struct of_device_id qcom_usb_hs_phy_match[] = { |
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{ .compatible = "qcom,usb-hs-phy", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, qcom_usb_hs_phy_match); |
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static struct ulpi_driver qcom_usb_hs_phy_driver = { |
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.probe = qcom_usb_hs_phy_probe, |
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.driver = { |
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.name = "qcom_usb_hs_phy", |
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.of_match_table = qcom_usb_hs_phy_match, |
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}, |
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}; |
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module_ulpi_driver(qcom_usb_hs_phy_driver); |
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MODULE_DESCRIPTION("Qualcomm USB HS phy"); |
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MODULE_LICENSE("GPL v2"); |
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