Reviewed-by: Linus Walleij <linux.walleij@stericsson.com> Signed-off-by: Viresh Kumar <viresh.kumar@st.com> Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com> Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>tirimbino
viresh kumar
15 years ago
committed by
Russell King
parent
a7e9c45219
commit
e024c3d50c
@ -0,0 +1,14 @@ |
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/* |
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* arch/arm/mach-spear6xx/include/mach/debug-macro.S |
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* |
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* Debugging macro include header for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com>
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <plat/debug-macro.S> |
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@ -0,0 +1,55 @@ |
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/* |
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* arch/arm/mach-spear6xx/include/mach/entry-macro.S |
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* |
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* Low-level IRQ helper macros for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com>
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <mach/hardware.h> |
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#include <mach/spear.h> |
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#include <asm/hardware/vic.h> |
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.macro disable_fiq
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.endm |
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.macro get_irqnr_preamble, base, tmp |
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.endm |
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.macro arch_ret_to_user, tmp1, tmp2 |
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.endm |
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.macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
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ldr \base, =VA_SPEAR6XX_CPU_VIC_PRI_BASE |
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ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status |
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mov \irqnr, #0 |
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teq \irqstat, #0 |
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bne 1001f |
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ldr \base, =VA_SPEAR6XX_CPU_VIC_SEC_BASE |
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ldr \irqstat, [\base, #VIC_IRQ_STATUS] @ get status |
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teq \irqstat, #0 |
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beq 1002f @ this will set/reset
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@ zero register
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mov \irqnr, #32 |
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1001: |
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/* |
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* Following code will find bit position of least significang |
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* bit set in irqstat, using following equation |
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* least significant bit set in n = (n & ~(n-1)) |
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*/ |
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sub \tmp, \irqstat, #1 @ tmp = irqstat - 1
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mvn \tmp, \tmp @ tmp = ~tmp
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and \irqstat, \irqstat, \tmp @ irqstat &= tmp
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/* Now, irqstat is = bit no. of 1st bit set in vic irq status */ |
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clz \tmp, \irqstat @ tmp = leading zeros
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rsb \tmp, \tmp, #0x1F @ tmp = 32 - tmp - 1
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add \irqnr, \irqnr, \tmp |
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1002: /* EQ will be set if no irqs pending */ |
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.endm |
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@ -0,0 +1,45 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/generic.h |
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* |
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* SPEAr6XX machine family specific generic header file |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_GENERIC_H |
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#define __MACH_GENERIC_H |
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#include <asm/mach/time.h> |
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#include <asm/mach/map.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/amba/bus.h> |
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/*
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* Each GPT has 2 timer channels |
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* Following GPT channels will be used as clock source and clockevent |
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*/ |
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#define SPEAR_GPT0_BASE SPEAR6XX_CPU_TMR_BASE |
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#define SPEAR_GPT0_CHAN0_IRQ IRQ_CPU_GPT1_1 |
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#define SPEAR_GPT0_CHAN1_IRQ IRQ_CPU_GPT1_2 |
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/* Add spear6xx family device structure declarations here */ |
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extern struct amba_device gpio_device[]; |
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extern struct amba_device uart_device[]; |
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extern struct sys_timer spear_sys_timer; |
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/* Add spear6xx family function declarations here */ |
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void __init spear6xx_map_io(void); |
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void __init spear6xx_init_irq(void); |
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void __init spear6xx_init(void); |
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void __init spear600_init(void); |
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void __init clk_init(void); |
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/* Add spear600 machine device structure declarations here */ |
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#endif /* __MACH_GENERIC_H */ |
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@ -0,0 +1,19 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/gpio.h |
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* |
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* GPIO macros for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Viresh Kumar<viresh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_GPIO_H |
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#define __MACH_GPIO_H |
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#include <plat/gpio.h> |
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#endif /* __MACH_GPIO_H */ |
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@ -0,0 +1,21 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/hardware.h |
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* |
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* Hardware definitions for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_HARDWARE_H |
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#define __MACH_HARDWARE_H |
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/* Vitual to physical translation of statically mapped space */ |
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#define IO_ADDRESS(x) (x | 0xF0000000) |
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#endif /* __MACH_HARDWARE_H */ |
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@ -0,0 +1,20 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/io.h |
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* |
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* IO definitions for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar Kumar<rajeev-dlh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_IO_H |
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#define __MACH_IO_H |
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#include <plat/io.h> |
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#endif /* __MACH_IO_H */ |
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@ -0,0 +1,96 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/irqs.h |
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* |
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* IRQ helper macros for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_IRQS_H |
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#define __MACH_IRQS_H |
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/* IRQ definitions */ |
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/* VIC 1 */ |
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#define IRQ_INTRCOMM_SW_IRQ 0 |
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#define IRQ_INTRCOMM_CPU_1 1 |
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#define IRQ_INTRCOMM_CPU_2 2 |
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#define IRQ_INTRCOMM_RAS2A11_1 3 |
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#define IRQ_INTRCOMM_RAS2A11_2 4 |
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#define IRQ_INTRCOMM_RAS2A12_1 5 |
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#define IRQ_INTRCOMM_RAS2A12_2 6 |
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#define IRQ_GEN_RAS_0 7 |
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#define IRQ_GEN_RAS_1 8 |
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#define IRQ_GEN_RAS_2 9 |
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#define IRQ_GEN_RAS_3 10 |
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#define IRQ_GEN_RAS_4 11 |
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#define IRQ_GEN_RAS_5 12 |
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#define IRQ_GEN_RAS_6 13 |
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#define IRQ_GEN_RAS_7 14 |
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#define IRQ_GEN_RAS_8 15 |
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#define IRQ_CPU_GPT1_1 16 |
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#define IRQ_CPU_GPT1_2 17 |
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#define IRQ_LOCAL_GPIO 18 |
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#define IRQ_PLL_UNLOCK 19 |
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#define IRQ_JPEG 20 |
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#define IRQ_FSMC 21 |
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#define IRQ_IRDA 22 |
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#define IRQ_RESERVED 23 |
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#define IRQ_UART_0 24 |
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#define IRQ_UART_1 25 |
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#define IRQ_SSP_1 26 |
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#define IRQ_SSP_2 27 |
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#define IRQ_I2C 28 |
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#define IRQ_GEN_RAS_9 29 |
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#define IRQ_GEN_RAS_10 30 |
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#define IRQ_GEN_RAS_11 31 |
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/* VIC 2 */ |
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#define IRQ_APPL_GPT1_1 32 |
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#define IRQ_APPL_GPT1_2 33 |
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#define IRQ_APPL_GPT2_1 34 |
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#define IRQ_APPL_GPT2_2 35 |
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#define IRQ_APPL_GPIO 36 |
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#define IRQ_APPL_SSP 37 |
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#define IRQ_APPL_ADC 38 |
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#define IRQ_APPL_RESERVED 39 |
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#define IRQ_AHB_EXP_MASTER 40 |
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#define IRQ_DDR_CONTROLLER 41 |
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#define IRQ_BASIC_DMA 42 |
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#define IRQ_BASIC_RESERVED1 43 |
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#define IRQ_BASIC_SMI 44 |
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#define IRQ_BASIC_CLCD 45 |
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#define IRQ_EXP_AHB_1 46 |
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#define IRQ_EXP_AHB_2 47 |
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#define IRQ_BASIC_GPT1_1 48 |
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#define IRQ_BASIC_GPT1_2 49 |
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#define IRQ_BASIC_RTC 50 |
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#define IRQ_BASIC_GPIO 51 |
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#define IRQ_BASIC_WDT 52 |
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#define IRQ_BASIC_RESERVED 53 |
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#define IRQ_AHB_EXP_SLAVE 54 |
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#define IRQ_GMAC_1 55 |
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#define IRQ_GMAC_2 56 |
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#define IRQ_USB_DEV 57 |
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#define IRQ_USB_H_OHCI_0 58 |
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#define IRQ_USB_H_EHCI_0 59 |
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#define IRQ_USB_H_OHCI_1 60 |
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#define IRQ_USB_H_EHCI_1 61 |
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#define IRQ_EXP_AHB_3 62 |
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#define IRQ_EXP_AHB_4 63 |
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#define IRQ_VIC_END 64 |
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#define SPEAR_GPIO_INT_BASE IRQ_VIC_END |
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#define SPEAR_GPIO0_INT_BASE SPEAR_GPIO_INT_BASE |
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#define SPEAR_GPIO1_INT_BASE (SPEAR_GPIO0_INT_BASE + 8) |
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#define SPEAR_GPIO2_INT_BASE (SPEAR_GPIO1_INT_BASE + 8) |
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#define SPEAR_GPIO_INT_END (SPEAR_GPIO2_INT_BASE + 8) |
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#define VIRTUAL_IRQS (SPEAR_GPIO_INT_END - IRQ_VIC_END) |
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#define NR_IRQS (IRQ_VIC_END + VIRTUAL_IRQS) |
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#endif /* __MACH_IRQS_H */ |
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@ -0,0 +1,19 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/memory.h |
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* |
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* Memory map for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_MEMORY_H |
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#define __MACH_MEMORY_H |
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#include <plat/memory.h> |
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#endif /* __MACH_MEMORY_H */ |
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@ -0,0 +1,173 @@ |
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/*
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* arch/arm/mach-spear6xx/include/mach/misc_regs.h |
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* |
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* Miscellaneous registers definitions for SPEAr6xx machine family |
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* |
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* Copyright (C) 2009 ST Microelectronics |
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* Viresh Kumar<viresh.kumar@st.com> |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#ifndef __MACH_MISC_REGS_H |
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#define __MACH_MISC_REGS_H |
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#include <mach/spear.h> |
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#define MISC_BASE VA_SPEAR6XX_ICM3_MISC_REG_BASE |
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#define SOC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x000)) |
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#define DIAG_CFG_CTR ((unsigned int *)(MISC_BASE + 0x004)) |
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#define PLL1_CTR ((unsigned int *)(MISC_BASE + 0x008)) |
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#define PLL1_FRQ ((unsigned int *)(MISC_BASE + 0x00C)) |
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#define PLL1_MOD ((unsigned int *)(MISC_BASE + 0x010)) |
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#define PLL2_CTR ((unsigned int *)(MISC_BASE + 0x014)) |
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/* PLL_CTR register masks */ |
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#define PLL_ENABLE 2 |
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#define PLL_MODE_SHIFT 4 |
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#define PLL_MODE_MASK 0x3 |
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#define PLL_MODE_NORMAL 0 |
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#define PLL_MODE_FRACTION 1 |
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#define PLL_MODE_DITH_DSB 2 |
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#define PLL_MODE_DITH_SSB 3 |
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#define PLL2_FRQ ((unsigned int *)(MISC_BASE + 0x018)) |
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/* PLL FRQ register masks */ |
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#define PLL_DIV_N_SHIFT 0 |
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#define PLL_DIV_N_MASK 0xFF |
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#define PLL_DIV_P_SHIFT 8 |
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#define PLL_DIV_P_MASK 0x7 |
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#define PLL_NORM_FDBK_M_SHIFT 24 |
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#define PLL_NORM_FDBK_M_MASK 0xFF |
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#define PLL_DITH_FDBK_M_SHIFT 16 |
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#define PLL_DITH_FDBK_M_MASK 0xFFFF |
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#define PLL2_MOD ((unsigned int *)(MISC_BASE + 0x01C)) |
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#define PLL_CLK_CFG ((unsigned int *)(MISC_BASE + 0x020)) |
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#define CORE_CLK_CFG ((unsigned int *)(MISC_BASE + 0x024)) |
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/* CORE CLK CFG register masks */ |
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#define PLL_HCLK_RATIO_SHIFT 10 |
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#define PLL_HCLK_RATIO_MASK 0x3 |
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#define HCLK_PCLK_RATIO_SHIFT 8 |
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#define HCLK_PCLK_RATIO_MASK 0x3 |
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#define PERIP_CLK_CFG ((unsigned int *)(MISC_BASE + 0x028)) |
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/* PERIP_CLK_CFG register masks */ |
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#define CLCD_CLK_SHIFT 2 |
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#define CLCD_CLK_MASK 0x3 |
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#define UART_CLK_SHIFT 4 |
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#define UART_CLK_MASK 0x1 |
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#define FIRDA_CLK_SHIFT 5 |
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#define FIRDA_CLK_MASK 0x3 |
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#define GPT0_CLK_SHIFT 8 |
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#define GPT1_CLK_SHIFT 10 |
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#define GPT2_CLK_SHIFT 11 |
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#define GPT3_CLK_SHIFT 12 |
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#define GPT_CLK_MASK 0x1 |
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#define AUX_CLK_PLL3_MASK 0 |
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#define AUX_CLK_PLL1_MASK 1 |
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#define PERIP1_CLK_ENB ((unsigned int *)(MISC_BASE + 0x02C)) |
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/* PERIP1_CLK_ENB register masks */ |
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#define UART0_CLK_ENB 3 |
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#define UART1_CLK_ENB 4 |
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#define SSP0_CLK_ENB 5 |
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#define SSP1_CLK_ENB 6 |
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#define I2C_CLK_ENB 7 |
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#define JPEG_CLK_ENB 8 |
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#define FSMC_CLK_ENB 9 |
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#define FIRDA_CLK_ENB 10 |
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#define GPT2_CLK_ENB 11 |
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#define GPT3_CLK_ENB 12 |
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#define GPIO2_CLK_ENB 13 |
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#define SSP2_CLK_ENB 14 |
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#define ADC_CLK_ENB 15 |
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#define GPT1_CLK_ENB 11 |
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#define RTC_CLK_ENB 17 |
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#define GPIO1_CLK_ENB 18 |
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#define DMA_CLK_ENB 19 |
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#define SMI_CLK_ENB 21 |
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#define CLCD_CLK_ENB 22 |
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#define GMAC_CLK_ENB 23 |
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#define USBD_CLK_ENB 24 |
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#define USBH0_CLK_ENB 25 |
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#define USBH1_CLK_ENB 26 |
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#define SOC_CORE_ID ((unsigned int *)(MISC_BASE + 0x030)) |
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#define RAS_CLK_ENB ((unsigned int *)(MISC_BASE + 0x034)) |
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#define PERIP1_SOF_RST ((unsigned int *)(MISC_BASE + 0x038)) |
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/* PERIP1_SOF_RST register masks */ |
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#define JPEG_SOF_RST 8 |
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#define SOC_USER_ID ((unsigned int *)(MISC_BASE + 0x03C)) |
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#define RAS_SOF_RST ((unsigned int *)(MISC_BASE + 0x040)) |
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#define PRSC1_CLK_CFG ((unsigned int *)(MISC_BASE + 0x044)) |
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#define PRSC2_CLK_CFG ((unsigned int *)(MISC_BASE + 0x048)) |
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#define PRSC3_CLK_CFG ((unsigned int *)(MISC_BASE + 0x04C)) |
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/* gpt synthesizer register masks */ |
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#define GPT_MSCALE_SHIFT 0 |
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#define GPT_MSCALE_MASK 0xFFF |
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#define GPT_NSCALE_SHIFT 12 |
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#define GPT_NSCALE_MASK 0xF |
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#define AMEM_CLK_CFG ((unsigned int *)(MISC_BASE + 0x050)) |
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#define EXPI_CLK_CFG ((unsigned int *)(MISC_BASE + 0x054)) |
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#define CLCD_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x05C)) |
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#define FIRDA_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x060)) |
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#define UART_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x064)) |
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#define GMAC_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x068)) |
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#define RAS1_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x06C)) |
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#define RAS2_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x070)) |
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#define RAS3_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x074)) |
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#define RAS4_CLK_SYNT ((unsigned int *)(MISC_BASE + 0x078)) |
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/* aux clk synthesiser register masks for irda to ras4 */ |
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#define AUX_EQ_SEL_SHIFT 30 |
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#define AUX_EQ_SEL_MASK 1 |
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#define AUX_EQ1_SEL 0 |
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#define AUX_EQ2_SEL 1 |
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#define AUX_XSCALE_SHIFT 16 |
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#define AUX_XSCALE_MASK 0xFFF |
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#define AUX_YSCALE_SHIFT 0 |
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#define AUX_YSCALE_MASK 0xFFF |
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#define ICM1_ARB_CFG ((unsigned int *)(MISC_BASE + 0x07C)) |
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#define ICM2_ARB_CFG ((unsigned int *)(MISC_BASE + 0x080)) |
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#define ICM3_ARB_CFG ((unsigned int *)(MISC_BASE + 0x084)) |
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#define ICM4_ARB_CFG ((unsigned int *)(MISC_BASE + 0x088)) |
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#define ICM5_ARB_CFG ((unsigned int *)(MISC_BASE + 0x08C)) |
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#define ICM6_ARB_CFG ((unsigned int *)(MISC_BASE + 0x090)) |
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#define ICM7_ARB_CFG ((unsigned int *)(MISC_BASE + 0x094)) |
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#define ICM8_ARB_CFG ((unsigned int *)(MISC_BASE + 0x098)) |
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#define ICM9_ARB_CFG ((unsigned int *)(MISC_BASE + 0x09C)) |
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#define DMA_CHN_CFG ((unsigned int *)(MISC_BASE + 0x0A0)) |
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#define USB2_PHY_CFG ((unsigned int *)(MISC_BASE + 0x0A4)) |
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#define GMAC_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0A8)) |
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#define EXPI_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0AC)) |
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#define PRC1_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C0)) |
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#define PRC2_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C4)) |
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#define PRC3_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0C8)) |
||||
#define PRC4_LOCK_CTR ((unsigned int *)(MISC_BASE + 0x0CC)) |
||||
#define PRC1_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D0)) |
||||
#define PRC2_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D4)) |
||||
#define PRC3_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0D8)) |
||||
#define PRC4_IRQ_CTR ((unsigned int *)(MISC_BASE + 0x0DC)) |
||||
#define PWRDOWN_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0E0)) |
||||
#define COMPSSTL_1V8_CFG ((unsigned int *)(MISC_BASE + 0x0E4)) |
||||
#define COMPSSTL_2V5_CFG ((unsigned int *)(MISC_BASE + 0x0E8)) |
||||
#define COMPCOR_3V3_CFG ((unsigned int *)(MISC_BASE + 0x0EC)) |
||||
#define SSTLPAD_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F0)) |
||||
#define BIST1_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F4)) |
||||
#define BIST2_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0F8)) |
||||
#define BIST3_CFG_CTR ((unsigned int *)(MISC_BASE + 0x0FC)) |
||||
#define BIST4_CFG_CTR ((unsigned int *)(MISC_BASE + 0x100)) |
||||
#define BIST5_CFG_CTR ((unsigned int *)(MISC_BASE + 0x104)) |
||||
#define BIST1_STS_RES ((unsigned int *)(MISC_BASE + 0x108)) |
||||
#define BIST2_STS_RES ((unsigned int *)(MISC_BASE + 0x10C)) |
||||
#define BIST3_STS_RES ((unsigned int *)(MISC_BASE + 0x110)) |
||||
#define BIST4_STS_RES ((unsigned int *)(MISC_BASE + 0x114)) |
||||
#define BIST5_STS_RES ((unsigned int *)(MISC_BASE + 0x118)) |
||||
#define SYSERR_CFG_CTR ((unsigned int *)(MISC_BASE + 0x11C)) |
||||
|
||||
#endif /* __MACH_MISC_REGS_H */ |
||||
@ -0,0 +1,173 @@ |
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/spear.h |
||||
* |
||||
* SPEAr6xx Machine family specific definition |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifndef __MACH_SPEAR6XX_H |
||||
#define __MACH_SPEAR6XX_H |
||||
|
||||
#include <mach/hardware.h> |
||||
#include <mach/spear600.h> |
||||
|
||||
#define SPEAR6XX_ML_SDRAM_BASE 0x00000000 |
||||
#define SPEAR6XX_ML_SDRAM_SIZE 0x40000000 |
||||
|
||||
/* ICM1 - Low speed connection */ |
||||
#define SPEAR6XX_ICM1_BASE 0xD0000000 |
||||
#define SPEAR6XX_ICM1_SIZE 0x08000000 |
||||
|
||||
#define SPEAR6XX_ICM1_UART0_BASE 0xD0000000 |
||||
#define VA_SPEAR6XX_ICM1_UART0_BASE IO_ADDRESS(SPEAR6XX_ICM1_UART0_BASE) |
||||
#define SPEAR6XX_ICM1_UART0_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM1_UART1_BASE 0xD0080000 |
||||
#define SPEAR6XX_ICM1_UART1_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM1_SSP0_BASE 0xD0100000 |
||||
#define SPEAR6XX_ICM1_SSP0_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM1_SSP1_BASE 0xD0180000 |
||||
#define SPEAR6XX_ICM1_SSP1_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM1_I2C_BASE 0xD0200000 |
||||
#define SPEAR6XX_ICM1_I2C_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM1_JPEG_BASE 0xD0800000 |
||||
#define SPEAR6XX_ICM1_JPEG_SIZE 0x00800000 |
||||
|
||||
#define SPEAR6XX_ICM1_IRDA_BASE 0xD1000000 |
||||
#define SPEAR6XX_ICM1_IRDA_SIZE 0x00800000 |
||||
|
||||
#define SPEAR6XX_ICM1_FSMC_BASE 0xD1800000 |
||||
#define SPEAR6XX_ICM1_FSMC_SIZE 0x00800000 |
||||
|
||||
#define SPEAR6XX_ICM1_NAND_BASE 0xD2000000 |
||||
#define SPEAR6XX_ICM1_NAND_SIZE 0x00800000 |
||||
|
||||
#define SPEAR6XX_ICM1_SRAM_BASE 0xD2800000 |
||||
#define SPEAR6XX_ICM1_SRAM_SIZE 0x00800000 |
||||
|
||||
/* ICM2 - Application Subsystem */ |
||||
#define SPEAR6XX_ICM2_BASE 0xD8000000 |
||||
#define SPEAR6XX_ICM2_SIZE 0x08000000 |
||||
|
||||
#define SPEAR6XX_ICM2_TMR0_BASE 0xD8000000 |
||||
#define SPEAR6XX_ICM2_TMR0_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM2_TMR1_BASE 0xD8080000 |
||||
#define SPEAR6XX_ICM2_TMR1_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM2_GPIO_BASE 0xD8100000 |
||||
#define SPEAR6XX_ICM2_GPIO_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM2_SPI2_BASE 0xD8180000 |
||||
#define SPEAR6XX_ICM2_SPI2_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM2_ADC_BASE 0xD8200000 |
||||
#define SPEAR6XX_ICM2_ADC_SIZE 0x00080000 |
||||
|
||||
/* ML-1, 2 - Multi Layer CPU Subsystem */ |
||||
#define SPEAR6XX_ML_CPU_BASE 0xF0000000 |
||||
#define SPEAR6XX_ML_CPU_SIZE 0x08000000 |
||||
|
||||
#define SPEAR6XX_CPU_TMR_BASE 0xF0000000 |
||||
#define SPEAR6XX_CPU_TMR_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_CPU_GPIO_BASE 0xF0100000 |
||||
#define SPEAR6XX_CPU_GPIO_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_CPU_VIC_SEC_BASE 0xF1000000 |
||||
#define VA_SPEAR6XX_CPU_VIC_SEC_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_SEC_BASE) |
||||
#define SPEAR6XX_CPU_VIC_SEC_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_CPU_VIC_PRI_BASE 0xF1100000 |
||||
#define VA_SPEAR6XX_CPU_VIC_PRI_BASE IO_ADDRESS(SPEAR6XX_CPU_VIC_PRI_BASE) |
||||
#define SPEAR6XX_CPU_VIC_PRI_SIZE 0x00100000 |
||||
|
||||
/* ICM3 - Basic Subsystem */ |
||||
#define SPEAR6XX_ICM3_BASE 0xF8000000 |
||||
#define SPEAR6XX_ICM3_SIZE 0x08000000 |
||||
|
||||
#define SPEAR6XX_ICM3_SMEM_BASE 0xF8000000 |
||||
#define SPEAR6XX_ICM3_SMEM_SIZE 0x04000000 |
||||
|
||||
#define SPEAR6XX_ICM3_SMI_CTRL_BASE 0xFC000000 |
||||
#define SPEAR6XX_ICM3_SMI_CTRL_SIZE 0x00200000 |
||||
|
||||
#define SPEAR6XX_ICM3_CLCD_BASE 0xFC200000 |
||||
#define SPEAR6XX_ICM3_CLCD_SIZE 0x00200000 |
||||
|
||||
#define SPEAR6XX_ICM3_DMA_BASE 0xFC400000 |
||||
#define SPEAR6XX_ICM3_DMA_SIZE 0x00200000 |
||||
|
||||
#define SPEAR6XX_ICM3_SDRAM_CTRL_BASE 0xFC600000 |
||||
#define SPEAR6XX_ICM3_SDRAM_CTRL_SIZE 0x00200000 |
||||
|
||||
#define SPEAR6XX_ICM3_TMR_BASE 0xFC800000 |
||||
#define SPEAR6XX_ICM3_TMR_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM3_WDT_BASE 0xFC880000 |
||||
#define SPEAR6XX_ICM3_WDT_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM3_RTC_BASE 0xFC900000 |
||||
#define SPEAR6XX_ICM3_RTC_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM3_GPIO_BASE 0xFC980000 |
||||
#define SPEAR6XX_ICM3_GPIO_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM3_SYS_CTRL_BASE 0xFCA00000 |
||||
#define VA_SPEAR6XX_ICM3_SYS_CTRL_BASE IO_ADDRESS(SPEAR6XX_ICM3_SYS_CTRL_BASE) |
||||
#define SPEAR6XX_ICM3_SYS_CTRL_SIZE 0x00080000 |
||||
|
||||
#define SPEAR6XX_ICM3_MISC_REG_BASE 0xFCA80000 |
||||
#define VA_SPEAR6XX_ICM3_MISC_REG_BASE IO_ADDRESS(SPEAR6XX_ICM3_MISC_REG_BASE) |
||||
#define SPEAR6XX_ICM3_MISC_REG_SIZE 0x00080000 |
||||
|
||||
/* ICM4 - High Speed Connection */ |
||||
#define SPEAR6XX_ICM4_BASE 0xE0000000 |
||||
#define SPEAR6XX_ICM4_SIZE 0x08000000 |
||||
|
||||
#define SPEAR6XX_ICM4_GMAC_BASE 0xE0800000 |
||||
#define SPEAR6XX_ICM4_GMAC_SIZE 0x00800000 |
||||
|
||||
#define SPEAR6XX_ICM4_USBD_FIFO_BASE 0xE1000000 |
||||
#define SPEAR6XX_ICM4_USBD_FIFO_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USBD_CSR_BASE 0xE1100000 |
||||
#define SPEAR6XX_ICM4_USBD_CSR_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USBD_PLDT_BASE 0xE1200000 |
||||
#define SPEAR6XX_ICM4_USBD_PLDT_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USB_EHCI0_BASE 0xE1800000 |
||||
#define SPEAR6XX_ICM4_USB_EHCI0_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USB_OHCI0_BASE 0xE1900000 |
||||
#define SPEAR6XX_ICM4_USB_OHCI0_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USB_EHCI1_BASE 0xE2000000 |
||||
#define SPEAR6XX_ICM4_USB_EHCI1_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USB_OHCI1_BASE 0xE2100000 |
||||
#define SPEAR6XX_ICM4_USB_OHCI1_SIZE 0x00100000 |
||||
|
||||
#define SPEAR6XX_ICM4_USB_ARB_BASE 0xE2800000 |
||||
#define SPEAR6XX_ICM4_USB_ARB_SIZE 0x00010000 |
||||
|
||||
/* Debug uart for linux, will be used for debug and uncompress messages */ |
||||
#define SPEAR_DBG_UART_BASE SPEAR6XX_ICM1_UART0_BASE |
||||
#define VA_SPEAR_DBG_UART_BASE VA_SPEAR6XX_ICM1_UART0_BASE |
||||
|
||||
/* Sysctl base for spear platform */ |
||||
#define SPEAR_SYS_CTRL_BASE SPEAR6XX_ICM3_SYS_CTRL_BASE |
||||
#define VA_SPEAR_SYS_CTRL_BASE VA_SPEAR6XX_ICM3_SYS_CTRL_BASE |
||||
|
||||
#endif /* __MACH_SPEAR6XX_H */ |
||||
@ -0,0 +1,21 @@ |
||||
/*
|
||||
* arch/arm/mach-spear66xx/include/mach/spear600.h |
||||
* |
||||
* SPEAr600 Machine specific definition |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Viresh Kumar<viresh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifdef CONFIG_MACH_SPEAR600 |
||||
|
||||
#ifndef __MACH_SPEAR600_H |
||||
#define __MACH_SPEAR600_H |
||||
|
||||
#endif /* __MACH_SPEAR600_H */ |
||||
|
||||
#endif /* CONFIG_MACH_SPEAR600 */ |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/system.h |
||||
* |
||||
* SPEAr6xx Machine family specific architecture functions |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifndef __MACH_SYSTEM_H |
||||
#define __MACH_SYSTEM_H |
||||
|
||||
#include <plat/system.h> |
||||
|
||||
#endif /* __MACH_SYSTEM_H */ |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/timex.h |
||||
* |
||||
* SPEAr6XX machine family specific timex definitions |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifndef __MACH_TIMEX_H |
||||
#define __MACH_TIMEX_H |
||||
|
||||
#include <plat/timex.h> |
||||
|
||||
#endif /* __MACH_TIMEX_H */ |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/uncompress.h |
||||
* |
||||
* Serial port stubs for kernel decompress status messages |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifndef __MACH_UNCOMPRESS_H |
||||
#define __MACH_UNCOMPRESS_H |
||||
|
||||
#include <plat/uncompress.h> |
||||
|
||||
#endif /* __MACH_UNCOMPRESS_H */ |
||||
@ -0,0 +1,19 @@ |
||||
/*
|
||||
* arch/arm/mach-spear6xx/include/mach/vmalloc.h |
||||
* |
||||
* Defining Vmalloc area for SPEAr6xx machine family |
||||
* |
||||
* Copyright (C) 2009 ST Microelectronics |
||||
* Rajeev Kumar<rajeev-dlh.kumar@st.com> |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
#ifndef __MACH_VMALLOC_H |
||||
#define __MACH_VMALLOC_H |
||||
|
||||
#include <plat/vmalloc.h> |
||||
|
||||
#endif /* __MACH_VMALLOC_H */ |
||||
Loading…
Reference in new issue