This adds support for the i.MX6 QuadPlus PRE units. Currently only linear prefetch into SRAM is supported, other modes of operation like the tiled-to-linear conversion will be added later. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>tirimbino
Lucas Stach
8 years ago
committed by
Philipp Zabel
parent
dcddda561b
commit
d2a3423258
@ -0,0 +1,289 @@ |
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/*
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* Copyright (c) 2017 Lucas Stach, Pengutronix |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms and conditions of the GNU General Public License, |
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* version 2, as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope it will be useful, but WITHOUT |
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or |
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for |
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* more details. |
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*/ |
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#include <drm/drm_fourcc.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/genalloc.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <video/imx-ipu-v3.h> |
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#include "ipu-prv.h" |
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#define IPU_PRE_MAX_WIDTH 2048 |
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#define IPU_PRE_NUM_SCANLINES 8 |
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#define IPU_PRE_CTRL 0x000 |
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#define IPU_PRE_CTRL_SET 0x004 |
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#define IPU_PRE_CTRL_ENABLE (1 << 0) |
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#define IPU_PRE_CTRL_BLOCK_EN (1 << 1) |
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#define IPU_PRE_CTRL_BLOCK_16 (1 << 2) |
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#define IPU_PRE_CTRL_SDW_UPDATE (1 << 4) |
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#define IPU_PRE_CTRL_VFLIP (1 << 5) |
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#define IPU_PRE_CTRL_SO (1 << 6) |
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#define IPU_PRE_CTRL_INTERLACED_FIELD (1 << 7) |
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#define IPU_PRE_CTRL_HANDSHAKE_EN (1 << 8) |
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#define IPU_PRE_CTRL_HANDSHAKE_LINE_NUM(v) ((v & 0x3) << 9) |
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#define IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN (1 << 11) |
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#define IPU_PRE_CTRL_EN_REPEAT (1 << 28) |
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#define IPU_PRE_CTRL_TPR_REST_SEL (1 << 29) |
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#define IPU_PRE_CTRL_CLKGATE (1 << 30) |
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#define IPU_PRE_CTRL_SFTRST (1 << 31) |
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#define IPU_PRE_CUR_BUF 0x030 |
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#define IPU_PRE_NEXT_BUF 0x040 |
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#define IPU_PRE_TPR_CTRL 0x070 |
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#define IPU_PRE_TPR_CTRL_TILE_FORMAT(v) ((v & 0xff) << 0) |
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#define IPU_PRE_TPR_CTRL_TILE_FORMAT_MASK 0xff |
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#define IPU_PRE_PREFETCH_ENG_CTRL 0x080 |
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#define IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN (1 << 0) |
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#define IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(v) ((v & 0x7) << 1) |
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#define IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) |
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#define IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(v) ((v & 0x7) << 8) |
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#define IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS (1 << 11) |
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#define IPU_PRE_PREF_ENG_CTRL_FIELD_INVERSE (1 << 12) |
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#define IPU_PRE_PREF_ENG_CTRL_PARTIAL_UV_SWAP (1 << 14) |
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#define IPU_PRE_PREF_ENG_CTRL_TPR_COOR_OFFSET_EN (1 << 15) |
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#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE 0x0a0 |
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#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(v) ((v & 0xffff) << 0) |
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#define IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(v) ((v & 0xffff) << 16) |
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#define IPU_PRE_PREFETCH_ENG_PITCH 0x0d0 |
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#define IPU_PRE_PREFETCH_ENG_PITCH_Y(v) ((v & 0xffff) << 0) |
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#define IPU_PRE_PREFETCH_ENG_PITCH_UV(v) ((v & 0xffff) << 16) |
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#define IPU_PRE_STORE_ENG_CTRL 0x110 |
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#define IPU_PRE_STORE_ENG_CTRL_STORE_EN (1 << 0) |
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#define IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(v) ((v & 0x7) << 1) |
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#define IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(v) ((v & 0x3) << 4) |
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#define IPU_PRE_STORE_ENG_SIZE 0x130 |
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#define IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(v) ((v & 0xffff) << 0) |
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#define IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(v) ((v & 0xffff) << 16) |
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#define IPU_PRE_STORE_ENG_PITCH 0x140 |
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#define IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(v) ((v & 0xffff) << 0) |
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#define IPU_PRE_STORE_ENG_ADDR 0x150 |
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struct ipu_pre { |
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struct list_head list; |
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struct device *dev; |
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void __iomem *regs; |
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struct clk *clk_axi; |
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struct gen_pool *iram; |
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dma_addr_t buffer_paddr; |
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void *buffer_virt; |
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bool in_use; |
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}; |
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static DEFINE_MUTEX(ipu_pre_list_mutex); |
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static LIST_HEAD(ipu_pre_list); |
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static int available_pres; |
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int ipu_pre_get_available_count(void) |
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{ |
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return available_pres; |
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} |
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struct ipu_pre * |
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ipu_pre_lookup_by_phandle(struct device *dev, const char *name, int index) |
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{ |
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struct device_node *pre_node = of_parse_phandle(dev->of_node, |
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name, index); |
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struct ipu_pre *pre; |
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mutex_lock(&ipu_pre_list_mutex); |
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list_for_each_entry(pre, &ipu_pre_list, list) { |
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if (pre_node == pre->dev->of_node) { |
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mutex_unlock(&ipu_pre_list_mutex); |
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device_link_add(dev, pre->dev, DL_FLAG_AUTOREMOVE); |
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return pre; |
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} |
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} |
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mutex_unlock(&ipu_pre_list_mutex); |
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return NULL; |
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} |
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int ipu_pre_get(struct ipu_pre *pre) |
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{ |
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u32 val; |
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if (pre->in_use) |
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return -EBUSY; |
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clk_prepare_enable(pre->clk_axi); |
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/* first get the engine out of reset and remove clock gating */ |
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writel(0, pre->regs + IPU_PRE_CTRL); |
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/* init defaults that should be applied to all streams */ |
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val = IPU_PRE_CTRL_HANDSHAKE_ABORT_SKIP_EN | |
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IPU_PRE_CTRL_HANDSHAKE_EN | |
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IPU_PRE_CTRL_TPR_REST_SEL | |
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IPU_PRE_CTRL_BLOCK_16 | IPU_PRE_CTRL_SDW_UPDATE; |
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writel(val, pre->regs + IPU_PRE_CTRL); |
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pre->in_use = true; |
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return 0; |
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} |
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void ipu_pre_put(struct ipu_pre *pre) |
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{ |
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u32 val; |
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val = IPU_PRE_CTRL_SFTRST | IPU_PRE_CTRL_CLKGATE; |
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writel(val, pre->regs + IPU_PRE_CTRL); |
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clk_disable_unprepare(pre->clk_axi); |
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pre->in_use = false; |
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} |
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void ipu_pre_configure(struct ipu_pre *pre, unsigned int width, |
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unsigned int height, unsigned int stride, u32 format, |
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unsigned int bufaddr) |
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{ |
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const struct drm_format_info *info = drm_format_info(format); |
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u32 active_bpp = info->cpp[0] >> 1; |
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u32 val; |
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writel(bufaddr, pre->regs + IPU_PRE_CUR_BUF); |
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writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); |
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val = IPU_PRE_PREF_ENG_CTRL_INPUT_PIXEL_FORMAT(0) | |
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IPU_PRE_PREF_ENG_CTRL_INPUT_ACTIVE_BPP(active_bpp) | |
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IPU_PRE_PREF_ENG_CTRL_RD_NUM_BYTES(4) | |
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IPU_PRE_PREF_ENG_CTRL_SHIFT_BYPASS | |
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IPU_PRE_PREF_ENG_CTRL_PREFETCH_EN; |
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writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_CTRL); |
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val = IPU_PRE_PREFETCH_ENG_INPUT_SIZE_WIDTH(width) | |
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IPU_PRE_PREFETCH_ENG_INPUT_SIZE_HEIGHT(height); |
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writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_INPUT_SIZE); |
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val = IPU_PRE_PREFETCH_ENG_PITCH_Y(stride); |
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writel(val, pre->regs + IPU_PRE_PREFETCH_ENG_PITCH); |
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val = IPU_PRE_STORE_ENG_CTRL_OUTPUT_ACTIVE_BPP(active_bpp) | |
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IPU_PRE_STORE_ENG_CTRL_WR_NUM_BYTES(4) | |
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IPU_PRE_STORE_ENG_CTRL_STORE_EN; |
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writel(val, pre->regs + IPU_PRE_STORE_ENG_CTRL); |
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val = IPU_PRE_STORE_ENG_SIZE_INPUT_WIDTH(width) | |
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IPU_PRE_STORE_ENG_SIZE_INPUT_HEIGHT(height); |
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writel(val, pre->regs + IPU_PRE_STORE_ENG_SIZE); |
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val = IPU_PRE_STORE_ENG_PITCH_OUT_PITCH(stride); |
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writel(val, pre->regs + IPU_PRE_STORE_ENG_PITCH); |
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writel(pre->buffer_paddr, pre->regs + IPU_PRE_STORE_ENG_ADDR); |
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val = readl(pre->regs + IPU_PRE_CTRL); |
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val |= IPU_PRE_CTRL_EN_REPEAT | IPU_PRE_CTRL_ENABLE | |
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IPU_PRE_CTRL_SDW_UPDATE; |
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writel(val, pre->regs + IPU_PRE_CTRL); |
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} |
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void ipu_pre_update(struct ipu_pre *pre, unsigned int bufaddr) |
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{ |
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writel(bufaddr, pre->regs + IPU_PRE_NEXT_BUF); |
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writel(IPU_PRE_CTRL_SDW_UPDATE, pre->regs + IPU_PRE_CTRL_SET); |
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} |
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u32 ipu_pre_get_baddr(struct ipu_pre *pre) |
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{ |
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return (u32)pre->buffer_paddr; |
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} |
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static int ipu_pre_probe(struct platform_device *pdev) |
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{ |
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struct device *dev = &pdev->dev; |
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struct resource *res; |
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struct ipu_pre *pre; |
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pre = devm_kzalloc(dev, sizeof(*pre), GFP_KERNEL); |
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if (!pre) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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pre->regs = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(pre->regs)) |
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return PTR_ERR(pre->regs); |
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pre->clk_axi = devm_clk_get(dev, "axi"); |
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if (IS_ERR(pre->clk_axi)) |
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return PTR_ERR(pre->clk_axi); |
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pre->iram = of_gen_pool_get(dev->of_node, "fsl,iram", 0); |
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if (!pre->iram) |
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return -EPROBE_DEFER; |
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/*
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* Allocate IRAM buffer with maximum size. This could be made dynamic, |
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* but as there is no other user of this IRAM region and we can fit all |
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* max sized buffers into it, there is no need yet. |
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*/ |
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pre->buffer_virt = gen_pool_dma_alloc(pre->iram, IPU_PRE_MAX_WIDTH * |
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IPU_PRE_NUM_SCANLINES * 4, |
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&pre->buffer_paddr); |
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if (!pre->buffer_virt) |
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return -ENOMEM; |
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pre->dev = dev; |
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platform_set_drvdata(pdev, pre); |
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mutex_lock(&ipu_pre_list_mutex); |
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list_add(&pre->list, &ipu_pre_list); |
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available_pres++; |
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mutex_unlock(&ipu_pre_list_mutex); |
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return 0; |
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} |
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static int ipu_pre_remove(struct platform_device *pdev) |
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{ |
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struct ipu_pre *pre = platform_get_drvdata(pdev); |
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mutex_lock(&ipu_pre_list_mutex); |
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list_del(&pre->list); |
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available_pres--; |
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mutex_unlock(&ipu_pre_list_mutex); |
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if (pre->buffer_virt) |
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gen_pool_free(pre->iram, (unsigned long)pre->buffer_virt, |
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IPU_PRE_MAX_WIDTH * IPU_PRE_NUM_SCANLINES * 4); |
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return 0; |
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} |
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static const struct of_device_id ipu_pre_dt_ids[] = { |
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{ .compatible = "fsl,imx6qp-pre", }, |
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{ /* sentinel */ }, |
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}; |
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struct platform_driver ipu_pre_drv = { |
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.probe = ipu_pre_probe, |
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.remove = ipu_pre_remove, |
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.driver = { |
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.name = "imx-ipu-pre", |
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.of_match_table = ipu_pre_dt_ids, |
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}, |
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}; |
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