Merge branch 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6 into drm-fixes
Fix some pageflip, oopses and some better clock support for some chipsets * 'drm-nouveau-next' of git://anongit.freedesktop.org/git/nouveau/linux-2.6: drm/nv50/disp: min/max are reversed in nv50_crtc_gamma_set() drm/nouveau/sw: fix oops if gpu has its display block disabled drm/nouveau: unreference fence after syncing drm/nouveau/kms: send timestamp data for correct head in flip completion events drm/nouveau/clk: Add support for NVAA/NVAC drm/nouveau/fifo: Hook up pause and resume for NV50 and NV84+ drm/nv10/plane: some chipsets don't support NV12 drm/nv10/plane: add downscaling restrictions drm/nv10/plane: fix format computation drm/nv04-nv30/clk: provide an empty domain listtirimbino
Dave Airlie
11 years ago
commit
c17f5bb529
@ -0,0 +1,445 @@ |
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/*
|
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* Copyright 2012 Red Hat Inc. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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* |
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* Authors: Ben Skeggs |
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*/ |
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|
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#include <engine/fifo.h> |
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#include <subdev/bios.h> |
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#include <subdev/bios/pll.h> |
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#include <subdev/timer.h> |
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#include <subdev/clock.h> |
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#include "pll.h" |
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|
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struct nvaa_clock_priv { |
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struct nouveau_clock base; |
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enum nv_clk_src csrc, ssrc, vsrc; |
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u32 cctrl, sctrl; |
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u32 ccoef, scoef; |
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u32 cpost, spost; |
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u32 vdiv; |
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}; |
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|
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static u32 |
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read_div(struct nouveau_clock *clk) |
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{ |
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return nv_rd32(clk, 0x004600); |
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} |
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|
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static u32 |
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read_pll(struct nouveau_clock *clk, u32 base) |
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{ |
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u32 ctrl = nv_rd32(clk, base + 0); |
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u32 coef = nv_rd32(clk, base + 4); |
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u32 ref = clk->read(clk, nv_clk_src_href); |
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u32 post_div = 0; |
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u32 clock = 0; |
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int N1, M1; |
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switch (base){ |
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case 0x4020: |
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post_div = 1 << ((nv_rd32(clk, 0x4070) & 0x000f0000) >> 16); |
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break; |
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case 0x4028: |
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post_div = (nv_rd32(clk, 0x4040) & 0x000f0000) >> 16; |
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break; |
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default: |
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break; |
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} |
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N1 = (coef & 0x0000ff00) >> 8; |
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M1 = (coef & 0x000000ff); |
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if ((ctrl & 0x80000000) && M1) { |
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clock = ref * N1 / M1; |
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clock = clock / post_div; |
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} |
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return clock; |
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} |
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static int |
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nvaa_clock_read(struct nouveau_clock *clk, enum nv_clk_src src) |
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{ |
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struct nvaa_clock_priv *priv = (void *)clk; |
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u32 mast = nv_rd32(clk, 0x00c054); |
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u32 P = 0; |
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switch (src) { |
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case nv_clk_src_crystal: |
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return nv_device(priv)->crystal; |
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case nv_clk_src_href: |
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return 100000; /* PCIE reference clock */ |
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case nv_clk_src_hclkm4: |
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return clk->read(clk, nv_clk_src_href) * 4; |
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case nv_clk_src_hclkm2d3: |
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return clk->read(clk, nv_clk_src_href) * 2 / 3; |
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case nv_clk_src_host: |
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switch (mast & 0x000c0000) { |
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case 0x00000000: return clk->read(clk, nv_clk_src_hclkm2d3); |
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case 0x00040000: break; |
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case 0x00080000: return clk->read(clk, nv_clk_src_hclkm4); |
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case 0x000c0000: return clk->read(clk, nv_clk_src_cclk); |
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} |
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break; |
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case nv_clk_src_core: |
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P = (nv_rd32(clk, 0x004028) & 0x00070000) >> 16; |
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|
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switch (mast & 0x00000003) { |
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case 0x00000000: return clk->read(clk, nv_clk_src_crystal) >> P; |
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case 0x00000001: return 0; |
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case 0x00000002: return clk->read(clk, nv_clk_src_hclkm4) >> P; |
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case 0x00000003: return read_pll(clk, 0x004028) >> P; |
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} |
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break; |
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case nv_clk_src_cclk: |
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if ((mast & 0x03000000) != 0x03000000) |
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return clk->read(clk, nv_clk_src_core); |
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|
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if ((mast & 0x00000200) == 0x00000000) |
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return clk->read(clk, nv_clk_src_core); |
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|
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switch (mast & 0x00000c00) { |
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case 0x00000000: return clk->read(clk, nv_clk_src_href); |
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case 0x00000400: return clk->read(clk, nv_clk_src_hclkm4); |
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case 0x00000800: return clk->read(clk, nv_clk_src_hclkm2d3); |
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default: return 0; |
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} |
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case nv_clk_src_shader: |
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P = (nv_rd32(clk, 0x004020) & 0x00070000) >> 16; |
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switch (mast & 0x00000030) { |
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case 0x00000000: |
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if (mast & 0x00000040) |
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return clk->read(clk, nv_clk_src_href) >> P; |
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return clk->read(clk, nv_clk_src_crystal) >> P; |
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case 0x00000010: break; |
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case 0x00000020: return read_pll(clk, 0x004028) >> P; |
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case 0x00000030: return read_pll(clk, 0x004020) >> P; |
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} |
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break; |
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case nv_clk_src_mem: |
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return 0; |
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break; |
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case nv_clk_src_vdec: |
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P = (read_div(clk) & 0x00000700) >> 8; |
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|
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switch (mast & 0x00400000) { |
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case 0x00400000: |
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return clk->read(clk, nv_clk_src_core) >> P; |
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break; |
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default: |
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return 500000 >> P; |
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break; |
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} |
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break; |
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default: |
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break; |
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} |
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nv_debug(priv, "unknown clock source %d 0x%08x\n", src, mast); |
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return 0; |
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} |
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static u32 |
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calc_pll(struct nvaa_clock_priv *priv, u32 reg, |
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u32 clock, int *N, int *M, int *P) |
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{ |
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struct nouveau_bios *bios = nouveau_bios(priv); |
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struct nvbios_pll pll; |
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struct nouveau_clock *clk = &priv->base; |
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int ret; |
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ret = nvbios_pll_parse(bios, reg, &pll); |
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if (ret) |
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return 0; |
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pll.vco2.max_freq = 0; |
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pll.refclk = clk->read(clk, nv_clk_src_href); |
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if (!pll.refclk) |
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return 0; |
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return nv04_pll_calc(nv_subdev(priv), &pll, clock, N, M, NULL, NULL, P); |
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} |
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static inline u32 |
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calc_P(u32 src, u32 target, int *div) |
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{ |
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u32 clk0 = src, clk1 = src; |
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for (*div = 0; *div <= 7; (*div)++) { |
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if (clk0 <= target) { |
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clk1 = clk0 << (*div ? 1 : 0); |
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break; |
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} |
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clk0 >>= 1; |
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} |
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if (target - clk0 <= clk1 - target) |
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return clk0; |
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(*div)--; |
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return clk1; |
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} |
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static int |
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nvaa_clock_calc(struct nouveau_clock *clk, struct nouveau_cstate *cstate) |
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{ |
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struct nvaa_clock_priv *priv = (void *)clk; |
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const int shader = cstate->domain[nv_clk_src_shader]; |
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const int core = cstate->domain[nv_clk_src_core]; |
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const int vdec = cstate->domain[nv_clk_src_vdec]; |
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u32 out = 0, clock = 0; |
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int N, M, P1, P2 = 0; |
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int divs = 0; |
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/* cclk: find suitable source, disable PLL if we can */ |
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if (core < clk->read(clk, nv_clk_src_hclkm4)) |
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out = calc_P(clk->read(clk, nv_clk_src_hclkm4), core, &divs); |
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/* Calculate clock * 2, so shader clock can use it too */ |
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clock = calc_pll(priv, 0x4028, (core << 1), &N, &M, &P1); |
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if (abs(core - out) <= |
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abs(core - (clock >> 1))) { |
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priv->csrc = nv_clk_src_hclkm4; |
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priv->cctrl = divs << 16; |
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} else { |
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/* NVCTRL is actually used _after_ NVPOST, and after what we
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* call NVPLL. To make matters worse, NVPOST is an integer |
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* divider instead of a right-shift number. */ |
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if(P1 > 2) { |
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P2 = P1 - 2; |
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P1 = 2; |
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} |
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priv->csrc = nv_clk_src_core; |
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priv->ccoef = (N << 8) | M; |
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|
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priv->cctrl = (P2 + 1) << 16; |
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priv->cpost = (1 << P1) << 16; |
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} |
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|
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/* sclk: nvpll + divisor, href or spll */ |
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out = 0; |
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if (shader == clk->read(clk, nv_clk_src_href)) { |
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priv->ssrc = nv_clk_src_href; |
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} else { |
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clock = calc_pll(priv, 0x4020, shader, &N, &M, &P1); |
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if (priv->csrc == nv_clk_src_core) { |
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out = calc_P((core << 1), shader, &divs); |
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} |
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|
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if (abs(shader - out) <= |
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abs(shader - clock) && |
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(divs + P2) <= 7) { |
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priv->ssrc = nv_clk_src_core; |
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priv->sctrl = (divs + P2) << 16; |
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} else { |
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priv->ssrc = nv_clk_src_shader; |
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priv->scoef = (N << 8) | M; |
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priv->sctrl = P1 << 16; |
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} |
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} |
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|
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/* vclk */ |
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out = calc_P(core, vdec, &divs); |
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clock = calc_P(500000, vdec, &P1); |
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if(abs(vdec - out) <= |
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abs(vdec - clock)) { |
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priv->vsrc = nv_clk_src_cclk; |
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priv->vdiv = divs << 16; |
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} else { |
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priv->vsrc = nv_clk_src_vdec; |
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priv->vdiv = P1 << 16; |
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} |
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|
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/* Print strategy! */ |
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nv_debug(priv, "nvpll: %08x %08x %08x\n", |
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priv->ccoef, priv->cpost, priv->cctrl); |
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nv_debug(priv, " spll: %08x %08x %08x\n", |
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priv->scoef, priv->spost, priv->sctrl); |
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nv_debug(priv, " vdiv: %08x\n", priv->vdiv); |
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if (priv->csrc == nv_clk_src_hclkm4) |
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nv_debug(priv, "core: hrefm4\n"); |
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else |
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nv_debug(priv, "core: nvpll\n"); |
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|
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if (priv->ssrc == nv_clk_src_hclkm4) |
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nv_debug(priv, "shader: hrefm4\n"); |
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else if (priv->ssrc == nv_clk_src_core) |
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nv_debug(priv, "shader: nvpll\n"); |
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else |
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nv_debug(priv, "shader: spll\n"); |
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|
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if (priv->vsrc == nv_clk_src_hclkm4) |
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nv_debug(priv, "vdec: 500MHz\n"); |
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else |
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nv_debug(priv, "vdec: core\n"); |
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|
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return 0; |
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} |
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|
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static int |
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nvaa_clock_prog(struct nouveau_clock *clk) |
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{ |
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struct nvaa_clock_priv *priv = (void *)clk; |
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struct nouveau_fifo *pfifo = nouveau_fifo(clk); |
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unsigned long flags; |
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u32 pllmask = 0, mast, ptherm_gate; |
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int ret = -EBUSY; |
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|
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/* halt and idle execution engines */ |
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ptherm_gate = nv_mask(clk, 0x020060, 0x00070000, 0x00000000); |
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nv_mask(clk, 0x002504, 0x00000001, 0x00000001); |
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/* Wait until the interrupt handler is finished */ |
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if (!nv_wait(clk, 0x000100, 0xffffffff, 0x00000000)) |
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goto resume; |
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|
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if (pfifo) |
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pfifo->pause(pfifo, &flags); |
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|
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if (!nv_wait(clk, 0x002504, 0x00000010, 0x00000010)) |
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goto resume; |
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if (!nv_wait(clk, 0x00251c, 0x0000003f, 0x0000003f)) |
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goto resume; |
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|
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/* First switch to safe clocks: href */ |
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mast = nv_mask(clk, 0xc054, 0x03400e70, 0x03400640); |
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mast &= ~0x00400e73; |
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mast |= 0x03000000; |
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|
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switch (priv->csrc) { |
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case nv_clk_src_hclkm4: |
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nv_mask(clk, 0x4028, 0x00070000, priv->cctrl); |
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mast |= 0x00000002; |
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break; |
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case nv_clk_src_core: |
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nv_wr32(clk, 0x402c, priv->ccoef); |
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nv_wr32(clk, 0x4028, 0x80000000 | priv->cctrl); |
||||
nv_wr32(clk, 0x4040, priv->cpost); |
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pllmask |= (0x3 << 8); |
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mast |= 0x00000003; |
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break; |
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default: |
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nv_warn(priv,"Reclocking failed: unknown core clock\n"); |
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goto resume; |
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} |
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|
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switch (priv->ssrc) { |
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case nv_clk_src_href: |
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nv_mask(clk, 0x4020, 0x00070000, 0x00000000); |
||||
/* mast |= 0x00000000; */ |
||||
break; |
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case nv_clk_src_core: |
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nv_mask(clk, 0x4020, 0x00070000, priv->sctrl); |
||||
mast |= 0x00000020; |
||||
break; |
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case nv_clk_src_shader: |
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nv_wr32(clk, 0x4024, priv->scoef); |
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nv_wr32(clk, 0x4020, 0x80000000 | priv->sctrl); |
||||
nv_wr32(clk, 0x4070, priv->spost); |
||||
pllmask |= (0x3 << 12); |
||||
mast |= 0x00000030; |
||||
break; |
||||
default: |
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nv_warn(priv,"Reclocking failed: unknown sclk clock\n"); |
||||
goto resume; |
||||
} |
||||
|
||||
if (!nv_wait(clk, 0x004080, pllmask, pllmask)) { |
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nv_warn(priv,"Reclocking failed: unstable PLLs\n"); |
||||
goto resume; |
||||
} |
||||
|
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switch (priv->vsrc) { |
||||
case nv_clk_src_cclk: |
||||
mast |= 0x00400000; |
||||
default: |
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nv_wr32(clk, 0x4600, priv->vdiv); |
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} |
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|
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nv_wr32(clk, 0xc054, mast); |
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ret = 0; |
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|
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resume: |
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if (pfifo) |
||||
pfifo->start(pfifo, &flags); |
||||
|
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nv_mask(clk, 0x002504, 0x00000001, 0x00000000); |
||||
nv_wr32(clk, 0x020060, ptherm_gate); |
||||
|
||||
/* Disable some PLLs and dividers when unused */ |
||||
if (priv->csrc != nv_clk_src_core) { |
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nv_wr32(clk, 0x4040, 0x00000000); |
||||
nv_mask(clk, 0x4028, 0x80000000, 0x00000000); |
||||
} |
||||
|
||||
if (priv->ssrc != nv_clk_src_shader) { |
||||
nv_wr32(clk, 0x4070, 0x00000000); |
||||
nv_mask(clk, 0x4020, 0x80000000, 0x00000000); |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void |
||||
nvaa_clock_tidy(struct nouveau_clock *clk) |
||||
{ |
||||
} |
||||
|
||||
static struct nouveau_clocks |
||||
nvaa_domains[] = { |
||||
{ nv_clk_src_crystal, 0xff }, |
||||
{ nv_clk_src_href , 0xff }, |
||||
{ nv_clk_src_core , 0xff, 0, "core", 1000 }, |
||||
{ nv_clk_src_shader , 0xff, 0, "shader", 1000 }, |
||||
{ nv_clk_src_vdec , 0xff, 0, "vdec", 1000 }, |
||||
{ nv_clk_src_max } |
||||
}; |
||||
|
||||
static int |
||||
nvaa_clock_ctor(struct nouveau_object *parent, struct nouveau_object *engine, |
||||
struct nouveau_oclass *oclass, void *data, u32 size, |
||||
struct nouveau_object **pobject) |
||||
{ |
||||
struct nvaa_clock_priv *priv; |
||||
int ret; |
||||
|
||||
ret = nouveau_clock_create(parent, engine, oclass, nvaa_domains, &priv); |
||||
*pobject = nv_object(priv); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
priv->base.read = nvaa_clock_read; |
||||
priv->base.calc = nvaa_clock_calc; |
||||
priv->base.prog = nvaa_clock_prog; |
||||
priv->base.tidy = nvaa_clock_tidy; |
||||
return 0; |
||||
} |
||||
|
||||
struct nouveau_oclass * |
||||
nvaa_clock_oclass = &(struct nouveau_oclass) { |
||||
.handle = NV_SUBDEV(CLOCK, 0xaa), |
||||
.ofuncs = &(struct nouveau_ofuncs) { |
||||
.ctor = nvaa_clock_ctor, |
||||
.dtor = _nouveau_clock_dtor, |
||||
.init = _nouveau_clock_init, |
||||
.fini = _nouveau_clock_fini, |
||||
}, |
||||
}; |
||||
Loading…
Reference in new issue