Merge branches 'pci/host-designware', 'pci/host-designware-common', 'pci/host-generic', 'pci/host-imx6', 'pci/host-iproc' and 'pci/host-xgene' into next
* pci/host-designware: PCI: designware: Use iATU0 for cfg and IO, iATU1 for MEM PCI: designware: Consolidate outbound iATU programming functions PCI: designware: Add support for x8 links * pci/host-designware-common: PCI: designware: Wait for link to come up with consistent style PCI: layerscape: Factor out ls_pcie_establish_link() PCI: layerscape: Use dw_pcie_link_up() consistently PCI: dra7xx: Use dw_pcie_link_up() consistently PCI: imx6: Rename imx6_pcie_start_link() to imx6_pcie_establish_link() * pci/host-generic: of/pci: Fix pci_address_to_pio() conversion of CPU address to I/O port * pci/host-imx6: PCI: imx6: Add #define PCIE_RC_LCSR PCI: imx6: Use "u32", not "uint32_t" PCI: imx6: Add speed change timeout message * pci/host-iproc: PCI: iproc: Free resource list after registration PCI: iproc: Directly add PCI resources PCI: iproc: Add BCMA PCIe driver PCI: iproc: Allow override of device tree IRQ mapping function * pci/host-xgene: arm64: dts: Add APM X-Gene PCIe MSI nodes PCI: xgene: Add APM X-Gene v1 PCIe MSI/MSIX termination drivertirimbino
Bjorn Helgaas
10 years ago
commit
bf933dbb84
@ -0,0 +1,68 @@ |
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* AppliedMicro X-Gene v1 PCIe MSI controller |
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|
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Required properties: |
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|
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- compatible: should be "apm,xgene1-msi" to identify |
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X-Gene v1 PCIe MSI controller block. |
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- msi-controller: indicates that this is X-Gene v1 PCIe MSI controller node |
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- reg: physical base address (0x79000000) and length (0x900000) for controller |
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registers. These registers include the MSI termination address and data |
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registers as well as the MSI interrupt status registers. |
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- reg-names: not required |
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- interrupts: A list of 16 interrupt outputs of the controller, starting from |
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interrupt number 0x10 to 0x1f. |
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- interrupt-names: not required |
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|
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Each PCIe node needs to have property msi-parent that points to msi controller node |
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|
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Examples: |
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|
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SoC DTSI: |
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|
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+ MSI node: |
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msi@79000000 { |
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compatible = "apm,xgene1-msi"; |
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msi-controller; |
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reg = <0x00 0x79000000 0x0 0x900000>; |
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interrupts = <0x0 0x10 0x4> |
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<0x0 0x11 0x4> |
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<0x0 0x12 0x4> |
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<0x0 0x13 0x4> |
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<0x0 0x14 0x4> |
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<0x0 0x15 0x4> |
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<0x0 0x16 0x4> |
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<0x0 0x17 0x4> |
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<0x0 0x18 0x4> |
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<0x0 0x19 0x4> |
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<0x0 0x1a 0x4> |
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<0x0 0x1b 0x4> |
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<0x0 0x1c 0x4> |
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<0x0 0x1d 0x4> |
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<0x0 0x1e 0x4> |
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<0x0 0x1f 0x4>; |
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}; |
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|
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+ PCIe controller node with msi-parent property pointing to MSI node: |
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pcie0: pcie@1f2b0000 { |
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status = "disabled"; |
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device_type = "pci"; |
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compatible = "apm,xgene-storm-pcie", "apm,xgene-pcie"; |
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#interrupt-cells = <1>; |
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#size-cells = <2>; |
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#address-cells = <3>; |
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reg = < 0x00 0x1f2b0000 0x0 0x00010000 /* Controller registers */ |
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0xe0 0xd0000000 0x0 0x00040000>; /* PCI config space */ |
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reg-names = "csr", "cfg"; |
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ranges = <0x01000000 0x00 0x00000000 0xe0 0x10000000 0x00 0x00010000 /* io */ |
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0x02000000 0x00 0x80000000 0xe1 0x80000000 0x00 0x80000000>; /* mem */ |
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dma-ranges = <0x42000000 0x80 0x00000000 0x80 0x00000000 0x00 0x80000000 |
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0x42000000 0x00 0x00000000 0x00 0x00000000 0x80 0x00000000>; |
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interrupt-map-mask = <0x0 0x0 0x0 0x7>; |
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interrupt-map = <0x0 0x0 0x0 0x1 &gic 0x0 0xc2 0x1 |
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0x0 0x0 0x0 0x2 &gic 0x0 0xc3 0x1 |
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0x0 0x0 0x0 0x3 &gic 0x0 0xc4 0x1 |
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0x0 0x0 0x0 0x4 &gic 0x0 0xc5 0x1>; |
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dma-coherent; |
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clocks = <&pcie0clk 0>; |
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msi-parent= <&msi>; |
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}; |
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@ -0,0 +1,596 @@ |
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/*
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* APM X-Gene MSI Driver |
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* |
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* Copyright (c) 2014, Applied Micro Circuits Corporation |
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* Author: Tanmay Inamdar <tinamdar@apm.com> |
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* Duc Dang <dhdang@apm.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/cpu.h> |
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#include <linux/interrupt.h> |
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#include <linux/module.h> |
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#include <linux/msi.h> |
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#include <linux/of_irq.h> |
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#include <linux/irqchip/chained_irq.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/of_pci.h> |
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|
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#define MSI_IR0 0x000000 |
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#define MSI_INT0 0x800000 |
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#define IDX_PER_GROUP 8 |
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#define IRQS_PER_IDX 16 |
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#define NR_HW_IRQS 16 |
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#define NR_MSI_VEC (IDX_PER_GROUP * IRQS_PER_IDX * NR_HW_IRQS) |
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|
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struct xgene_msi_group { |
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struct xgene_msi *msi; |
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int gic_irq; |
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u32 msi_grp; |
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}; |
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|
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struct xgene_msi { |
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struct device_node *node; |
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struct msi_controller mchip; |
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struct irq_domain *domain; |
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u64 msi_addr; |
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void __iomem *msi_regs; |
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unsigned long *bitmap; |
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struct mutex bitmap_lock; |
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struct xgene_msi_group *msi_groups; |
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int num_cpus; |
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}; |
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|
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/* Global data */ |
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static struct xgene_msi xgene_msi_ctrl; |
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|
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static struct irq_chip xgene_msi_top_irq_chip = { |
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.name = "X-Gene1 MSI", |
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.irq_enable = pci_msi_unmask_irq, |
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.irq_disable = pci_msi_mask_irq, |
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.irq_mask = pci_msi_mask_irq, |
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.irq_unmask = pci_msi_unmask_irq, |
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}; |
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|
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static struct msi_domain_info xgene_msi_domain_info = { |
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.flags = (MSI_FLAG_USE_DEF_DOM_OPS | MSI_FLAG_USE_DEF_CHIP_OPS | |
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MSI_FLAG_PCI_MSIX), |
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.chip = &xgene_msi_top_irq_chip, |
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}; |
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|
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/*
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* X-Gene v1 has 16 groups of MSI termination registers MSInIRx, where |
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* n is group number (0..F), x is index of registers in each group (0..7) |
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* The register layout is as follows: |
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* MSI0IR0 base_addr |
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* MSI0IR1 base_addr + 0x10000 |
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* ... ... |
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* MSI0IR6 base_addr + 0x60000 |
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* MSI0IR7 base_addr + 0x70000 |
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* MSI1IR0 base_addr + 0x80000 |
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* MSI1IR1 base_addr + 0x90000 |
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* ... ... |
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* MSI1IR7 base_addr + 0xF0000 |
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* MSI2IR0 base_addr + 0x100000 |
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* ... ... |
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* MSIFIR0 base_addr + 0x780000 |
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* MSIFIR1 base_addr + 0x790000 |
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* ... ... |
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* MSIFIR7 base_addr + 0x7F0000 |
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* MSIINT0 base_addr + 0x800000 |
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* MSIINT1 base_addr + 0x810000 |
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* ... ... |
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* MSIINTF base_addr + 0x8F0000 |
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* |
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* Each index register supports 16 MSI vectors (0..15) to generate interrupt. |
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* There are total 16 GIC IRQs assigned for these 16 groups of MSI termination |
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* registers. |
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* |
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* Each MSI termination group has 1 MSIINTn register (n is 0..15) to indicate |
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* the MSI pending status caused by 1 of its 8 index registers. |
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*/ |
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|
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/* MSInIRx read helper */ |
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static u32 xgene_msi_ir_read(struct xgene_msi *msi, |
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u32 msi_grp, u32 msir_idx) |
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{ |
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return readl_relaxed(msi->msi_regs + MSI_IR0 + |
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(msi_grp << 19) + (msir_idx << 16)); |
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} |
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|
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/* MSIINTn read helper */ |
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static u32 xgene_msi_int_read(struct xgene_msi *msi, u32 msi_grp) |
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{ |
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return readl_relaxed(msi->msi_regs + MSI_INT0 + (msi_grp << 16)); |
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} |
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|
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/*
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* With 2048 MSI vectors supported, the MSI message can be constructed using |
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* following scheme: |
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* - Divide into 8 256-vector groups |
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* Group 0: 0-255 |
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* Group 1: 256-511 |
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* Group 2: 512-767 |
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* ... |
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* Group 7: 1792-2047 |
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* - Each 256-vector group is divided into 16 16-vector groups |
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* As an example: 16 16-vector groups for 256-vector group 0-255 is |
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* Group 0: 0-15 |
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* Group 1: 16-32 |
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* ... |
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* Group 15: 240-255 |
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* - The termination address of MSI vector in 256-vector group n and 16-vector |
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* group x is the address of MSIxIRn |
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* - The data for MSI vector in 16-vector group x is x |
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*/ |
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static u32 hwirq_to_reg_set(unsigned long hwirq) |
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{ |
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return (hwirq / (NR_HW_IRQS * IRQS_PER_IDX)); |
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} |
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|
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static u32 hwirq_to_group(unsigned long hwirq) |
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{ |
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return (hwirq % NR_HW_IRQS); |
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} |
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static u32 hwirq_to_msi_data(unsigned long hwirq) |
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{ |
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return ((hwirq / NR_HW_IRQS) % IRQS_PER_IDX); |
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} |
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|
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static void xgene_compose_msi_msg(struct irq_data *data, struct msi_msg *msg) |
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{ |
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struct xgene_msi *msi = irq_data_get_irq_chip_data(data); |
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u32 reg_set = hwirq_to_reg_set(data->hwirq); |
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u32 group = hwirq_to_group(data->hwirq); |
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u64 target_addr = msi->msi_addr + (((8 * group) + reg_set) << 16); |
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msg->address_hi = upper_32_bits(target_addr); |
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msg->address_lo = lower_32_bits(target_addr); |
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msg->data = hwirq_to_msi_data(data->hwirq); |
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} |
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|
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/*
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* X-Gene v1 only has 16 MSI GIC IRQs for 2048 MSI vectors. To maintain |
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* the expected behaviour of .set_affinity for each MSI interrupt, the 16 |
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* MSI GIC IRQs are statically allocated to 8 X-Gene v1 cores (2 GIC IRQs |
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* for each core). The MSI vector is moved fom 1 MSI GIC IRQ to another |
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* MSI GIC IRQ to steer its MSI interrupt to correct X-Gene v1 core. As a |
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* consequence, the total MSI vectors that X-Gene v1 supports will be |
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* reduced to 256 (2048/8) vectors. |
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*/ |
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static int hwirq_to_cpu(unsigned long hwirq) |
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{ |
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return (hwirq % xgene_msi_ctrl.num_cpus); |
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} |
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static unsigned long hwirq_to_canonical_hwirq(unsigned long hwirq) |
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{ |
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return (hwirq - hwirq_to_cpu(hwirq)); |
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} |
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static int xgene_msi_set_affinity(struct irq_data *irqdata, |
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const struct cpumask *mask, bool force) |
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{ |
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int target_cpu = cpumask_first(mask); |
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int curr_cpu; |
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curr_cpu = hwirq_to_cpu(irqdata->hwirq); |
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if (curr_cpu == target_cpu) |
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return IRQ_SET_MASK_OK_DONE; |
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|
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/* Update MSI number to target the new CPU */ |
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irqdata->hwirq = hwirq_to_canonical_hwirq(irqdata->hwirq) + target_cpu; |
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return IRQ_SET_MASK_OK; |
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} |
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|
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static struct irq_chip xgene_msi_bottom_irq_chip = { |
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.name = "MSI", |
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.irq_set_affinity = xgene_msi_set_affinity, |
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.irq_compose_msi_msg = xgene_compose_msi_msg, |
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}; |
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|
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static int xgene_irq_domain_alloc(struct irq_domain *domain, unsigned int virq, |
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unsigned int nr_irqs, void *args) |
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{ |
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struct xgene_msi *msi = domain->host_data; |
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int msi_irq; |
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mutex_lock(&msi->bitmap_lock); |
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msi_irq = bitmap_find_next_zero_area(msi->bitmap, NR_MSI_VEC, 0, |
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msi->num_cpus, 0); |
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if (msi_irq < NR_MSI_VEC) |
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bitmap_set(msi->bitmap, msi_irq, msi->num_cpus); |
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else |
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msi_irq = -ENOSPC; |
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mutex_unlock(&msi->bitmap_lock); |
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|
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if (msi_irq < 0) |
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return msi_irq; |
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irq_domain_set_info(domain, virq, msi_irq, |
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&xgene_msi_bottom_irq_chip, domain->host_data, |
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handle_simple_irq, NULL, NULL); |
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set_irq_flags(virq, IRQF_VALID); |
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|
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return 0; |
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} |
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|
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static void xgene_irq_domain_free(struct irq_domain *domain, |
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unsigned int virq, unsigned int nr_irqs) |
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{ |
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struct irq_data *d = irq_domain_get_irq_data(domain, virq); |
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struct xgene_msi *msi = irq_data_get_irq_chip_data(d); |
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u32 hwirq; |
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|
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mutex_lock(&msi->bitmap_lock); |
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|
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hwirq = hwirq_to_canonical_hwirq(d->hwirq); |
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bitmap_clear(msi->bitmap, hwirq, msi->num_cpus); |
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|
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mutex_unlock(&msi->bitmap_lock); |
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irq_domain_free_irqs_parent(domain, virq, nr_irqs); |
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} |
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|
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static const struct irq_domain_ops msi_domain_ops = { |
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.alloc = xgene_irq_domain_alloc, |
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.free = xgene_irq_domain_free, |
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}; |
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|
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static int xgene_allocate_domains(struct xgene_msi *msi) |
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{ |
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msi->domain = irq_domain_add_linear(NULL, NR_MSI_VEC, |
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&msi_domain_ops, msi); |
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if (!msi->domain) |
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return -ENOMEM; |
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|
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msi->mchip.domain = pci_msi_create_irq_domain(msi->mchip.of_node, |
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&xgene_msi_domain_info, |
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msi->domain); |
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|
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if (!msi->mchip.domain) { |
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irq_domain_remove(msi->domain); |
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return -ENOMEM; |
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} |
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|
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return 0; |
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} |
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|
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static void xgene_free_domains(struct xgene_msi *msi) |
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{ |
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if (msi->mchip.domain) |
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irq_domain_remove(msi->mchip.domain); |
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if (msi->domain) |
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irq_domain_remove(msi->domain); |
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} |
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|
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static int xgene_msi_init_allocator(struct xgene_msi *xgene_msi) |
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{ |
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int size = BITS_TO_LONGS(NR_MSI_VEC) * sizeof(long); |
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|
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xgene_msi->bitmap = kzalloc(size, GFP_KERNEL); |
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if (!xgene_msi->bitmap) |
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return -ENOMEM; |
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|
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mutex_init(&xgene_msi->bitmap_lock); |
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|
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xgene_msi->msi_groups = kcalloc(NR_HW_IRQS, |
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sizeof(struct xgene_msi_group), |
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GFP_KERNEL); |
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if (!xgene_msi->msi_groups) |
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return -ENOMEM; |
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|
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return 0; |
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} |
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|
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static void xgene_msi_isr(unsigned int irq, struct irq_desc *desc) |
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{ |
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struct irq_chip *chip = irq_desc_get_chip(desc); |
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struct xgene_msi_group *msi_groups; |
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struct xgene_msi *xgene_msi; |
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unsigned int virq; |
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int msir_index, msir_val, hw_irq; |
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u32 intr_index, grp_select, msi_grp; |
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|
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chained_irq_enter(chip, desc); |
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|
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msi_groups = irq_desc_get_handler_data(desc); |
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xgene_msi = msi_groups->msi; |
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msi_grp = msi_groups->msi_grp; |
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|
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/*
|
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* MSIINTn (n is 0..F) indicates if there is a pending MSI interrupt |
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* If bit x of this register is set (x is 0..7), one or more interupts |
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* corresponding to MSInIRx is set. |
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*/ |
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grp_select = xgene_msi_int_read(xgene_msi, msi_grp); |
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while (grp_select) { |
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msir_index = ffs(grp_select) - 1; |
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/*
|
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* Calculate MSInIRx address to read to check for interrupts |
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* (refer to termination address and data assignment |
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* described in xgene_compose_msi_msg() ) |
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*/ |
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msir_val = xgene_msi_ir_read(xgene_msi, msi_grp, msir_index); |
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while (msir_val) { |
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intr_index = ffs(msir_val) - 1; |
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/*
|
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* Calculate MSI vector number (refer to the termination |
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* address and data assignment described in |
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* xgene_compose_msi_msg function) |
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*/ |
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hw_irq = (((msir_index * IRQS_PER_IDX) + intr_index) * |
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NR_HW_IRQS) + msi_grp; |
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/*
|
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* As we have multiple hw_irq that maps to single MSI, |
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* always look up the virq using the hw_irq as seen from |
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* CPU0 |
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*/ |
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hw_irq = hwirq_to_canonical_hwirq(hw_irq); |
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virq = irq_find_mapping(xgene_msi->domain, hw_irq); |
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WARN_ON(!virq); |
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if (virq != 0) |
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generic_handle_irq(virq); |
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msir_val &= ~(1 << intr_index); |
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} |
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grp_select &= ~(1 << msir_index); |
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|
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if (!grp_select) { |
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/*
|
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* We handled all interrupts happened in this group, |
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* resample this group MSI_INTx register in case |
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* something else has been made pending in the meantime |
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*/ |
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grp_select = xgene_msi_int_read(xgene_msi, msi_grp); |
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} |
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} |
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|
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chained_irq_exit(chip, desc); |
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} |
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|
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static int xgene_msi_remove(struct platform_device *pdev) |
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{ |
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int virq, i; |
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struct xgene_msi *msi = platform_get_drvdata(pdev); |
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|
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for (i = 0; i < NR_HW_IRQS; i++) { |
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virq = msi->msi_groups[i].gic_irq; |
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if (virq != 0) { |
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irq_set_chained_handler(virq, NULL); |
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irq_set_handler_data(virq, NULL); |
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} |
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} |
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kfree(msi->msi_groups); |
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|
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kfree(msi->bitmap); |
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msi->bitmap = NULL; |
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|
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xgene_free_domains(msi); |
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|
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return 0; |
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} |
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|
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static int xgene_msi_hwirq_alloc(unsigned int cpu) |
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{ |
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struct xgene_msi *msi = &xgene_msi_ctrl; |
||||
struct xgene_msi_group *msi_group; |
||||
cpumask_var_t mask; |
||||
int i; |
||||
int err; |
||||
|
||||
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { |
||||
msi_group = &msi->msi_groups[i]; |
||||
if (!msi_group->gic_irq) |
||||
continue; |
||||
|
||||
irq_set_chained_handler(msi_group->gic_irq, |
||||
xgene_msi_isr); |
||||
err = irq_set_handler_data(msi_group->gic_irq, msi_group); |
||||
if (err) { |
||||
pr_err("failed to register GIC IRQ handler\n"); |
||||
return -EINVAL; |
||||
} |
||||
/*
|
||||
* Statically allocate MSI GIC IRQs to each CPU core. |
||||
* With 8-core X-Gene v1, 2 MSI GIC IRQs are allocated |
||||
* to each core. |
||||
*/ |
||||
if (alloc_cpumask_var(&mask, GFP_KERNEL)) { |
||||
cpumask_clear(mask); |
||||
cpumask_set_cpu(cpu, mask); |
||||
err = irq_set_affinity(msi_group->gic_irq, mask); |
||||
if (err) |
||||
pr_err("failed to set affinity for GIC IRQ"); |
||||
free_cpumask_var(mask); |
||||
} else { |
||||
pr_err("failed to alloc CPU mask for affinity\n"); |
||||
err = -EINVAL; |
||||
} |
||||
|
||||
if (err) { |
||||
irq_set_chained_handler(msi_group->gic_irq, NULL); |
||||
irq_set_handler_data(msi_group->gic_irq, NULL); |
||||
return err; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void xgene_msi_hwirq_free(unsigned int cpu) |
||||
{ |
||||
struct xgene_msi *msi = &xgene_msi_ctrl; |
||||
struct xgene_msi_group *msi_group; |
||||
int i; |
||||
|
||||
for (i = cpu; i < NR_HW_IRQS; i += msi->num_cpus) { |
||||
msi_group = &msi->msi_groups[i]; |
||||
if (!msi_group->gic_irq) |
||||
continue; |
||||
|
||||
irq_set_chained_handler(msi_group->gic_irq, NULL); |
||||
irq_set_handler_data(msi_group->gic_irq, NULL); |
||||
} |
||||
} |
||||
|
||||
static int xgene_msi_cpu_callback(struct notifier_block *nfb, |
||||
unsigned long action, void *hcpu) |
||||
{ |
||||
unsigned cpu = (unsigned long)hcpu; |
||||
|
||||
switch (action) { |
||||
case CPU_ONLINE: |
||||
case CPU_ONLINE_FROZEN: |
||||
xgene_msi_hwirq_alloc(cpu); |
||||
break; |
||||
case CPU_DEAD: |
||||
case CPU_DEAD_FROZEN: |
||||
xgene_msi_hwirq_free(cpu); |
||||
break; |
||||
default: |
||||
break; |
||||
} |
||||
|
||||
return NOTIFY_OK; |
||||
} |
||||
|
||||
static struct notifier_block xgene_msi_cpu_notifier = { |
||||
.notifier_call = xgene_msi_cpu_callback, |
||||
}; |
||||
|
||||
static const struct of_device_id xgene_msi_match_table[] = { |
||||
{.compatible = "apm,xgene1-msi"}, |
||||
{}, |
||||
}; |
||||
|
||||
static int xgene_msi_probe(struct platform_device *pdev) |
||||
{ |
||||
struct resource *res; |
||||
int rc, irq_index; |
||||
struct xgene_msi *xgene_msi; |
||||
unsigned int cpu; |
||||
int virt_msir; |
||||
u32 msi_val, msi_idx; |
||||
|
||||
xgene_msi = &xgene_msi_ctrl; |
||||
|
||||
platform_set_drvdata(pdev, xgene_msi); |
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
xgene_msi->msi_regs = devm_ioremap_resource(&pdev->dev, res); |
||||
if (IS_ERR(xgene_msi->msi_regs)) { |
||||
dev_err(&pdev->dev, "no reg space\n"); |
||||
rc = -EINVAL; |
||||
goto error; |
||||
} |
||||
xgene_msi->msi_addr = res->start; |
||||
|
||||
xgene_msi->num_cpus = num_possible_cpus(); |
||||
|
||||
rc = xgene_msi_init_allocator(xgene_msi); |
||||
if (rc) { |
||||
dev_err(&pdev->dev, "Error allocating MSI bitmap\n"); |
||||
goto error; |
||||
} |
||||
|
||||
rc = xgene_allocate_domains(xgene_msi); |
||||
if (rc) { |
||||
dev_err(&pdev->dev, "Failed to allocate MSI domain\n"); |
||||
goto error; |
||||
} |
||||
|
||||
for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { |
||||
virt_msir = platform_get_irq(pdev, irq_index); |
||||
if (virt_msir < 0) { |
||||
dev_err(&pdev->dev, "Cannot translate IRQ index %d\n", |
||||
irq_index); |
||||
rc = -EINVAL; |
||||
goto error; |
||||
} |
||||
xgene_msi->msi_groups[irq_index].gic_irq = virt_msir; |
||||
xgene_msi->msi_groups[irq_index].msi_grp = irq_index; |
||||
xgene_msi->msi_groups[irq_index].msi = xgene_msi; |
||||
} |
||||
|
||||
/*
|
||||
* MSInIRx registers are read-to-clear; before registering |
||||
* interrupt handlers, read all of them to clear spurious |
||||
* interrupts that may occur before the driver is probed. |
||||
*/ |
||||
for (irq_index = 0; irq_index < NR_HW_IRQS; irq_index++) { |
||||
for (msi_idx = 0; msi_idx < IDX_PER_GROUP; msi_idx++) |
||||
msi_val = xgene_msi_ir_read(xgene_msi, irq_index, |
||||
msi_idx); |
||||
/* Read MSIINTn to confirm */ |
||||
msi_val = xgene_msi_int_read(xgene_msi, irq_index); |
||||
if (msi_val) { |
||||
dev_err(&pdev->dev, "Failed to clear spurious IRQ\n"); |
||||
rc = -EINVAL; |
||||
goto error; |
||||
} |
||||
} |
||||
|
||||
cpu_notifier_register_begin(); |
||||
|
||||
for_each_online_cpu(cpu) |
||||
if (xgene_msi_hwirq_alloc(cpu)) { |
||||
dev_err(&pdev->dev, "failed to register MSI handlers\n"); |
||||
cpu_notifier_register_done(); |
||||
goto error; |
||||
} |
||||
|
||||
rc = __register_hotcpu_notifier(&xgene_msi_cpu_notifier); |
||||
if (rc) { |
||||
dev_err(&pdev->dev, "failed to add CPU MSI notifier\n"); |
||||
cpu_notifier_register_done(); |
||||
goto error; |
||||
} |
||||
|
||||
cpu_notifier_register_done(); |
||||
|
||||
xgene_msi->mchip.of_node = pdev->dev.of_node; |
||||
rc = of_pci_msi_chip_add(&xgene_msi->mchip); |
||||
if (rc) { |
||||
dev_err(&pdev->dev, "failed to add MSI controller chip\n"); |
||||
goto error_notifier; |
||||
} |
||||
|
||||
dev_info(&pdev->dev, "APM X-Gene PCIe MSI driver loaded\n"); |
||||
|
||||
return 0; |
||||
|
||||
error_notifier: |
||||
unregister_hotcpu_notifier(&xgene_msi_cpu_notifier); |
||||
error: |
||||
xgene_msi_remove(pdev); |
||||
return rc; |
||||
} |
||||
|
||||
static struct platform_driver xgene_msi_driver = { |
||||
.driver = { |
||||
.name = "xgene-msi", |
||||
.owner = THIS_MODULE, |
||||
.of_match_table = xgene_msi_match_table, |
||||
}, |
||||
.probe = xgene_msi_probe, |
||||
.remove = xgene_msi_remove, |
||||
}; |
||||
|
||||
static int __init xgene_pcie_msi_init(void) |
||||
{ |
||||
return platform_driver_register(&xgene_msi_driver); |
||||
} |
||||
subsys_initcall(xgene_pcie_msi_init); |
||||
@ -0,0 +1,110 @@ |
||||
/*
|
||||
* Copyright (C) 2015 Broadcom Corporation |
||||
* Copyright (C) 2015 Hauke Mehrtens <hauke@hauke-m.de> |
||||
* |
||||
* This program is free software; you can redistribute it and/or |
||||
* modify it under the terms of the GNU General Public License as |
||||
* published by the Free Software Foundation version 2. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/pci.h> |
||||
#include <linux/module.h> |
||||
#include <linux/slab.h> |
||||
#include <linux/phy/phy.h> |
||||
#include <linux/bcma/bcma.h> |
||||
#include <linux/ioport.h> |
||||
|
||||
#include "pcie-iproc.h" |
||||
|
||||
|
||||
/* NS: CLASS field is R/O, and set to wrong 0x200 value */ |
||||
static void bcma_pcie2_fixup_class(struct pci_dev *dev) |
||||
{ |
||||
dev->class = PCI_CLASS_BRIDGE_PCI << 8; |
||||
} |
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8011, bcma_pcie2_fixup_class); |
||||
DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_BROADCOM, 0x8012, bcma_pcie2_fixup_class); |
||||
|
||||
static int iproc_pcie_bcma_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
||||
{ |
||||
struct pci_sys_data *sys = dev->sysdata; |
||||
struct iproc_pcie *pcie = sys->private_data; |
||||
struct bcma_device *bdev = container_of(pcie->dev, struct bcma_device, dev); |
||||
|
||||
return bcma_core_irq(bdev, 5); |
||||
} |
||||
|
||||
static int iproc_pcie_bcma_probe(struct bcma_device *bdev) |
||||
{ |
||||
struct iproc_pcie *pcie; |
||||
LIST_HEAD(res); |
||||
struct resource res_mem; |
||||
int ret; |
||||
|
||||
pcie = devm_kzalloc(&bdev->dev, sizeof(*pcie), GFP_KERNEL); |
||||
if (!pcie) |
||||
return -ENOMEM; |
||||
|
||||
pcie->dev = &bdev->dev; |
||||
bcma_set_drvdata(bdev, pcie); |
||||
|
||||
pcie->base = bdev->io_addr; |
||||
|
||||
res_mem.start = bdev->addr_s[0]; |
||||
res_mem.end = bdev->addr_s[0] + SZ_128M - 1; |
||||
res_mem.name = "PCIe MEM space"; |
||||
res_mem.flags = IORESOURCE_MEM; |
||||
pci_add_resource(&res, &res_mem); |
||||
|
||||
pcie->map_irq = iproc_pcie_bcma_map_irq; |
||||
|
||||
ret = iproc_pcie_setup(pcie, &res); |
||||
if (ret) |
||||
dev_err(pcie->dev, "PCIe controller setup failed\n"); |
||||
|
||||
pci_free_resource_list(&res); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void iproc_pcie_bcma_remove(struct bcma_device *bdev) |
||||
{ |
||||
struct iproc_pcie *pcie = bcma_get_drvdata(bdev); |
||||
|
||||
iproc_pcie_remove(pcie); |
||||
} |
||||
|
||||
static const struct bcma_device_id iproc_pcie_bcma_table[] = { |
||||
BCMA_CORE(BCMA_MANUF_BCM, BCMA_CORE_NS_PCIEG2, BCMA_ANY_REV, BCMA_ANY_CLASS), |
||||
{}, |
||||
}; |
||||
MODULE_DEVICE_TABLE(bcma, iproc_pcie_bcma_table); |
||||
|
||||
static struct bcma_driver iproc_pcie_bcma_driver = { |
||||
.name = KBUILD_MODNAME, |
||||
.id_table = iproc_pcie_bcma_table, |
||||
.probe = iproc_pcie_bcma_probe, |
||||
.remove = iproc_pcie_bcma_remove, |
||||
}; |
||||
|
||||
static int __init iproc_pcie_bcma_init(void) |
||||
{ |
||||
return bcma_driver_register(&iproc_pcie_bcma_driver); |
||||
} |
||||
module_init(iproc_pcie_bcma_init); |
||||
|
||||
static void __exit iproc_pcie_bcma_exit(void) |
||||
{ |
||||
bcma_driver_unregister(&iproc_pcie_bcma_driver); |
||||
} |
||||
module_exit(iproc_pcie_bcma_exit); |
||||
|
||||
MODULE_AUTHOR("Hauke Mehrtens"); |
||||
MODULE_DESCRIPTION("Broadcom iProc PCIe BCMA driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
Loading…
Reference in new issue