Disintegrate asm/system.h for Tile. Signed-off-by: David Howells <dhowells@redhat.com> Acked-by: Chris Metcalf <cmetcalf@tilera.com>tirimbino
David Howells
13 years ago
parent
d550bbd40c
commit
bd119c6923
@ -0,0 +1,148 @@ |
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation, version 2. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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* NON INFRINGEMENT. See the GNU General Public License for |
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* more details. |
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*/ |
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|
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#ifndef _ASM_TILE_BARRIER_H |
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#define _ASM_TILE_BARRIER_H |
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#ifndef __ASSEMBLY__ |
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#include <linux/types.h> |
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#include <arch/chip.h> |
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#include <arch/spr_def.h> |
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#include <asm/timex.h> |
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|
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads |
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* depend on. |
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* |
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* No data-dependent reads from memory-like regions are ever reordered |
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* over this barrier. All reads preceding this primitive are guaranteed |
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* to access memory (but not necessarily other CPUs' caches) before any |
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* reads following this primitive that depend on the data return by |
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* any of the preceding reads. This primitive is much lighter weight than |
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* rmb() on most CPUs, and is never heavier weight than is |
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* rmb(). |
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* |
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* These ordering constraints are respected by both the local CPU |
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* and the compiler. |
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* |
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* Ordering is not guaranteed by anything other than these primitives, |
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* not even by data dependencies. See the documentation for |
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* memory_barrier() for examples and URLs to more information. |
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* |
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* For example, the following code would force ordering (the initial |
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* value of "a" is zero, "b" is one, and "p" is "&a"): |
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* |
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* <programlisting> |
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* CPU 0 CPU 1 |
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* |
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* b = 2; |
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* memory_barrier(); |
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* p = &b; q = p; |
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* read_barrier_depends(); |
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* d = *q; |
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* </programlisting> |
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* |
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* because the read of "*q" depends on the read of "p" and these |
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* two reads are separated by a read_barrier_depends(). However, |
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* the following code, with the same initial values for "a" and "b": |
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* |
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* <programlisting> |
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* CPU 0 CPU 1 |
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* |
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* a = 2; |
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* memory_barrier(); |
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* b = 3; y = b; |
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* read_barrier_depends(); |
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* x = a; |
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* </programlisting> |
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* |
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* does not enforce ordering, since there is no data dependency between |
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* the read of "a" and the read of "b". Therefore, on some CPUs, such |
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() |
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* in cases like this where there are no data dependencies. |
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*/ |
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#define read_barrier_depends() do { } while (0) |
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#define __sync() __insn_mf() |
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#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() |
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#include <hv/syscall_public.h> |
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/*
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* Issue an uncacheable load to each memory controller, then |
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* wait until those loads have completed. |
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*/ |
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static inline void __mb_incoherent(void) |
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{ |
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long clobber_r10; |
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asm volatile("swint2" |
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: "=R10" (clobber_r10) |
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: "R10" (HV_SYS_fence_incoherent) |
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: "r0", "r1", "r2", "r3", "r4", |
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"r5", "r6", "r7", "r8", "r9", |
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"r11", "r12", "r13", "r14", |
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"r15", "r16", "r17", "r18", "r19", |
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"r20", "r21", "r22", "r23", "r24", |
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"r25", "r26", "r27", "r28", "r29"); |
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} |
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#endif |
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/* Fence to guarantee visibility of stores to incoherent memory. */ |
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static inline void |
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mb_incoherent(void) |
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{ |
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__insn_mf(); |
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#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() |
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{ |
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#if CHIP_HAS_TILE_WRITE_PENDING() |
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const unsigned long WRITE_TIMEOUT_CYCLES = 400; |
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unsigned long start = get_cycles_low(); |
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do { |
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if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0) |
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return; |
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} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES); |
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#endif /* CHIP_HAS_TILE_WRITE_PENDING() */ |
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(void) __mb_incoherent(); |
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} |
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#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */ |
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} |
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#define fast_wmb() __sync() |
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#define fast_rmb() __sync() |
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#define fast_mb() __sync() |
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#define fast_iob() mb_incoherent() |
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#define wmb() fast_wmb() |
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#define rmb() fast_rmb() |
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#define mb() fast_mb() |
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#define iob() fast_iob() |
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#ifdef CONFIG_SMP |
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#define smp_mb() mb() |
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#define smp_rmb() rmb() |
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#define smp_wmb() wmb() |
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#define smp_read_barrier_depends() read_barrier_depends() |
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#else |
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#define smp_mb() barrier() |
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#define smp_rmb() barrier() |
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#define smp_wmb() barrier() |
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#define smp_read_barrier_depends() do { } while (0) |
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#endif |
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#define set_mb(var, value) \ |
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do { var = value; mb(); } while (0) |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* _ASM_TILE_BARRIER_H */ |
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@ -0,0 +1,20 @@ |
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation, version 2. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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* NON INFRINGEMENT. See the GNU General Public License for |
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* more details. |
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*/ |
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#ifndef _ASM_TILE_EXEC_H |
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#define _ASM_TILE_EXEC_H |
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#define arch_align_stack(x) (x) |
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#endif /* _ASM_TILE_EXEC_H */ |
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@ -0,0 +1,76 @@ |
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation, version 2. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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* NON INFRINGEMENT. See the GNU General Public License for |
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* more details. |
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*/ |
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#ifndef _ASM_TILE_SWITCH_TO_H |
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#define _ASM_TILE_SWITCH_TO_H |
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#include <arch/sim_def.h> |
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/*
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* switch_to(n) should switch tasks to task nr n, first |
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* checking that n isn't the current task, in which case it does nothing. |
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* The number of callee-saved registers saved on the kernel stack |
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* is defined here for use in copy_thread() and must agree with __switch_to(). |
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*/ |
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#define CALLEE_SAVED_FIRST_REG 30 |
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#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */ |
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#ifndef __ASSEMBLY__ |
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struct task_struct; |
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/*
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* Pause the DMA engine and static network before task switching. |
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*/ |
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#define prepare_arch_switch(next) _prepare_arch_switch(next) |
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void _prepare_arch_switch(struct task_struct *next); |
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struct task_struct; |
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#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next))) |
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extern struct task_struct *_switch_to(struct task_struct *prev, |
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struct task_struct *next); |
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/* Helper function for _switch_to(). */ |
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extern struct task_struct *__switch_to(struct task_struct *prev, |
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struct task_struct *next, |
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unsigned long new_system_save_k_0); |
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/* Address that switched-away from tasks are at. */ |
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extern unsigned long get_switch_to_pc(void); |
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/*
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* Kernel threads can check to see if they need to migrate their |
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* stack whenever they return from a context switch; for user |
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* threads, we defer until they are returning to user-space. |
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*/ |
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#define finish_arch_switch(prev) do { \ |
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if (unlikely((prev)->state == TASK_DEAD)) \
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
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((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
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(current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
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if (current->mm == NULL && !kstack_hash && \
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current_thread_info()->homecache_cpu != smp_processor_id()) \
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homecache_migrate_kthread(); \
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} while (0) |
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/* Support function for forking a new task. */ |
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void ret_from_fork(void); |
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/* Called from ret_from_fork() when a new process starts up. */ |
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struct task_struct *sim_notify_fork(struct task_struct *prev); |
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#endif /* !__ASSEMBLY__ */ |
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#endif /* _ASM_TILE_SWITCH_TO_H */ |
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@ -1,261 +1,4 @@ |
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/*
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* Copyright 2010 Tilera Corporation. All Rights Reserved. |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License |
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* as published by the Free Software Foundation, version 2. |
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* |
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* This program is distributed in the hope that it will be useful, but |
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* WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or |
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* NON INFRINGEMENT. See the GNU General Public License for |
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* more details. |
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*/ |
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#ifndef _ASM_TILE_SYSTEM_H |
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#define _ASM_TILE_SYSTEM_H |
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#ifndef __ASSEMBLY__ |
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#include <linux/types.h> |
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#include <linux/irqflags.h> |
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/* NOTE: we can't include <linux/ptrace.h> due to #include dependencies. */ |
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#include <asm/ptrace.h> |
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#include <arch/chip.h> |
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#include <arch/sim_def.h> |
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#include <arch/spr_def.h> |
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|
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/*
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* read_barrier_depends - Flush all pending reads that subsequents reads |
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* depend on. |
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* |
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* No data-dependent reads from memory-like regions are ever reordered |
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* over this barrier. All reads preceding this primitive are guaranteed |
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* to access memory (but not necessarily other CPUs' caches) before any |
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* reads following this primitive that depend on the data return by |
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* any of the preceding reads. This primitive is much lighter weight than |
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* rmb() on most CPUs, and is never heavier weight than is |
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* rmb(). |
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* |
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* These ordering constraints are respected by both the local CPU |
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* and the compiler. |
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* |
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* Ordering is not guaranteed by anything other than these primitives, |
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* not even by data dependencies. See the documentation for |
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* memory_barrier() for examples and URLs to more information. |
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* |
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* For example, the following code would force ordering (the initial |
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* value of "a" is zero, "b" is one, and "p" is "&a"): |
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* |
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* <programlisting> |
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* CPU 0 CPU 1 |
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* |
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* b = 2; |
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* memory_barrier(); |
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* p = &b; q = p; |
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* read_barrier_depends(); |
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* d = *q; |
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* </programlisting> |
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* |
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* because the read of "*q" depends on the read of "p" and these |
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* two reads are separated by a read_barrier_depends(). However, |
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* the following code, with the same initial values for "a" and "b": |
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* |
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* <programlisting> |
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* CPU 0 CPU 1 |
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* |
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* a = 2; |
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* memory_barrier(); |
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* b = 3; y = b; |
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* read_barrier_depends(); |
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* x = a; |
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* </programlisting> |
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* |
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* does not enforce ordering, since there is no data dependency between |
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* the read of "a" and the read of "b". Therefore, on some CPUs, such |
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* as Alpha, "y" could be set to 3 and "x" to 0. Use rmb() |
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* in cases like this where there are no data dependencies. |
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*/ |
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#define read_barrier_depends() do { } while (0) |
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#define __sync() __insn_mf() |
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#if CHIP_HAS_SPLIT_CYCLE() |
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#define get_cycles_low() __insn_mfspr(SPR_CYCLE_LOW) |
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#else |
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#define get_cycles_low() __insn_mfspr(SPR_CYCLE) /* just get all 64 bits */ |
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#endif |
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#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() |
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#include <hv/syscall_public.h> |
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/*
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* Issue an uncacheable load to each memory controller, then |
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* wait until those loads have completed. |
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*/ |
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static inline void __mb_incoherent(void) |
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{ |
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long clobber_r10; |
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asm volatile("swint2" |
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: "=R10" (clobber_r10) |
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: "R10" (HV_SYS_fence_incoherent) |
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: "r0", "r1", "r2", "r3", "r4", |
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"r5", "r6", "r7", "r8", "r9", |
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"r11", "r12", "r13", "r14", |
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"r15", "r16", "r17", "r18", "r19", |
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"r20", "r21", "r22", "r23", "r24", |
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"r25", "r26", "r27", "r28", "r29"); |
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} |
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#endif |
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/* Fence to guarantee visibility of stores to incoherent memory. */ |
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static inline void |
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mb_incoherent(void) |
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{ |
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__insn_mf(); |
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#if !CHIP_HAS_MF_WAITS_FOR_VICTIMS() |
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{ |
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#if CHIP_HAS_TILE_WRITE_PENDING() |
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const unsigned long WRITE_TIMEOUT_CYCLES = 400; |
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unsigned long start = get_cycles_low(); |
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do { |
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if (__insn_mfspr(SPR_TILE_WRITE_PENDING) == 0) |
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return; |
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} while ((get_cycles_low() - start) < WRITE_TIMEOUT_CYCLES); |
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#endif /* CHIP_HAS_TILE_WRITE_PENDING() */ |
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(void) __mb_incoherent(); |
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} |
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#endif /* CHIP_HAS_MF_WAITS_FOR_VICTIMS() */ |
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} |
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#define fast_wmb() __sync() |
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#define fast_rmb() __sync() |
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#define fast_mb() __sync() |
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#define fast_iob() mb_incoherent() |
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#define wmb() fast_wmb() |
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#define rmb() fast_rmb() |
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#define mb() fast_mb() |
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#define iob() fast_iob() |
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#ifdef CONFIG_SMP |
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#define smp_mb() mb() |
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#define smp_rmb() rmb() |
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#define smp_wmb() wmb() |
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#define smp_read_barrier_depends() read_barrier_depends() |
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#else |
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#define smp_mb() barrier() |
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#define smp_rmb() barrier() |
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#define smp_wmb() barrier() |
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#define smp_read_barrier_depends() do { } while (0) |
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#endif |
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#define set_mb(var, value) \ |
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do { var = value; mb(); } while (0) |
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/*
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* Pause the DMA engine and static network before task switching. |
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*/ |
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#define prepare_arch_switch(next) _prepare_arch_switch(next) |
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void _prepare_arch_switch(struct task_struct *next); |
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/*
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* switch_to(n) should switch tasks to task nr n, first |
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* checking that n isn't the current task, in which case it does nothing. |
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* The number of callee-saved registers saved on the kernel stack |
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* is defined here for use in copy_thread() and must agree with __switch_to(). |
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*/ |
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#endif /* !__ASSEMBLY__ */ |
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#define CALLEE_SAVED_FIRST_REG 30 |
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#define CALLEE_SAVED_REGS_COUNT 24 /* r30 to r52, plus an empty to align */ |
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#ifndef __ASSEMBLY__ |
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struct task_struct; |
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#define switch_to(prev, next, last) ((last) = _switch_to((prev), (next))) |
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extern struct task_struct *_switch_to(struct task_struct *prev, |
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struct task_struct *next); |
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|
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/* Helper function for _switch_to(). */ |
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extern struct task_struct *__switch_to(struct task_struct *prev, |
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struct task_struct *next, |
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unsigned long new_system_save_k_0); |
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/* Address that switched-away from tasks are at. */ |
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extern unsigned long get_switch_to_pc(void); |
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/*
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* On SMP systems, when the scheduler does migration-cost autodetection, |
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* it needs a way to flush as much of the CPU's caches as possible: |
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* |
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* TODO: fill this in! |
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*/ |
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static inline void sched_cacheflush(void) |
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{ |
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} |
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#define arch_align_stack(x) (x) |
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/*
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* Is the kernel doing fixups of unaligned accesses? If <0, no kernel |
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* intervention occurs and SIGBUS is delivered with no data address |
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* info. If 0, the kernel single-steps the instruction to discover |
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* the data address to provide with the SIGBUS. If 1, the kernel does |
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* a fixup. |
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*/ |
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extern int unaligned_fixup; |
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/* Is the kernel printing on each unaligned fixup? */ |
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extern int unaligned_printk; |
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/* Number of unaligned fixups performed */ |
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extern unsigned int unaligned_fixup_count; |
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/* Init-time routine to do tile-specific per-cpu setup. */ |
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void setup_cpu(int boot); |
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/* User-level DMA management functions */ |
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void grant_dma_mpls(void); |
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void restrict_dma_mpls(void); |
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#ifdef CONFIG_HARDWALL |
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/* User-level network management functions */ |
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void reset_network_state(void); |
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void grant_network_mpls(void); |
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void restrict_network_mpls(void); |
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int hardwall_deactivate(struct task_struct *task); |
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/* Hook hardwall code into changes in affinity. */ |
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#define arch_set_cpus_allowed(p, new_mask) do { \ |
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if (p->thread.hardwall && !cpumask_equal(&p->cpus_allowed, new_mask)) \
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hardwall_deactivate(p); \
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} while (0) |
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#endif |
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|
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/*
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* Kernel threads can check to see if they need to migrate their |
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* stack whenever they return from a context switch; for user |
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* threads, we defer until they are returning to user-space. |
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*/ |
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#define finish_arch_switch(prev) do { \ |
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if (unlikely((prev)->state == TASK_DEAD)) \
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_EXIT | \
|
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((prev)->pid << _SIM_CONTROL_OPERATOR_BITS)); \
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__insn_mtspr(SPR_SIM_CONTROL, SIM_CONTROL_OS_SWITCH | \
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(current->pid << _SIM_CONTROL_OPERATOR_BITS)); \
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if (current->mm == NULL && !kstack_hash && \
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current_thread_info()->homecache_cpu != smp_processor_id()) \
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homecache_migrate_kthread(); \
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} while (0) |
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|
||||
/* Support function for forking a new task. */ |
||||
void ret_from_fork(void); |
||||
|
||||
/* Called from ret_from_fork() when a new process starts up. */ |
||||
struct task_struct *sim_notify_fork(struct task_struct *prev); |
||||
|
||||
#endif /* !__ASSEMBLY__ */ |
||||
|
||||
#endif /* _ASM_TILE_SYSTEM_H */ |
||||
/* FILE TO BE DELETED. DO NOT ADD STUFF HERE! */ |
||||
#include <asm/barrier.h> |
||||
#include <asm/exec.h> |
||||
#include <asm/switch_to.h> |
||||
|
||||
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Reference in new issue