This patch removes supporting codes for s5pc100 because no more used now. [jason@lakedaemon.net: for drivers/irqchip/Kconfig] Acked-by: Jason Cooper <jason@lakedaemon.net> Acked-by: Arnd Bergmann <arnd@arndb.de> Cc: Russell King <rmk+kernel@arm.linux.org.uk> Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>tirimbino
Kukjin Kim
11 years ago
parent
8340417c66
commit
b8529ec1c1
@ -1,49 +0,0 @@ |
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CONFIG_EXPERIMENTAL=y |
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CONFIG_SYSFS_DEPRECATED_V2=y |
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CONFIG_BLK_DEV_INITRD=y |
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CONFIG_KALLSYMS_ALL=y |
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CONFIG_MODULES=y |
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CONFIG_MODULE_UNLOAD=y |
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# CONFIG_BLK_DEV_BSG is not set |
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CONFIG_ARCH_S5PC100=y |
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CONFIG_MACH_SMDKC100=y |
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CONFIG_AEABI=y |
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CONFIG_CMDLINE="root=/dev/mtdblock2 rootfstype=cramfs init=/linuxrc console=ttySAC2,115200 mem=128M" |
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CONFIG_UEVENT_HELPER_PATH="/sbin/hotplug" |
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CONFIG_BLK_DEV_LOOP=y |
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CONFIG_BLK_DEV_RAM=y |
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CONFIG_BLK_DEV_RAM_SIZE=8192 |
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CONFIG_EEPROM_AT24=y |
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CONFIG_SERIAL_8250=y |
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CONFIG_SERIAL_SAMSUNG=y |
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CONFIG_SERIAL_SAMSUNG_CONSOLE=y |
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CONFIG_HW_RANDOM=y |
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CONFIG_I2C=y |
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CONFIG_I2C_CHARDEV=y |
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# CONFIG_VGA_CONSOLE is not set |
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CONFIG_MMC=y |
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CONFIG_MMC_DEBUG=y |
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CONFIG_MMC_UNSAFE_RESUME=y |
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CONFIG_SDIO_UART=y |
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CONFIG_MMC_SDHCI=y |
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CONFIG_EXT2_FS=y |
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CONFIG_EXT3_FS=y |
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CONFIG_EXT3_FS_POSIX_ACL=y |
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CONFIG_EXT3_FS_SECURITY=y |
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CONFIG_INOTIFY=y |
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CONFIG_TMPFS=y |
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CONFIG_TMPFS_POSIX_ACL=y |
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CONFIG_CRAMFS=y |
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CONFIG_ROMFS_FS=y |
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CONFIG_MAGIC_SYSRQ=y |
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CONFIG_DEBUG_KERNEL=y |
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CONFIG_DEBUG_RT_MUTEXES=y |
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CONFIG_DEBUG_SPINLOCK=y |
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CONFIG_DEBUG_MUTEXES=y |
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CONFIG_DEBUG_SPINLOCK_SLEEP=y |
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CONFIG_DEBUG_INFO=y |
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# CONFIG_RCU_CPU_STALL_DETECTOR is not set |
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CONFIG_SYSCTL_SYSCALL_CHECK=y |
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CONFIG_DEBUG_USER=y |
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CONFIG_DEBUG_ERRORS=y |
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CONFIG_DEBUG_LL=y |
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@ -1,81 +0,0 @@ |
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# Copyright 2009 Samsung Electronics Co. |
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# Byungho Min <bhmin@samsung.com> |
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# |
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# Licensed under GPLv2 |
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|
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# Configuration options for the S5PC100 CPU |
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|
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if ARCH_S5PC100 |
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config CPU_S5PC100 |
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bool |
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select ARM_AMBA |
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select PL330_DMA if DMADEVICES |
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select S5P_EXT_INT |
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help |
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Enable S5PC100 CPU support |
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|
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config S5PC100_SETUP_FB_24BPP |
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bool |
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help |
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Common setup code for S5PC1XX with an 24bpp RGB display helper. |
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config S5PC100_SETUP_I2C1 |
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bool |
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help |
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Common setup code for i2c bus 1. |
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config S5PC100_SETUP_IDE |
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bool |
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help |
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Common setup code for S5PC100 IDE GPIO configurations |
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|
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config S5PC100_SETUP_KEYPAD |
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bool |
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help |
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Common setup code for KEYPAD GPIO configurations. |
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config S5PC100_SETUP_SDHCI |
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bool |
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select S5PC100_SETUP_SDHCI_GPIO |
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help |
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Internal helper functions for S5PC100 based SDHCI systems |
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config S5PC100_SETUP_SDHCI_GPIO |
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bool |
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help |
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Common setup code for SDHCI gpio. |
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|
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config S5PC100_SETUP_SPI |
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bool |
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help |
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Common setup code for SPI GPIO configurations. |
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config MACH_SMDKC100 |
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bool "SMDKC100" |
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select CPU_S5PC100 |
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select S3C_DEV_FB |
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select S3C_DEV_HSMMC |
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select S3C_DEV_HSMMC1 |
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select S3C_DEV_HSMMC2 |
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select S3C_DEV_I2C1 |
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select S3C_DEV_RTC |
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select S3C_DEV_WDT |
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select S5PC100_SETUP_FB_24BPP |
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select S5PC100_SETUP_I2C1 |
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select S5PC100_SETUP_IDE |
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select S5PC100_SETUP_KEYPAD |
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select S5PC100_SETUP_SDHCI |
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select S5P_DEV_FIMC0 |
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select S5P_DEV_FIMC1 |
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select S5P_DEV_FIMC2 |
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select SAMSUNG_DEV_ADC |
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select SAMSUNG_DEV_BACKLIGHT |
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select SAMSUNG_DEV_IDE |
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select SAMSUNG_DEV_KEYPAD |
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select SAMSUNG_DEV_PWM |
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select SAMSUNG_DEV_TS |
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help |
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Machine support for the Samsung SMDKC100 |
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endif |
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@ -1,32 +0,0 @@ |
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# arch/arm/mach-s5pc100/Makefile
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#
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# Copyright 2009 Samsung Electronics Co.
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#
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# Licensed under GPLv2
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obj-y :=
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obj-m :=
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obj-n :=
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obj- :=
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# Core
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obj-y += common.o clock.o
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obj-y += dma.o
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# machine support
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obj-$(CONFIG_MACH_SMDKC100) += mach-smdkc100.o
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# device support
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obj-y += dev-audio.o
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obj-y += setup-i2c0.o
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obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
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obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
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obj-$(CONFIG_S5PC100_SETUP_IDE) += setup-ide.o
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obj-$(CONFIG_S5PC100_SETUP_KEYPAD) += setup-keypad.o
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obj-$(CONFIG_S5PC100_SETUP_SDHCI_GPIO) += setup-sdhci-gpio.o
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obj-$(CONFIG_S5PC100_SETUP_SPI) += setup-spi.o
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@ -1,2 +0,0 @@ |
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zreladdr-y += 0x20008000
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params_phys-y := 0x20000100
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File diff suppressed because it is too large
Load Diff
@ -1,255 +0,0 @@ |
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/*
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* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com
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* |
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* Copyright 2009 Samsung Electronics Co. |
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* Byungho Min <bhmin@samsung.com> |
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* |
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* Common Codes for S5PC100 |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/types.h> |
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#include <linux/interrupt.h> |
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#include <linux/list.h> |
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#include <linux/timer.h> |
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#include <linux/init.h> |
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/device.h> |
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#include <linux/serial_core.h> |
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#include <linux/serial_s3c.h> |
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#include <clocksource/samsung_pwm.h> |
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#include <linux/platform_device.h> |
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#include <linux/sched.h> |
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#include <linux/reboot.h> |
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#include <asm/irq.h> |
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#include <asm/proc-fns.h> |
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#include <asm/system_misc.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include <asm/mach/irq.h> |
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#include <mach/map.h> |
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#include <mach/hardware.h> |
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#include <mach/regs-clock.h> |
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#include <plat/cpu.h> |
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#include <plat/devs.h> |
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#include <plat/clock.h> |
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#include <plat/sdhci.h> |
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#include <plat/adc-core.h> |
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#include <plat/ata-core.h> |
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#include <plat/fb-core.h> |
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#include <plat/iic-core.h> |
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#include <plat/onenand-core.h> |
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#include <plat/pwm-core.h> |
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#include <plat/spi-core.h> |
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#include <plat/watchdog-reset.h> |
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#include "common.h" |
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static const char name_s5pc100[] = "S5PC100"; |
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static struct cpu_table cpu_ids[] __initdata = { |
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{ |
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.idcode = S5PC100_CPU_ID, |
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.idmask = S5PC100_CPU_MASK, |
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.map_io = s5pc100_map_io, |
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.init_clocks = s5pc100_init_clocks, |
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.init_uarts = s5pc100_init_uarts, |
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.init = s5pc100_init, |
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.name = name_s5pc100, |
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}, |
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}; |
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/* Initial IO mappings */ |
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static struct map_desc s5pc100_iodesc[] __initdata = { |
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{ |
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.virtual = (unsigned long)S5P_VA_CHIPID, |
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.pfn = __phys_to_pfn(S5PC100_PA_CHIPID), |
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.length = SZ_4K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S3C_VA_SYS, |
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.pfn = __phys_to_pfn(S5PC100_PA_SYSCON), |
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.length = SZ_64K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S3C_VA_TIMER, |
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.pfn = __phys_to_pfn(S5PC100_PA_TIMER), |
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.length = SZ_16K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S3C_VA_WATCHDOG, |
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.pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG), |
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.length = SZ_4K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S5P_VA_SROMC, |
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.pfn = __phys_to_pfn(S5PC100_PA_SROMC), |
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.length = SZ_4K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S5P_VA_SYSTIMER, |
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.pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER), |
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.length = SZ_16K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S5P_VA_GPIO, |
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.pfn = __phys_to_pfn(S5PC100_PA_GPIO), |
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.length = SZ_4K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)VA_VIC0, |
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.pfn = __phys_to_pfn(S5PC100_PA_VIC0), |
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.length = SZ_16K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)VA_VIC1, |
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.pfn = __phys_to_pfn(S5PC100_PA_VIC1), |
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.length = SZ_16K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)VA_VIC2, |
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.pfn = __phys_to_pfn(S5PC100_PA_VIC2), |
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.length = SZ_16K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S3C_VA_UART, |
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.pfn = __phys_to_pfn(S3C_PA_UART), |
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.length = SZ_512K, |
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.type = MT_DEVICE, |
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}, { |
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.virtual = (unsigned long)S5PC100_VA_OTHERS, |
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.pfn = __phys_to_pfn(S5PC100_PA_OTHERS), |
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.length = SZ_4K, |
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.type = MT_DEVICE, |
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} |
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}; |
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static struct samsung_pwm_variant s5pc100_pwm_variant = { |
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.bits = 32, |
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.div_base = 0, |
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.has_tint_cstat = true, |
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.tclk_mask = (1 << 5), |
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}; |
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void __init samsung_set_timer_source(unsigned int event, unsigned int source) |
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{ |
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s5pc100_pwm_variant.output_mask = BIT(SAMSUNG_PWM_NUM) - 1; |
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s5pc100_pwm_variant.output_mask &= ~(BIT(event) | BIT(source)); |
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} |
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void __init samsung_timer_init(void) |
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{ |
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unsigned int timer_irqs[SAMSUNG_PWM_NUM] = { |
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IRQ_TIMER0_VIC, IRQ_TIMER1_VIC, IRQ_TIMER2_VIC, |
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IRQ_TIMER3_VIC, IRQ_TIMER4_VIC, |
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}; |
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samsung_pwm_clocksource_init(S3C_VA_TIMER, |
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timer_irqs, &s5pc100_pwm_variant); |
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} |
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/*
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* s5pc100_map_io |
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* |
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* register the standard CPU IO areas |
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*/ |
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void __init s5pc100_init_io(struct map_desc *mach_desc, int size) |
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{ |
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/* initialize the io descriptors we need for initialization */ |
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iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc)); |
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if (mach_desc) |
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iotable_init(mach_desc, size); |
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/* detect cpu id and rev. */ |
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s5p_init_cpu(S5P_VA_CHIPID); |
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s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids)); |
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samsung_pwm_set_platdata(&s5pc100_pwm_variant); |
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} |
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void __init s5pc100_map_io(void) |
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{ |
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/* initialise device information early */ |
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s5pc100_default_sdhci0(); |
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s5pc100_default_sdhci1(); |
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s5pc100_default_sdhci2(); |
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s3c_adc_setname("s3c64xx-adc"); |
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/* the i2c devices are directly compatible with s3c2440 */ |
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s3c_i2c0_setname("s3c2440-i2c"); |
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s3c_i2c1_setname("s3c2440-i2c"); |
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s3c_onenand_setname("s5pc100-onenand"); |
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s3c_fb_setname("s5pc100-fb"); |
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s3c_cfcon_setname("s5pc100-pata"); |
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s3c64xx_spi_setname("s5pc100-spi"); |
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} |
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void __init s5pc100_init_clocks(int xtal) |
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{ |
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printk(KERN_DEBUG "%s: initializing clocks\n", __func__); |
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s3c24xx_register_baseclocks(xtal); |
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s5p_register_clocks(xtal); |
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s5pc100_register_clocks(); |
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s5pc100_setup_clocks(); |
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samsung_wdt_reset_init(S3C_VA_WATCHDOG); |
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} |
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void __init s5pc100_init_irq(void) |
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{ |
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u32 vic[] = {~0, ~0, ~0}; |
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/* VIC0, VIC1, and VIC2 are fully populated. */ |
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s5p_init_irq(vic, ARRAY_SIZE(vic)); |
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} |
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static struct bus_type s5pc100_subsys = { |
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.name = "s5pc100-core", |
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.dev_name = "s5pc100-core", |
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}; |
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static struct device s5pc100_dev = { |
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.bus = &s5pc100_subsys, |
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}; |
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static int __init s5pc100_core_init(void) |
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{ |
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return subsys_system_register(&s5pc100_subsys, NULL); |
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} |
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core_initcall(s5pc100_core_init); |
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int __init s5pc100_init(void) |
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{ |
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printk(KERN_INFO "S5PC100: Initializing architecture\n"); |
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return device_register(&s5pc100_dev); |
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} |
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/* uart registration process */ |
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void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no) |
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{ |
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s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no); |
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} |
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void s5pc100_restart(enum reboot_mode mode, const char *cmd) |
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{ |
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if (mode != REBOOT_SOFT) |
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samsung_wdt_reset(); |
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soft_restart(0); |
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} |
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@ -1,30 +0,0 @@ |
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/*
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* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com
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* |
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* Common Header for S5PC100 machines |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __ARCH_ARM_MACH_S5PC100_COMMON_H |
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#define __ARCH_ARM_MACH_S5PC100_COMMON_H |
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#include <linux/reboot.h> |
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void s5pc100_init_io(struct map_desc *mach_desc, int size); |
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void s5pc100_init_irq(void); |
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void s5pc100_register_clocks(void); |
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void s5pc100_setup_clocks(void); |
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void s5pc100_restart(enum reboot_mode mode, const char *cmd); |
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extern int s5pc100_init(void); |
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extern void s5pc100_map_io(void); |
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extern void s5pc100_init_clocks(int xtal); |
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extern void s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no); |
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#endif /* __ARCH_ARM_MACH_S5PC100_COMMON_H */ |
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@ -1,239 +0,0 @@ |
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/* linux/arch/arm/mach-s5pc100/dev-audio.c
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* |
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* Copyright (c) 2010 Samsung Electronics Co. Ltd |
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* Jaswinder Singh <jassi.brar@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <linux/platform_device.h> |
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#include <linux/dma-mapping.h> |
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#include <linux/gpio.h> |
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#include <plat/gpio-cfg.h> |
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#include <linux/platform_data/asoc-s3c.h> |
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#include <mach/map.h> |
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#include <mach/dma.h> |
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#include <mach/irqs.h> |
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static int s5pc100_cfg_i2s(struct platform_device *pdev) |
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{ |
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/* configure GPIO for i2s port */ |
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switch (pdev->id) { |
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case 0: /* Dedicated pins */ |
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break; |
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case 1: |
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s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(2)); |
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break; |
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case 2: |
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s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(4)); |
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break; |
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default: |
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printk(KERN_ERR "Invalid Device %d\n", pdev->id); |
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return -EINVAL; |
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} |
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return 0; |
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} |
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static struct s3c_audio_pdata i2sv5_pdata = { |
||||
.cfg_gpio = s5pc100_cfg_i2s, |
||||
.type = { |
||||
.i2s = { |
||||
.quirks = QUIRK_PRI_6CHAN | QUIRK_SEC_DAI |
||||
| QUIRK_NEED_RSTCLR, |
||||
}, |
||||
}, |
||||
}; |
||||
|
||||
static struct resource s5pc100_iis0_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_I2S0, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_I2S0_TX), |
||||
[2] = DEFINE_RES_DMA(DMACH_I2S0_RX), |
||||
[3] = DEFINE_RES_DMA(DMACH_I2S0S_TX), |
||||
}; |
||||
|
||||
struct platform_device s5pc100_device_iis0 = { |
||||
.name = "samsung-i2s", |
||||
.id = 0, |
||||
.num_resources = ARRAY_SIZE(s5pc100_iis0_resource), |
||||
.resource = s5pc100_iis0_resource, |
||||
.dev = { |
||||
.platform_data = &i2sv5_pdata, |
||||
}, |
||||
}; |
||||
|
||||
static struct s3c_audio_pdata i2sv3_pdata = { |
||||
.cfg_gpio = s5pc100_cfg_i2s, |
||||
}; |
||||
|
||||
static struct resource s5pc100_iis1_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_I2S1, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_I2S1_TX), |
||||
[2] = DEFINE_RES_DMA(DMACH_I2S1_RX), |
||||
}; |
||||
|
||||
struct platform_device s5pc100_device_iis1 = { |
||||
.name = "samsung-i2s", |
||||
.id = 1, |
||||
.num_resources = ARRAY_SIZE(s5pc100_iis1_resource), |
||||
.resource = s5pc100_iis1_resource, |
||||
.dev = { |
||||
.platform_data = &i2sv3_pdata, |
||||
}, |
||||
}; |
||||
|
||||
static struct resource s5pc100_iis2_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_I2S2, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_I2S2_TX), |
||||
[2] = DEFINE_RES_DMA(DMACH_I2S2_RX), |
||||
}; |
||||
|
||||
struct platform_device s5pc100_device_iis2 = { |
||||
.name = "samsung-i2s", |
||||
.id = 2, |
||||
.num_resources = ARRAY_SIZE(s5pc100_iis2_resource), |
||||
.resource = s5pc100_iis2_resource, |
||||
.dev = { |
||||
.platform_data = &i2sv3_pdata, |
||||
}, |
||||
}; |
||||
|
||||
/* PCM Controller platform_devices */ |
||||
|
||||
static int s5pc100_pcm_cfg_gpio(struct platform_device *pdev) |
||||
{ |
||||
switch (pdev->id) { |
||||
case 0: |
||||
s3c_gpio_cfgpin_range(S5PC100_GPG3(0), 5, S3C_GPIO_SFN(5)); |
||||
break; |
||||
|
||||
case 1: |
||||
s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(3)); |
||||
break; |
||||
|
||||
default: |
||||
printk(KERN_DEBUG "Invalid PCM Controller number!"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct s3c_audio_pdata s3c_pcm_pdata = { |
||||
.cfg_gpio = s5pc100_pcm_cfg_gpio, |
||||
}; |
||||
|
||||
static struct resource s5pc100_pcm0_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_PCM0, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_PCM0_TX), |
||||
[2] = DEFINE_RES_DMA(DMACH_PCM0_RX), |
||||
}; |
||||
|
||||
struct platform_device s5pc100_device_pcm0 = { |
||||
.name = "samsung-pcm", |
||||
.id = 0, |
||||
.num_resources = ARRAY_SIZE(s5pc100_pcm0_resource), |
||||
.resource = s5pc100_pcm0_resource, |
||||
.dev = { |
||||
.platform_data = &s3c_pcm_pdata, |
||||
}, |
||||
}; |
||||
|
||||
static struct resource s5pc100_pcm1_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_PCM1, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_PCM1_TX), |
||||
[2] = DEFINE_RES_DMA(DMACH_PCM1_RX), |
||||
}; |
||||
|
||||
struct platform_device s5pc100_device_pcm1 = { |
||||
.name = "samsung-pcm", |
||||
.id = 1, |
||||
.num_resources = ARRAY_SIZE(s5pc100_pcm1_resource), |
||||
.resource = s5pc100_pcm1_resource, |
||||
.dev = { |
||||
.platform_data = &s3c_pcm_pdata, |
||||
}, |
||||
}; |
||||
|
||||
/* AC97 Controller platform devices */ |
||||
|
||||
static int s5pc100_ac97_cfg_gpio(struct platform_device *pdev) |
||||
{ |
||||
return s3c_gpio_cfgpin_range(S5PC100_GPC(0), 5, S3C_GPIO_SFN(4)); |
||||
} |
||||
|
||||
static struct resource s5pc100_ac97_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_AC97, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_AC97_PCMOUT), |
||||
[2] = DEFINE_RES_DMA(DMACH_AC97_PCMIN), |
||||
[3] = DEFINE_RES_DMA(DMACH_AC97_MICIN), |
||||
[4] = DEFINE_RES_IRQ(IRQ_AC97), |
||||
}; |
||||
|
||||
static struct s3c_audio_pdata s3c_ac97_pdata = { |
||||
.cfg_gpio = s5pc100_ac97_cfg_gpio, |
||||
}; |
||||
|
||||
static u64 s5pc100_ac97_dmamask = DMA_BIT_MASK(32); |
||||
|
||||
struct platform_device s5pc100_device_ac97 = { |
||||
.name = "samsung-ac97", |
||||
.id = -1, |
||||
.num_resources = ARRAY_SIZE(s5pc100_ac97_resource), |
||||
.resource = s5pc100_ac97_resource, |
||||
.dev = { |
||||
.platform_data = &s3c_ac97_pdata, |
||||
.dma_mask = &s5pc100_ac97_dmamask, |
||||
.coherent_dma_mask = DMA_BIT_MASK(32), |
||||
}, |
||||
}; |
||||
|
||||
/* S/PDIF Controller platform_device */ |
||||
static int s5pc100_spdif_cfg_gpd(struct platform_device *pdev) |
||||
{ |
||||
s3c_gpio_cfgpin_range(S5PC100_GPD(5), 2, S3C_GPIO_SFN(3)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int s5pc100_spdif_cfg_gpg3(struct platform_device *pdev) |
||||
{ |
||||
s3c_gpio_cfgpin_range(S5PC100_GPG3(5), 2, S3C_GPIO_SFN(3)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct resource s5pc100_spdif_resource[] = { |
||||
[0] = DEFINE_RES_MEM(S5PC100_PA_SPDIF, SZ_256), |
||||
[1] = DEFINE_RES_DMA(DMACH_SPDIF), |
||||
}; |
||||
|
||||
static struct s3c_audio_pdata s5p_spdif_pdata = { |
||||
.cfg_gpio = s5pc100_spdif_cfg_gpd, |
||||
}; |
||||
|
||||
static u64 s5pc100_spdif_dmamask = DMA_BIT_MASK(32); |
||||
|
||||
struct platform_device s5pc100_device_spdif = { |
||||
.name = "samsung-spdif", |
||||
.id = -1, |
||||
.num_resources = ARRAY_SIZE(s5pc100_spdif_resource), |
||||
.resource = s5pc100_spdif_resource, |
||||
.dev = { |
||||
.platform_data = &s5p_spdif_pdata, |
||||
.dma_mask = &s5pc100_spdif_dmamask, |
||||
.coherent_dma_mask = DMA_BIT_MASK(32), |
||||
}, |
||||
}; |
||||
|
||||
void __init s5pc100_spdif_setup_gpio(int gpio) |
||||
{ |
||||
if (gpio == S5PC100_SPDIF_GPD) |
||||
s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpd; |
||||
else |
||||
s5p_spdif_pdata.cfg_gpio = s5pc100_spdif_cfg_gpg3; |
||||
} |
||||
@ -1,130 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/dma.c
|
||||
* |
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com
|
||||
* |
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd. |
||||
* Jaswinder Singh <jassi.brar@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#include <linux/dma-mapping.h> |
||||
#include <linux/amba/bus.h> |
||||
#include <linux/amba/pl330.h> |
||||
|
||||
#include <asm/irq.h> |
||||
#include <plat/devs.h> |
||||
#include <plat/irqs.h> |
||||
|
||||
#include <mach/map.h> |
||||
#include <mach/irqs.h> |
||||
#include <mach/dma.h> |
||||
|
||||
static u8 pdma0_peri[] = { |
||||
DMACH_UART0_RX, |
||||
DMACH_UART0_TX, |
||||
DMACH_UART1_RX, |
||||
DMACH_UART1_TX, |
||||
DMACH_UART2_RX, |
||||
DMACH_UART2_TX, |
||||
DMACH_UART3_RX, |
||||
DMACH_UART3_TX, |
||||
DMACH_IRDA, |
||||
DMACH_I2S0_RX, |
||||
DMACH_I2S0_TX, |
||||
DMACH_I2S0S_TX, |
||||
DMACH_I2S1_RX, |
||||
DMACH_I2S1_TX, |
||||
DMACH_I2S2_RX, |
||||
DMACH_I2S2_TX, |
||||
DMACH_SPI0_RX, |
||||
DMACH_SPI0_TX, |
||||
DMACH_SPI1_RX, |
||||
DMACH_SPI1_TX, |
||||
DMACH_SPI2_RX, |
||||
DMACH_SPI2_TX, |
||||
DMACH_AC97_MICIN, |
||||
DMACH_AC97_PCMIN, |
||||
DMACH_AC97_PCMOUT, |
||||
DMACH_EXTERNAL, |
||||
DMACH_PWM, |
||||
DMACH_SPDIF, |
||||
DMACH_HSI_RX, |
||||
DMACH_HSI_TX, |
||||
}; |
||||
|
||||
static struct dma_pl330_platdata s5pc100_pdma0_pdata = { |
||||
.nr_valid_peri = ARRAY_SIZE(pdma0_peri), |
||||
.peri_id = pdma0_peri, |
||||
}; |
||||
|
||||
static AMBA_AHB_DEVICE(s5pc100_pdma0, "dma-pl330.0", 0x00041330, |
||||
S5PC100_PA_PDMA0, {IRQ_PDMA0}, &s5pc100_pdma0_pdata); |
||||
|
||||
static u8 pdma1_peri[] = { |
||||
DMACH_UART0_RX, |
||||
DMACH_UART0_TX, |
||||
DMACH_UART1_RX, |
||||
DMACH_UART1_TX, |
||||
DMACH_UART2_RX, |
||||
DMACH_UART2_TX, |
||||
DMACH_UART3_RX, |
||||
DMACH_UART3_TX, |
||||
DMACH_IRDA, |
||||
DMACH_I2S0_RX, |
||||
DMACH_I2S0_TX, |
||||
DMACH_I2S0S_TX, |
||||
DMACH_I2S1_RX, |
||||
DMACH_I2S1_TX, |
||||
DMACH_I2S2_RX, |
||||
DMACH_I2S2_TX, |
||||
DMACH_SPI0_RX, |
||||
DMACH_SPI0_TX, |
||||
DMACH_SPI1_RX, |
||||
DMACH_SPI1_TX, |
||||
DMACH_SPI2_RX, |
||||
DMACH_SPI2_TX, |
||||
DMACH_PCM0_RX, |
||||
DMACH_PCM0_TX, |
||||
DMACH_PCM1_RX, |
||||
DMACH_PCM1_TX, |
||||
DMACH_MSM_REQ0, |
||||
DMACH_MSM_REQ1, |
||||
DMACH_MSM_REQ2, |
||||
DMACH_MSM_REQ3, |
||||
}; |
||||
|
||||
static struct dma_pl330_platdata s5pc100_pdma1_pdata = { |
||||
.nr_valid_peri = ARRAY_SIZE(pdma1_peri), |
||||
.peri_id = pdma1_peri, |
||||
}; |
||||
|
||||
static AMBA_AHB_DEVICE(s5pc100_pdma1, "dma-pl330.1", 0x00041330, |
||||
S5PC100_PA_PDMA1, {IRQ_PDMA1}, &s5pc100_pdma1_pdata); |
||||
|
||||
static int __init s5pc100_dma_init(void) |
||||
{ |
||||
dma_cap_set(DMA_SLAVE, s5pc100_pdma0_pdata.cap_mask); |
||||
dma_cap_set(DMA_CYCLIC, s5pc100_pdma0_pdata.cap_mask); |
||||
amba_device_register(&s5pc100_pdma0_device, &iomem_resource); |
||||
|
||||
dma_cap_set(DMA_SLAVE, s5pc100_pdma1_pdata.cap_mask); |
||||
dma_cap_set(DMA_CYCLIC, s5pc100_pdma1_pdata.cap_mask); |
||||
amba_device_register(&s5pc100_pdma1_device, &iomem_resource); |
||||
|
||||
return 0; |
||||
} |
||||
arch_initcall(s5pc100_dma_init); |
||||
@ -1,39 +0,0 @@ |
||||
/* arch/arm/mach-s5pc100/include/mach/debug-macro.S |
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com>
|
||||
* |
||||
* |
||||
* Based on mach-s3c6400/include/mach/debug-macro.S |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
/* pull in the relevant register and map files. */ |
||||
|
||||
#include <linux/serial_s3c.h> |
||||
#include <mach/map.h> |
||||
|
||||
/* note, for the boot process to work we have to keep the UART |
||||
* virtual address aligned to an 1MiB boundary for the L1 |
||||
* mapping the head code makes. We keep the UART virtual address |
||||
* aligned and add in the offset when we load the value here. |
||||
*/ |
||||
|
||||
.macro addruart, rp, rv, tmp |
||||
ldr \rp, = S3C_PA_UART |
||||
ldr \rv, = S3C_VA_UART |
||||
#if CONFIG_DEBUG_S3C_UART != 0 |
||||
add \rp, \rp, #(0x400 * CONFIG_DEBUG_S3C_UART) |
||||
add \rv, \rv, #(0x400 * CONFIG_DEBUG_S3C_UART) |
||||
#endif |
||||
.endm |
||||
|
||||
/* include the reset of the code which will do the work, we're only |
||||
* compiling for a single cpu processor type so the default of s3c2440 |
||||
* will be fine with us. |
||||
*/ |
||||
|
||||
#include <debug/samsung.S> |
||||
@ -1,26 +0,0 @@ |
||||
/*
|
||||
* Copyright (C) 2010 Samsung Electronics Co. Ltd. |
||||
* Jaswinder Singh <jassi.brar@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License as published by |
||||
* the Free Software Foundation; either version 2 of the License, or |
||||
* (at your option) any later version. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
* |
||||
* You should have received a copy of the GNU General Public License |
||||
* along with this program; if not, write to the Free Software |
||||
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. |
||||
*/ |
||||
|
||||
#ifndef __MACH_DMA_H |
||||
#define __MACH_DMA_H |
||||
|
||||
/* This platform uses the common DMA API driver for PL330 */ |
||||
#include <plat/dma-pl330.h> |
||||
|
||||
#endif /* __MACH_DMA_H */ |
||||
@ -1,19 +0,0 @@ |
||||
/* arch/arm/mach-s5pc100/include/mach/entry-macro.S |
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com>
|
||||
* |
||||
* Based on mach-s3c6400/include/mach/entry-macro.S |
||||
* |
||||
* Low-level IRQ helper macros for the Samsung S5PC1XX series |
||||
* |
||||
* This file is licensed under the terms of the GNU General Public |
||||
* License version 2. This program is licensed "as is" without any |
||||
* warranty of any kind, whether express or implied. |
||||
*/ |
||||
|
||||
.macro get_irqnr_preamble, base, tmp |
||||
.endm |
||||
|
||||
.macro get_irqnr_and_base, irqnr, irqstat, base, tmp |
||||
.endm |
||||
@ -1,144 +0,0 @@ |
||||
/* arch/arm/mach-s5pc100/include/mach/gpio.h
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - GPIO lib support |
||||
* |
||||
* Base on mach-s3c6400/include/mach/gpio.h |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_GPIO_H |
||||
#define __ASM_ARCH_GPIO_H __FILE__ |
||||
|
||||
/* GPIO bank sizes */ |
||||
#define S5PC100_GPIO_A0_NR (8) |
||||
#define S5PC100_GPIO_A1_NR (5) |
||||
#define S5PC100_GPIO_B_NR (8) |
||||
#define S5PC100_GPIO_C_NR (5) |
||||
#define S5PC100_GPIO_D_NR (7) |
||||
#define S5PC100_GPIO_E0_NR (8) |
||||
#define S5PC100_GPIO_E1_NR (6) |
||||
#define S5PC100_GPIO_F0_NR (8) |
||||
#define S5PC100_GPIO_F1_NR (8) |
||||
#define S5PC100_GPIO_F2_NR (8) |
||||
#define S5PC100_GPIO_F3_NR (4) |
||||
#define S5PC100_GPIO_G0_NR (8) |
||||
#define S5PC100_GPIO_G1_NR (3) |
||||
#define S5PC100_GPIO_G2_NR (7) |
||||
#define S5PC100_GPIO_G3_NR (7) |
||||
#define S5PC100_GPIO_H0_NR (8) |
||||
#define S5PC100_GPIO_H1_NR (8) |
||||
#define S5PC100_GPIO_H2_NR (8) |
||||
#define S5PC100_GPIO_H3_NR (8) |
||||
#define S5PC100_GPIO_I_NR (8) |
||||
#define S5PC100_GPIO_J0_NR (8) |
||||
#define S5PC100_GPIO_J1_NR (5) |
||||
#define S5PC100_GPIO_J2_NR (8) |
||||
#define S5PC100_GPIO_J3_NR (8) |
||||
#define S5PC100_GPIO_J4_NR (4) |
||||
#define S5PC100_GPIO_K0_NR (8) |
||||
#define S5PC100_GPIO_K1_NR (6) |
||||
#define S5PC100_GPIO_K2_NR (8) |
||||
#define S5PC100_GPIO_K3_NR (8) |
||||
#define S5PC100_GPIO_L0_NR (8) |
||||
#define S5PC100_GPIO_L1_NR (8) |
||||
#define S5PC100_GPIO_L2_NR (8) |
||||
#define S5PC100_GPIO_L3_NR (8) |
||||
#define S5PC100_GPIO_L4_NR (8) |
||||
|
||||
/* GPIO bank numbes */ |
||||
|
||||
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra
|
||||
* space for debugging purposes so that any accidental |
||||
* change from one gpio bank to another can be caught. |
||||
*/ |
||||
|
||||
#define S5PC100_GPIO_NEXT(__gpio) \ |
||||
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) |
||||
|
||||
enum s5p_gpio_number { |
||||
S5PC100_GPIO_A0_START = 0, |
||||
S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0), |
||||
S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1), |
||||
S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B), |
||||
S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C), |
||||
S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D), |
||||
S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0), |
||||
S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1), |
||||
S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0), |
||||
S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1), |
||||
S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2), |
||||
S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3), |
||||
S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0), |
||||
S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1), |
||||
S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2), |
||||
S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3), |
||||
S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0), |
||||
S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1), |
||||
S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2), |
||||
S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3), |
||||
S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I), |
||||
S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0), |
||||
S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1), |
||||
S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2), |
||||
S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3), |
||||
S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4), |
||||
S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0), |
||||
S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1), |
||||
S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2), |
||||
S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3), |
||||
S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0), |
||||
S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1), |
||||
S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2), |
||||
S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3), |
||||
S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4), |
||||
}; |
||||
|
||||
/* S5PC100 GPIO number definitions. */ |
||||
#define S5PC100_GPA0(_nr) (S5PC100_GPIO_A0_START + (_nr)) |
||||
#define S5PC100_GPA1(_nr) (S5PC100_GPIO_A1_START + (_nr)) |
||||
#define S5PC100_GPB(_nr) (S5PC100_GPIO_B_START + (_nr)) |
||||
#define S5PC100_GPC(_nr) (S5PC100_GPIO_C_START + (_nr)) |
||||
#define S5PC100_GPD(_nr) (S5PC100_GPIO_D_START + (_nr)) |
||||
#define S5PC100_GPE0(_nr) (S5PC100_GPIO_E0_START + (_nr)) |
||||
#define S5PC100_GPE1(_nr) (S5PC100_GPIO_E1_START + (_nr)) |
||||
#define S5PC100_GPF0(_nr) (S5PC100_GPIO_F0_START + (_nr)) |
||||
#define S5PC100_GPF1(_nr) (S5PC100_GPIO_F1_START + (_nr)) |
||||
#define S5PC100_GPF2(_nr) (S5PC100_GPIO_F2_START + (_nr)) |
||||
#define S5PC100_GPF3(_nr) (S5PC100_GPIO_F3_START + (_nr)) |
||||
#define S5PC100_GPG0(_nr) (S5PC100_GPIO_G0_START + (_nr)) |
||||
#define S5PC100_GPG1(_nr) (S5PC100_GPIO_G1_START + (_nr)) |
||||
#define S5PC100_GPG2(_nr) (S5PC100_GPIO_G2_START + (_nr)) |
||||
#define S5PC100_GPG3(_nr) (S5PC100_GPIO_G3_START + (_nr)) |
||||
#define S5PC100_GPH0(_nr) (S5PC100_GPIO_H0_START + (_nr)) |
||||
#define S5PC100_GPH1(_nr) (S5PC100_GPIO_H1_START + (_nr)) |
||||
#define S5PC100_GPH2(_nr) (S5PC100_GPIO_H2_START + (_nr)) |
||||
#define S5PC100_GPH3(_nr) (S5PC100_GPIO_H3_START + (_nr)) |
||||
#define S5PC100_GPI(_nr) (S5PC100_GPIO_I_START + (_nr)) |
||||
#define S5PC100_GPJ0(_nr) (S5PC100_GPIO_J0_START + (_nr)) |
||||
#define S5PC100_GPJ1(_nr) (S5PC100_GPIO_J1_START + (_nr)) |
||||
#define S5PC100_GPJ2(_nr) (S5PC100_GPIO_J2_START + (_nr)) |
||||
#define S5PC100_GPJ3(_nr) (S5PC100_GPIO_J3_START + (_nr)) |
||||
#define S5PC100_GPJ4(_nr) (S5PC100_GPIO_J4_START + (_nr)) |
||||
#define S5PC100_GPK0(_nr) (S5PC100_GPIO_K0_START + (_nr)) |
||||
#define S5PC100_GPK1(_nr) (S5PC100_GPIO_K1_START + (_nr)) |
||||
#define S5PC100_GPK2(_nr) (S5PC100_GPIO_K2_START + (_nr)) |
||||
#define S5PC100_GPK3(_nr) (S5PC100_GPIO_K3_START + (_nr)) |
||||
#define S5PC100_GPL0(_nr) (S5PC100_GPIO_L0_START + (_nr)) |
||||
#define S5PC100_GPL1(_nr) (S5PC100_GPIO_L1_START + (_nr)) |
||||
#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) |
||||
#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) |
||||
#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) |
||||
|
||||
/* It used the end of the S5PC100 gpios */ |
||||
#define S3C_GPIO_END S5PC100_GPIO_END |
||||
|
||||
/* define the number of gpios we need to the one after the MP04() range */ |
||||
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) |
||||
|
||||
#endif /* __ASM_ARCH_GPIO_H */ |
||||
@ -1,14 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/include/mach/hardware.h
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - Hardware support |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_HARDWARE_H |
||||
#define __ASM_ARCH_HARDWARE_H __FILE__ |
||||
|
||||
/* currently nothing here, placeholder */ |
||||
|
||||
#endif /* __ASM_ARCH_HARDWARE_H */ |
||||
@ -1,115 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/include/mach/irqs.h
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - IRQ definitions |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_IRQS_H |
||||
#define __ASM_ARCH_IRQS_H __FILE__ |
||||
|
||||
#include <plat/irqs.h> |
||||
|
||||
/* VIC0: system, DMA, timer */ |
||||
#define IRQ_EINT16_31 S5P_IRQ_VIC0(16) |
||||
#define IRQ_BATF S5P_IRQ_VIC0(17) |
||||
#define IRQ_MDMA S5P_IRQ_VIC0(18) |
||||
#define IRQ_PDMA0 S5P_IRQ_VIC0(19) |
||||
#define IRQ_PDMA1 S5P_IRQ_VIC0(20) |
||||
#define IRQ_TIMER0_VIC S5P_IRQ_VIC0(21) |
||||
#define IRQ_TIMER1_VIC S5P_IRQ_VIC0(22) |
||||
#define IRQ_TIMER2_VIC S5P_IRQ_VIC0(23) |
||||
#define IRQ_TIMER3_VIC S5P_IRQ_VIC0(24) |
||||
#define IRQ_TIMER4_VIC S5P_IRQ_VIC0(25) |
||||
#define IRQ_SYSTIMER S5P_IRQ_VIC0(26) |
||||
#define IRQ_WDT S5P_IRQ_VIC0(27) |
||||
#define IRQ_RTC_ALARM S5P_IRQ_VIC0(28) |
||||
#define IRQ_RTC_TIC S5P_IRQ_VIC0(29) |
||||
#define IRQ_GPIOINT S5P_IRQ_VIC0(30) |
||||
|
||||
/* VIC1: ARM, power, memory, connectivity */ |
||||
#define IRQ_PMU S5P_IRQ_VIC1(0) |
||||
#define IRQ_CORTEX1 S5P_IRQ_VIC1(1) |
||||
#define IRQ_CORTEX2 S5P_IRQ_VIC1(2) |
||||
#define IRQ_CORTEX3 S5P_IRQ_VIC1(3) |
||||
#define IRQ_CORTEX4 S5P_IRQ_VIC1(4) |
||||
#define IRQ_IEMAPC S5P_IRQ_VIC1(5) |
||||
#define IRQ_IEMIEC S5P_IRQ_VIC1(6) |
||||
#define IRQ_ONENAND S5P_IRQ_VIC1(7) |
||||
#define IRQ_NFC S5P_IRQ_VIC1(8) |
||||
#define IRQ_CFCON S5P_IRQ_VIC1(9) |
||||
#define IRQ_UART0 S5P_IRQ_VIC1(10) |
||||
#define IRQ_UART1 S5P_IRQ_VIC1(11) |
||||
#define IRQ_UART2 S5P_IRQ_VIC1(12) |
||||
#define IRQ_UART3 S5P_IRQ_VIC1(13) |
||||
#define IRQ_IIC S5P_IRQ_VIC1(14) |
||||
#define IRQ_SPI0 S5P_IRQ_VIC1(15) |
||||
#define IRQ_SPI1 S5P_IRQ_VIC1(16) |
||||
#define IRQ_SPI2 S5P_IRQ_VIC1(17) |
||||
#define IRQ_IRDA S5P_IRQ_VIC1(18) |
||||
#define IRQ_IIC2 S5P_IRQ_VIC1(19) |
||||
#define IRQ_IIC3 S5P_IRQ_VIC1(20) |
||||
#define IRQ_HSIRX S5P_IRQ_VIC1(21) |
||||
#define IRQ_HSITX S5P_IRQ_VIC1(22) |
||||
#define IRQ_UHOST S5P_IRQ_VIC1(23) |
||||
#define IRQ_OTG S5P_IRQ_VIC1(24) |
||||
#define IRQ_MSM S5P_IRQ_VIC1(25) |
||||
#define IRQ_HSMMC0 S5P_IRQ_VIC1(26) |
||||
#define IRQ_HSMMC1 S5P_IRQ_VIC1(27) |
||||
#define IRQ_HSMMC2 S5P_IRQ_VIC1(28) |
||||
#define IRQ_MIPICSI S5P_IRQ_VIC1(29) |
||||
#define IRQ_MIPIDSI S5P_IRQ_VIC1(30) |
||||
|
||||
/* VIC2: multimedia, audio, security */ |
||||
#define IRQ_LCD0 S5P_IRQ_VIC2(0) |
||||
#define IRQ_LCD1 S5P_IRQ_VIC2(1) |
||||
#define IRQ_LCD2 S5P_IRQ_VIC2(2) |
||||
#define IRQ_LCD3 S5P_IRQ_VIC2(3) |
||||
#define IRQ_ROTATOR S5P_IRQ_VIC2(4) |
||||
#define IRQ_FIMC0 S5P_IRQ_VIC2(5) |
||||
#define IRQ_FIMC1 S5P_IRQ_VIC2(6) |
||||
#define IRQ_FIMC2 S5P_IRQ_VIC2(7) |
||||
#define IRQ_JPEG S5P_IRQ_VIC2(8) |
||||
#define IRQ_2D S5P_IRQ_VIC2(9) |
||||
#define IRQ_3D S5P_IRQ_VIC2(10) |
||||
#define IRQ_MIXER S5P_IRQ_VIC2(11) |
||||
#define IRQ_HDMI S5P_IRQ_VIC2(12) |
||||
#define IRQ_IIC1 S5P_IRQ_VIC2(13) |
||||
#define IRQ_MFC S5P_IRQ_VIC2(14) |
||||
#define IRQ_TVENC S5P_IRQ_VIC2(15) |
||||
#define IRQ_I2S0 S5P_IRQ_VIC2(16) |
||||
#define IRQ_I2S1 S5P_IRQ_VIC2(17) |
||||
#define IRQ_I2S2 S5P_IRQ_VIC2(18) |
||||
#define IRQ_AC97 S5P_IRQ_VIC2(19) |
||||
#define IRQ_PCM0 S5P_IRQ_VIC2(20) |
||||
#define IRQ_PCM1 S5P_IRQ_VIC2(21) |
||||
#define IRQ_SPDIF S5P_IRQ_VIC2(22) |
||||
#define IRQ_ADC S5P_IRQ_VIC2(23) |
||||
#define IRQ_PENDN S5P_IRQ_VIC2(24) |
||||
#define IRQ_TC IRQ_PENDN |
||||
#define IRQ_KEYPAD S5P_IRQ_VIC2(25) |
||||
#define IRQ_CG S5P_IRQ_VIC2(26) |
||||
#define IRQ_SEC S5P_IRQ_VIC2(27) |
||||
#define IRQ_SECRX S5P_IRQ_VIC2(28) |
||||
#define IRQ_SECTX S5P_IRQ_VIC2(29) |
||||
#define IRQ_SDMIRQ S5P_IRQ_VIC2(30) |
||||
#define IRQ_SDMFIQ S5P_IRQ_VIC2(31) |
||||
#define IRQ_VIC_END S5P_IRQ_VIC2(31) |
||||
|
||||
#define S5P_EINT_BASE1 (S5P_IRQ_VIC0(0)) |
||||
#define S5P_EINT_BASE2 (IRQ_VIC_END + 1) |
||||
|
||||
/* GPIO interrupt */ |
||||
#define S5P_GPIOINT_BASE (IRQ_EINT(31) + 1) |
||||
#define S5P_GPIOINT_GROUP_MAXNR 21 |
||||
|
||||
/* Set the default NR_IRQS */ |
||||
#define NR_IRQS (IRQ_EINT(31) + S5P_GPIOINT_COUNT + 1) |
||||
|
||||
/* Compatibility */ |
||||
#define IRQ_LCD_FIFO IRQ_LCD0 |
||||
#define IRQ_LCD_VSYNC IRQ_LCD1 |
||||
#define IRQ_LCD_SYSTEM IRQ_LCD2 |
||||
|
||||
#endif /* __ASM_ARCH_IRQS_H */ |
||||
@ -1,137 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/include/mach/map.h
|
||||
* |
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - Memory map definitions |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_MAP_H |
||||
#define __ASM_ARCH_MAP_H __FILE__ |
||||
|
||||
#include <plat/map-base.h> |
||||
#include <plat/map-s5p.h> |
||||
|
||||
#define S5PC100_PA_SDRAM 0x20000000 |
||||
|
||||
#define S5PC100_PA_ONENAND 0xE7100000 |
||||
#define S5PC100_PA_ONENAND_BUF 0xB0000000 |
||||
|
||||
#define S5PC100_PA_CHIPID 0xE0000000 |
||||
|
||||
#define S5PC100_PA_SYSCON 0xE0100000 |
||||
|
||||
#define S5PC100_PA_OTHERS 0xE0200000 |
||||
|
||||
#define S5PC100_PA_GPIO 0xE0300000 |
||||
|
||||
#define S5PC100_PA_VIC0 0xE4000000 |
||||
#define S5PC100_PA_VIC1 0xE4100000 |
||||
#define S5PC100_PA_VIC2 0xE4200000 |
||||
|
||||
#define S5PC100_PA_SROMC 0xE7000000 |
||||
|
||||
#define S5PC100_PA_CFCON 0xE7800000 |
||||
|
||||
#define S5PC100_PA_MDMA 0xE8100000 |
||||
#define S5PC100_PA_PDMA0 0xE9000000 |
||||
#define S5PC100_PA_PDMA1 0xE9200000 |
||||
|
||||
#define S5PC100_PA_TIMER 0xEA000000 |
||||
#define S5PC100_PA_SYSTIMER 0xEA100000 |
||||
#define S5PC100_PA_WATCHDOG 0xEA200000 |
||||
#define S5PC100_PA_RTC 0xEA300000 |
||||
|
||||
#define S5PC100_PA_UART 0xEC000000 |
||||
|
||||
#define S5PC100_PA_IIC0 0xEC100000 |
||||
#define S5PC100_PA_IIC1 0xEC200000 |
||||
|
||||
#define S5PC100_PA_SPI0 0xEC300000 |
||||
#define S5PC100_PA_SPI1 0xEC400000 |
||||
#define S5PC100_PA_SPI2 0xEC500000 |
||||
|
||||
#define S5PC100_PA_USB_HSOTG 0xED200000 |
||||
#define S5PC100_PA_USB_HSPHY 0xED300000 |
||||
|
||||
#define S5PC100_PA_HSMMC(x) (0xED800000 + ((x) * 0x100000)) |
||||
|
||||
#define S5PC100_PA_FB 0xEE000000 |
||||
|
||||
#define S5PC100_PA_FIMC0 0xEE200000 |
||||
#define S5PC100_PA_FIMC1 0xEE300000 |
||||
#define S5PC100_PA_FIMC2 0xEE400000 |
||||
|
||||
#define S5PC100_PA_I2S0 0xF2000000 |
||||
#define S5PC100_PA_I2S1 0xF2100000 |
||||
#define S5PC100_PA_I2S2 0xF2200000 |
||||
|
||||
#define S5PC100_PA_AC97 0xF2300000 |
||||
|
||||
#define S5PC100_PA_PCM0 0xF2400000 |
||||
#define S5PC100_PA_PCM1 0xF2500000 |
||||
|
||||
#define S5PC100_PA_SPDIF 0xF2600000 |
||||
|
||||
#define S5PC100_PA_TSADC 0xF3000000 |
||||
|
||||
#define S5PC100_PA_KEYPAD 0xF3100000 |
||||
|
||||
/* Compatibiltiy Defines */ |
||||
|
||||
#define S3C_PA_FB S5PC100_PA_FB |
||||
#define S3C_PA_HSMMC0 S5PC100_PA_HSMMC(0) |
||||
#define S3C_PA_HSMMC1 S5PC100_PA_HSMMC(1) |
||||
#define S3C_PA_HSMMC2 S5PC100_PA_HSMMC(2) |
||||
#define S3C_PA_IIC S5PC100_PA_IIC0 |
||||
#define S3C_PA_IIC1 S5PC100_PA_IIC1 |
||||
#define S3C_PA_KEYPAD S5PC100_PA_KEYPAD |
||||
#define S3C_PA_ONENAND S5PC100_PA_ONENAND |
||||
#define S3C_PA_ONENAND_BUF S5PC100_PA_ONENAND_BUF |
||||
#define S3C_PA_RTC S5PC100_PA_RTC |
||||
#define S3C_PA_TSADC S5PC100_PA_TSADC |
||||
#define S3C_PA_USB_HSOTG S5PC100_PA_USB_HSOTG |
||||
#define S3C_PA_USB_HSPHY S5PC100_PA_USB_HSPHY |
||||
#define S3C_PA_WDT S5PC100_PA_WATCHDOG |
||||
#define S3C_PA_SPI0 S5PC100_PA_SPI0 |
||||
#define S3C_PA_SPI1 S5PC100_PA_SPI1 |
||||
#define S3C_PA_SPI2 S5PC100_PA_SPI2 |
||||
|
||||
#define S5P_PA_CHIPID S5PC100_PA_CHIPID |
||||
#define S5P_PA_FIMC0 S5PC100_PA_FIMC0 |
||||
#define S5P_PA_FIMC1 S5PC100_PA_FIMC1 |
||||
#define S5P_PA_FIMC2 S5PC100_PA_FIMC2 |
||||
#define S5P_PA_SDRAM S5PC100_PA_SDRAM |
||||
#define S5P_PA_SROMC S5PC100_PA_SROMC |
||||
#define S5P_PA_SYSCON S5PC100_PA_SYSCON |
||||
#define S5P_PA_TIMER S5PC100_PA_TIMER |
||||
|
||||
#define SAMSUNG_PA_ADC S5PC100_PA_TSADC |
||||
#define SAMSUNG_PA_CFCON S5PC100_PA_CFCON |
||||
#define SAMSUNG_PA_KEYPAD S5PC100_PA_KEYPAD |
||||
#define SAMSUNG_PA_TIMER S5PC100_PA_TIMER |
||||
|
||||
#define S5PC100_VA_OTHERS (S3C_VA_SYS + 0x10000) |
||||
|
||||
#define S3C_SZ_ONENAND_BUF (SZ_256M - SZ_32M) |
||||
|
||||
/* UART */ |
||||
|
||||
#define S3C_PA_UART S5PC100_PA_UART |
||||
|
||||
#define S5P_PA_UART(x) (S3C_PA_UART + ((x) * S3C_UART_OFFSET)) |
||||
#define S5P_PA_UART0 S5P_PA_UART(0) |
||||
#define S5P_PA_UART1 S5P_PA_UART(1) |
||||
#define S5P_PA_UART2 S5P_PA_UART(2) |
||||
#define S5P_PA_UART3 S5P_PA_UART(3) |
||||
|
||||
#define S5P_SZ_UART SZ_256 |
||||
|
||||
#endif /* __ASM_ARCH_MAP_H */ |
||||
@ -1,80 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
|
||||
* |
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* S5PC100 - Clock register definitions |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_REGS_CLOCK_H |
||||
#define __ASM_ARCH_REGS_CLOCK_H __FILE__ |
||||
|
||||
#include <mach/map.h> |
||||
|
||||
#define S5P_CLKREG(x) (S3C_VA_SYS + (x)) |
||||
|
||||
#define S5PC100_REG_OTHERS(x) (S5PC100_VA_OTHERS + (x)) |
||||
|
||||
#define S5P_APLL_LOCK S5P_CLKREG(0x00) |
||||
#define S5P_MPLL_LOCK S5P_CLKREG(0x04) |
||||
#define S5P_EPLL_LOCK S5P_CLKREG(0x08) |
||||
#define S5P_HPLL_LOCK S5P_CLKREG(0x0C) |
||||
|
||||
#define S5P_APLL_CON S5P_CLKREG(0x100) |
||||
#define S5P_MPLL_CON S5P_CLKREG(0x104) |
||||
#define S5P_EPLL_CON S5P_CLKREG(0x108) |
||||
#define S5P_HPLL_CON S5P_CLKREG(0x10C) |
||||
|
||||
#define S5P_CLK_SRC0 S5P_CLKREG(0x200) |
||||
#define S5P_CLK_SRC1 S5P_CLKREG(0x204) |
||||
#define S5P_CLK_SRC2 S5P_CLKREG(0x208) |
||||
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C) |
||||
|
||||
#define S5P_CLK_DIV0 S5P_CLKREG(0x300) |
||||
#define S5P_CLK_DIV1 S5P_CLKREG(0x304) |
||||
#define S5P_CLK_DIV2 S5P_CLKREG(0x308) |
||||
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C) |
||||
#define S5P_CLK_DIV4 S5P_CLKREG(0x310) |
||||
|
||||
#define S5P_CLK_OUT S5P_CLKREG(0x400) |
||||
|
||||
#define S5P_CLKGATE_D00 S5P_CLKREG(0x500) |
||||
#define S5P_CLKGATE_D01 S5P_CLKREG(0x504) |
||||
#define S5P_CLKGATE_D02 S5P_CLKREG(0x508) |
||||
|
||||
#define S5P_CLKGATE_D10 S5P_CLKREG(0x520) |
||||
#define S5P_CLKGATE_D11 S5P_CLKREG(0x524) |
||||
#define S5P_CLKGATE_D12 S5P_CLKREG(0x528) |
||||
#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C) |
||||
#define S5P_CLKGATE_D14 S5P_CLKREG(0x530) |
||||
#define S5P_CLKGATE_D15 S5P_CLKREG(0x534) |
||||
|
||||
#define S5P_CLKGATE_D20 S5P_CLKREG(0x540) |
||||
|
||||
#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560) |
||||
#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564) |
||||
|
||||
/* CLKDIV0 */ |
||||
#define S5P_CLKDIV0_D0_MASK (0x7<<8) |
||||
#define S5P_CLKDIV0_D0_SHIFT (8) |
||||
#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12) |
||||
#define S5P_CLKDIV0_PCLKD0_SHIFT (12) |
||||
|
||||
/* CLKDIV1 */ |
||||
#define S5P_CLKDIV1_D1_MASK (0x7<<12) |
||||
#define S5P_CLKDIV1_D1_SHIFT (12) |
||||
#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16) |
||||
#define S5P_CLKDIV1_PCLKD1_SHIFT (16) |
||||
|
||||
#define S5PC100_SWRESET S5PC100_REG_OTHERS(0x000) |
||||
#define S5PC100_MEM_SYS_CFG S5PC100_REG_OTHERS(0x200) |
||||
|
||||
#define S5PC100_SWRESET_RESETVAL 0xc100 |
||||
|
||||
#define MEM_SYS_CFG_EBI_FIX_PRI_CFCON 0x30 |
||||
|
||||
#endif /* __ASM_ARCH_REGS_CLOCK_H */ |
||||
@ -1,38 +0,0 @@ |
||||
/* linux/arch/arm/plat-s5pc100/include/plat/regs-gpio.h
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - GPIO register definitions |
||||
*/ |
||||
|
||||
#ifndef __ASM_MACH_S5PC100_REGS_GPIO_H |
||||
#define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__ |
||||
|
||||
#include <mach/map.h> |
||||
|
||||
#define S5PC100EINT30CON (S5P_VA_GPIO + 0xE00) |
||||
#define S5P_EINT_CON(x) (S5PC100EINT30CON + ((x) * 0x4)) |
||||
|
||||
#define S5PC100EINT30FLTCON0 (S5P_VA_GPIO + 0xE80) |
||||
#define S5P_EINT_FLTCON(x) (S5PC100EINT30FLTCON0 + ((x) * 0x4)) |
||||
|
||||
#define S5PC100EINT30MASK (S5P_VA_GPIO + 0xF00) |
||||
#define S5P_EINT_MASK(x) (S5PC100EINT30MASK + ((x) * 0x4)) |
||||
|
||||
#define S5PC100EINT30PEND (S5P_VA_GPIO + 0xF40) |
||||
#define S5P_EINT_PEND(x) (S5PC100EINT30PEND + ((x) * 0x4)) |
||||
|
||||
#define EINT_REG_NR(x) (EINT_OFFSET(x) >> 3) |
||||
|
||||
#define eint_irq_to_bit(irq) (1 << (EINT_OFFSET(irq) & 0x7)) |
||||
|
||||
#define EINT_MODE S3C_GPIO_SFN(0x2) |
||||
|
||||
#define EINT_GPIO_0(x) S5PC100_GPH0(x) |
||||
#define EINT_GPIO_1(x) S5PC100_GPH1(x) |
||||
#define EINT_GPIO_2(x) S5PC100_GPH2(x) |
||||
#define EINT_GPIO_3(x) S5PC100_GPH3(x) |
||||
|
||||
#endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */ |
||||
|
||||
@ -1,18 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/include/mach/regs-irq.h
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* S5PC100 - IRQ register definitions |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef __ASM_ARCH_REGS_IRQ_H |
||||
#define __ASM_ARCH_REGS_IRQ_H __FILE__ |
||||
|
||||
#include <mach/map.h> |
||||
|
||||
#endif /* __ASM_ARCH_REGS_IRQ_H */ |
||||
@ -1,264 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/mach-smdkc100.c
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Author: Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/types.h> |
||||
#include <linux/interrupt.h> |
||||
#include <linux/list.h> |
||||
#include <linux/timer.h> |
||||
#include <linux/init.h> |
||||
#include <linux/serial_core.h> |
||||
#include <linux/serial_s3c.h> |
||||
#include <linux/platform_device.h> |
||||
#include <linux/io.h> |
||||
#include <linux/gpio.h> |
||||
#include <linux/i2c.h> |
||||
#include <linux/fb.h> |
||||
#include <linux/delay.h> |
||||
#include <linux/input.h> |
||||
#include <linux/pwm_backlight.h> |
||||
|
||||
#include <asm/mach/arch.h> |
||||
#include <asm/mach/map.h> |
||||
|
||||
#include <mach/map.h> |
||||
#include <mach/regs-gpio.h> |
||||
|
||||
#include <video/platform_lcd.h> |
||||
#include <video/samsung_fimd.h> |
||||
|
||||
#include <asm/irq.h> |
||||
#include <asm/mach-types.h> |
||||
|
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
#include <plat/clock.h> |
||||
#include <plat/devs.h> |
||||
#include <plat/cpu.h> |
||||
#include <plat/fb.h> |
||||
#include <linux/platform_data/i2c-s3c2410.h> |
||||
#include <linux/platform_data/ata-samsung_cf.h> |
||||
#include <plat/adc.h> |
||||
#include <plat/keypad.h> |
||||
#include <linux/platform_data/touchscreen-s3c2410.h> |
||||
#include <linux/platform_data/asoc-s3c.h> |
||||
#include <plat/backlight.h> |
||||
#include <plat/samsung-time.h> |
||||
|
||||
#include "common.h" |
||||
|
||||
/* Following are default values for UCON, ULCON and UFCON UART registers */ |
||||
#define SMDKC100_UCON_DEFAULT (S3C2410_UCON_TXILEVEL | \ |
||||
S3C2410_UCON_RXILEVEL | \
|
||||
S3C2410_UCON_TXIRQMODE | \
|
||||
S3C2410_UCON_RXIRQMODE | \
|
||||
S3C2410_UCON_RXFIFO_TOI | \
|
||||
S3C2443_UCON_RXERR_IRQEN) |
||||
|
||||
#define SMDKC100_ULCON_DEFAULT S3C2410_LCON_CS8 |
||||
|
||||
#define SMDKC100_UFCON_DEFAULT (S3C2410_UFCON_FIFOMODE | \ |
||||
S3C2440_UFCON_RXTRIG8 | \
|
||||
S3C2440_UFCON_TXTRIG16) |
||||
|
||||
static struct s3c2410_uartcfg smdkc100_uartcfgs[] __initdata = { |
||||
[0] = { |
||||
.hwport = 0, |
||||
.flags = 0, |
||||
.ucon = SMDKC100_UCON_DEFAULT, |
||||
.ulcon = SMDKC100_ULCON_DEFAULT, |
||||
.ufcon = SMDKC100_UFCON_DEFAULT, |
||||
}, |
||||
[1] = { |
||||
.hwport = 1, |
||||
.flags = 0, |
||||
.ucon = SMDKC100_UCON_DEFAULT, |
||||
.ulcon = SMDKC100_ULCON_DEFAULT, |
||||
.ufcon = SMDKC100_UFCON_DEFAULT, |
||||
}, |
||||
[2] = { |
||||
.hwport = 2, |
||||
.flags = 0, |
||||
.ucon = SMDKC100_UCON_DEFAULT, |
||||
.ulcon = SMDKC100_ULCON_DEFAULT, |
||||
.ufcon = SMDKC100_UFCON_DEFAULT, |
||||
}, |
||||
[3] = { |
||||
.hwport = 3, |
||||
.flags = 0, |
||||
.ucon = SMDKC100_UCON_DEFAULT, |
||||
.ulcon = SMDKC100_ULCON_DEFAULT, |
||||
.ufcon = SMDKC100_UFCON_DEFAULT, |
||||
}, |
||||
}; |
||||
|
||||
/* I2C0 */ |
||||
static struct i2c_board_info i2c_devs0[] __initdata = { |
||||
{I2C_BOARD_INFO("wm8580", 0x1b),}, |
||||
}; |
||||
|
||||
/* I2C1 */ |
||||
static struct i2c_board_info i2c_devs1[] __initdata = { |
||||
}; |
||||
|
||||
/* LCD power controller */ |
||||
static void smdkc100_lcd_power_set(struct plat_lcd_data *pd, |
||||
unsigned int power) |
||||
{ |
||||
if (power) { |
||||
/* module reset */ |
||||
gpio_direction_output(S5PC100_GPH0(6), 1); |
||||
mdelay(100); |
||||
gpio_direction_output(S5PC100_GPH0(6), 0); |
||||
mdelay(10); |
||||
gpio_direction_output(S5PC100_GPH0(6), 1); |
||||
mdelay(10); |
||||
} |
||||
} |
||||
|
||||
static struct plat_lcd_data smdkc100_lcd_power_data = { |
||||
.set_power = smdkc100_lcd_power_set, |
||||
}; |
||||
|
||||
static struct platform_device smdkc100_lcd_powerdev = { |
||||
.name = "platform-lcd", |
||||
.dev.parent = &s3c_device_fb.dev, |
||||
.dev.platform_data = &smdkc100_lcd_power_data, |
||||
}; |
||||
|
||||
/* Frame Buffer */ |
||||
static struct s3c_fb_pd_win smdkc100_fb_win0 = { |
||||
.max_bpp = 32, |
||||
.default_bpp = 16, |
||||
.xres = 800, |
||||
.yres = 480, |
||||
}; |
||||
|
||||
static struct fb_videomode smdkc100_lcd_timing = { |
||||
.left_margin = 8, |
||||
.right_margin = 13, |
||||
.upper_margin = 7, |
||||
.lower_margin = 5, |
||||
.hsync_len = 3, |
||||
.vsync_len = 1, |
||||
.xres = 800, |
||||
.yres = 480, |
||||
.refresh = 80, |
||||
}; |
||||
|
||||
static struct s3c_fb_platdata smdkc100_lcd_pdata __initdata = { |
||||
.win[0] = &smdkc100_fb_win0, |
||||
.vtiming = &smdkc100_lcd_timing, |
||||
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB, |
||||
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC, |
||||
.setup_gpio = s5pc100_fb_gpio_setup_24bpp, |
||||
}; |
||||
|
||||
static struct s3c_ide_platdata smdkc100_ide_pdata __initdata = { |
||||
.setup_gpio = s5pc100_ide_setup_gpio, |
||||
}; |
||||
|
||||
static uint32_t smdkc100_keymap[] __initdata = { |
||||
/* KEY(row, col, keycode) */ |
||||
KEY(0, 3, KEY_1), KEY(0, 4, KEY_2), KEY(0, 5, KEY_3), |
||||
KEY(0, 6, KEY_4), KEY(0, 7, KEY_5), |
||||
KEY(1, 3, KEY_A), KEY(1, 4, KEY_B), KEY(1, 5, KEY_C), |
||||
KEY(1, 6, KEY_D), KEY(1, 7, KEY_E) |
||||
}; |
||||
|
||||
static struct matrix_keymap_data smdkc100_keymap_data __initdata = { |
||||
.keymap = smdkc100_keymap, |
||||
.keymap_size = ARRAY_SIZE(smdkc100_keymap), |
||||
}; |
||||
|
||||
static struct samsung_keypad_platdata smdkc100_keypad_data __initdata = { |
||||
.keymap_data = &smdkc100_keymap_data, |
||||
.rows = 2, |
||||
.cols = 8, |
||||
}; |
||||
|
||||
static struct platform_device *smdkc100_devices[] __initdata = { |
||||
&s3c_device_adc, |
||||
&s3c_device_cfcon, |
||||
&s3c_device_i2c0, |
||||
&s3c_device_i2c1, |
||||
&s3c_device_fb, |
||||
&s3c_device_hsmmc0, |
||||
&s3c_device_hsmmc1, |
||||
&s3c_device_hsmmc2, |
||||
&samsung_device_pwm, |
||||
&s3c_device_ts, |
||||
&s3c_device_wdt, |
||||
&smdkc100_lcd_powerdev, |
||||
&s5pc100_device_iis0, |
||||
&samsung_device_keypad, |
||||
&s5pc100_device_ac97, |
||||
&s3c_device_rtc, |
||||
&s5p_device_fimc0, |
||||
&s5p_device_fimc1, |
||||
&s5p_device_fimc2, |
||||
&s5pc100_device_spdif, |
||||
}; |
||||
|
||||
/* LCD Backlight data */ |
||||
static struct samsung_bl_gpio_info smdkc100_bl_gpio_info = { |
||||
.no = S5PC100_GPD(0), |
||||
.func = S3C_GPIO_SFN(2), |
||||
}; |
||||
|
||||
static struct platform_pwm_backlight_data smdkc100_bl_data = { |
||||
.pwm_id = 0, |
||||
.enable_gpio = -1, |
||||
}; |
||||
|
||||
static void __init smdkc100_map_io(void) |
||||
{ |
||||
s5pc100_init_io(NULL, 0); |
||||
s3c24xx_init_clocks(12000000); |
||||
s3c24xx_init_uarts(smdkc100_uartcfgs, ARRAY_SIZE(smdkc100_uartcfgs)); |
||||
samsung_set_timer_source(SAMSUNG_PWM3, SAMSUNG_PWM4); |
||||
} |
||||
|
||||
static void __init smdkc100_machine_init(void) |
||||
{ |
||||
s3c24xx_ts_set_platdata(NULL); |
||||
|
||||
/* I2C */ |
||||
s3c_i2c0_set_platdata(NULL); |
||||
s3c_i2c1_set_platdata(NULL); |
||||
i2c_register_board_info(0, i2c_devs0, ARRAY_SIZE(i2c_devs0)); |
||||
i2c_register_board_info(1, i2c_devs1, ARRAY_SIZE(i2c_devs1)); |
||||
|
||||
s3c_fb_set_platdata(&smdkc100_lcd_pdata); |
||||
s3c_ide_set_platdata(&smdkc100_ide_pdata); |
||||
|
||||
samsung_keypad_set_platdata(&smdkc100_keypad_data); |
||||
|
||||
s5pc100_spdif_setup_gpio(S5PC100_SPDIF_GPD); |
||||
|
||||
/* LCD init */ |
||||
gpio_request(S5PC100_GPH0(6), "GPH0"); |
||||
smdkc100_lcd_power_set(&smdkc100_lcd_power_data, 0); |
||||
|
||||
platform_add_devices(smdkc100_devices, ARRAY_SIZE(smdkc100_devices)); |
||||
|
||||
samsung_bl_set(&smdkc100_bl_gpio_info, &smdkc100_bl_data); |
||||
} |
||||
|
||||
MACHINE_START(SMDKC100, "SMDKC100") |
||||
/* Maintainer: Byungho Min <bhmin@samsung.com> */ |
||||
.atag_offset = 0x100, |
||||
.init_irq = s5pc100_init_irq, |
||||
.map_io = smdkc100_map_io, |
||||
.init_machine = smdkc100_machine_init, |
||||
.init_time = samsung_timer_init, |
||||
.restart = s5pc100_restart, |
||||
MACHINE_END |
||||
@ -1,35 +0,0 @@ |
||||
/*
|
||||
* linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c |
||||
* |
||||
* Copyright 2009 Samsung Electronics |
||||
* |
||||
* Base S5PC100 setup information for 24bpp LCD framebuffer |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/types.h> |
||||
#include <linux/fb.h> |
||||
#include <linux/gpio.h> |
||||
|
||||
#include <mach/map.h> |
||||
#include <plat/fb.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
#define DISR_OFFSET 0x7008 |
||||
|
||||
static void s5pc100_fb_setgpios(unsigned int base, unsigned int nr) |
||||
{ |
||||
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(2)); |
||||
} |
||||
|
||||
void s5pc100_fb_gpio_setup_24bpp(void) |
||||
{ |
||||
s5pc100_fb_setgpios(S5PC100_GPF0(0), 8); |
||||
s5pc100_fb_setgpios(S5PC100_GPF1(0), 8); |
||||
s5pc100_fb_setgpios(S5PC100_GPF2(0), 8); |
||||
s5pc100_fb_setgpios(S5PC100_GPF3(0), 4); |
||||
} |
||||
@ -1,28 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/setup-i2c0.c
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* Base S5PC100 I2C bus 0 gpio configuration |
||||
* |
||||
* Based on plat-s3c64xx/setup-i2c0.c |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/types.h> |
||||
|
||||
struct platform_device; /* don't need the contents */ |
||||
|
||||
#include <linux/gpio.h> |
||||
#include <linux/platform_data/i2c-s3c2410.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
void s3c_i2c0_cfg_gpio(struct platform_device *dev) |
||||
{ |
||||
s3c_gpio_cfgall_range(S5PC100_GPD(3), 2, |
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
||||
} |
||||
@ -1,28 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/setup-i2c1.c
|
||||
* |
||||
* Copyright 2009 Samsung Electronics Co. |
||||
* Byungho Min <bhmin@samsung.com> |
||||
* |
||||
* Base S5PC100 I2C bus 1 gpio configuration |
||||
* |
||||
* Based on plat-s3c64xx/setup-i2c1.c |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/types.h> |
||||
|
||||
struct platform_device; /* don't need the contents */ |
||||
|
||||
#include <linux/gpio.h> |
||||
#include <linux/platform_data/i2c-s3c2410.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
void s3c_i2c1_cfg_gpio(struct platform_device *dev) |
||||
{ |
||||
s3c_gpio_cfgall_range(S5PC100_GPD(5), 2, |
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
||||
} |
||||
@ -1,57 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/setup-ide.c
|
||||
* |
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com
|
||||
* |
||||
* S5PC100 setup information for IDE |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/gpio.h> |
||||
#include <linux/io.h> |
||||
|
||||
#include <mach/regs-clock.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
static void s5pc100_ide_cfg_gpios(unsigned int base, unsigned int nr) |
||||
{ |
||||
s3c_gpio_cfgrange_nopull(base, nr, S3C_GPIO_SFN(4)); |
||||
|
||||
for (; nr > 0; nr--, base++) |
||||
s5p_gpio_set_drvstr(base, S5P_GPIO_DRVSTR_LV4); |
||||
} |
||||
|
||||
void s5pc100_ide_setup_gpio(void) |
||||
{ |
||||
u32 reg; |
||||
|
||||
/* Independent CF interface, CF chip select configuration */ |
||||
reg = readl(S5PC100_MEM_SYS_CFG) & (~0x3f); |
||||
writel(reg | MEM_SYS_CFG_EBI_FIX_PRI_CFCON, S5PC100_MEM_SYS_CFG); |
||||
|
||||
/* CF_Add[0 - 2], CF_IORDY, CF_INTRQ, CF_DMARQ, CF_DMARST, CF_DMACK */ |
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ0(0), 8); |
||||
|
||||
/*CF_Data[0 - 7] */ |
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ2(0), 8); |
||||
|
||||
/* CF_Data[8 - 15] */ |
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ3(0), 8); |
||||
|
||||
/* CF_CS0, CF_CS1, CF_IORD, CF_IOWR */ |
||||
s5pc100_ide_cfg_gpios(S5PC100_GPJ4(0), 4); |
||||
|
||||
/* EBI_OE, EBI_WE */ |
||||
s3c_gpio_cfgpin_range(S5PC100_GPK0(6), 2, S3C_GPIO_SFN(0)); |
||||
|
||||
/* CF_OE, CF_WE */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPK1(6), 8, S3C_GPIO_SFN(2)); |
||||
|
||||
/* CF_CD */ |
||||
s3c_gpio_cfgpin(S5PC100_GPK3(5), S3C_GPIO_SFN(2)); |
||||
s3c_gpio_setpull(S5PC100_GPK3(5), S3C_GPIO_PULL_NONE); |
||||
} |
||||
@ -1,23 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/setup-keypad.c
|
||||
* |
||||
* Copyright (c) 2010 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* GPIO configuration for S5PC100 KeyPad device |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/gpio.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
void samsung_keypad_cfg_gpio(unsigned int rows, unsigned int cols) |
||||
{ |
||||
/* Set all the necessary GPH3 pins to special-function 3: KP_ROW[x] */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPH3(0), rows, S3C_GPIO_SFN(3)); |
||||
|
||||
/* Set all the necessary GPH2 pins to special-function 3: KP_COL[x] */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPH2(0), cols, S3C_GPIO_SFN(3)); |
||||
} |
||||
@ -1,70 +0,0 @@ |
||||
/* linux/arch/arm/plat-s5pc100/setup-sdhci-gpio.c
|
||||
* |
||||
* Copyright 2009 Samsung Eletronics |
||||
* |
||||
* S5PC100 - Helper functions for setting up SDHCI device(s) GPIO (HSMMC) |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/types.h> |
||||
#include <linux/interrupt.h> |
||||
#include <linux/platform_device.h> |
||||
#include <linux/io.h> |
||||
#include <linux/gpio.h> |
||||
#include <linux/mmc/host.h> |
||||
#include <linux/mmc/card.h> |
||||
|
||||
#include <plat/gpio-cfg.h> |
||||
#include <plat/sdhci.h> |
||||
|
||||
void s5pc100_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) |
||||
{ |
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; |
||||
unsigned int num; |
||||
|
||||
num = width; |
||||
/* In case of 8 width, we should decrease the 2 */ |
||||
if (width == 8) |
||||
num = width - 2; |
||||
|
||||
/* Set all the necessary GPG0/GPG1 pins to special-function 0 */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG0(0), 2 + num, S3C_GPIO_SFN(2)); |
||||
|
||||
if (width == 8) |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG1(0), 2, S3C_GPIO_SFN(2)); |
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { |
||||
s3c_gpio_setpull(S5PC100_GPG1(2), S3C_GPIO_PULL_UP); |
||||
s3c_gpio_cfgpin(S5PC100_GPG1(2), S3C_GPIO_SFN(2)); |
||||
} |
||||
} |
||||
|
||||
void s5pc100_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) |
||||
{ |
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; |
||||
|
||||
/* Set all the necessary GPG2 pins to special-function 2 */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG2(0), 2 + width, S3C_GPIO_SFN(2)); |
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { |
||||
s3c_gpio_setpull(S5PC100_GPG2(6), S3C_GPIO_PULL_UP); |
||||
s3c_gpio_cfgpin(S5PC100_GPG2(6), S3C_GPIO_SFN(2)); |
||||
} |
||||
} |
||||
|
||||
void s5pc100_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) |
||||
{ |
||||
struct s3c_sdhci_platdata *pdata = dev->dev.platform_data; |
||||
|
||||
/* Set all the necessary GPG3 pins to special-function 2 */ |
||||
s3c_gpio_cfgrange_nopull(S5PC100_GPG3(0), 2 + width, S3C_GPIO_SFN(2)); |
||||
|
||||
if (pdata->cd_type == S3C_SDHCI_CD_INTERNAL) { |
||||
s3c_gpio_setpull(S5PC100_GPG3(6), S3C_GPIO_PULL_UP); |
||||
s3c_gpio_cfgpin(S5PC100_GPG3(6), S3C_GPIO_SFN(2)); |
||||
} |
||||
} |
||||
@ -1,41 +0,0 @@ |
||||
/* linux/arch/arm/mach-s5pc100/setup-spi.c
|
||||
* |
||||
* Copyright (C) 2011 Samsung Electronics Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/gpio.h> |
||||
#include <plat/gpio-cfg.h> |
||||
|
||||
#ifdef CONFIG_S3C64XX_DEV_SPI0 |
||||
int s3c64xx_spi0_cfg_gpio(void) |
||||
{ |
||||
s3c_gpio_cfgall_range(S5PC100_GPB(0), 3, |
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_S3C64XX_DEV_SPI1 |
||||
int s3c64xx_spi1_cfg_gpio(void) |
||||
{ |
||||
s3c_gpio_cfgall_range(S5PC100_GPB(4), 3, |
||||
S3C_GPIO_SFN(2), S3C_GPIO_PULL_UP); |
||||
return 0; |
||||
} |
||||
#endif |
||||
|
||||
#ifdef CONFIG_S3C64XX_DEV_SPI2 |
||||
int s3c64xx_spi2_cfg_gpio(void) |
||||
{ |
||||
s3c_gpio_cfgpin(S5PC100_GPG3(0), S3C_GPIO_SFN(3)); |
||||
s3c_gpio_setpull(S5PC100_GPG3(0), S3C_GPIO_PULL_UP); |
||||
s3c_gpio_cfgall_range(S5PC100_GPB(2), 2, |
||||
S3C_GPIO_SFN(3), S3C_GPIO_PULL_UP); |
||||
return 0; |
||||
} |
||||
#endif |
||||
Loading…
Reference in new issue