* 'for-linus' of git://codeaurora.org/quic/kernel/davidb/linux-msm: (35 commits) mmc: msm_sdcc: Check for only DATA_END interrupt to end a request mmc: msm_sdcc: Fix bug in PIO mode when data size is not word aligned mmc: msm_sdcc: Reset SDCC in case of data transfer errors mmc: msm_sdcc: Add prog done interrupt support mmc: msm_sdcc: Fix possible circular locking dependency warning MSM: Add USB support for MSM7x30 MSM: Add USB suport for QSD8x50 msm: initial framebuffer support msm: add handling for clocks tagged as CLK_MINMAX msm: trout: change name of pmdh_clk to mddi_clk msm: add CLK_MINMAX to pmdh_clk msm: trout: add gpio_to_irq msm: iommu: Use the correct memory allocation flag msm_serial: Remove redundant unlikely() msm: iommu: Miscellaneous code cleanup msm: iommu: Support cache-coherent memory access msm: iommu: Definitions for extended memory attributes msm: iommu: Kconfig dependency for the IOMMU API msm: iommu: Check if device is already attached msm: iommu: Kconfig item for cacheable page tables ...tirimbino
Linus Torvalds
14 years ago
commit
b69fc2efc9
@ -0,0 +1,297 @@ |
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/* linux/arch/arm/mach-msm/board-trout-mddi.c
|
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** Author: Brian Swetland <swetland@google.com> |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/platform_device.h> |
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#include <linux/delay.h> |
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#include <linux/leds.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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|
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#include <asm/io.h> |
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#include <asm/gpio.h> |
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#include <asm/mach-types.h> |
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#include <mach/msm_fb.h> |
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#include <mach/vreg.h> |
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|
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#include "board-trout.h" |
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#include "proc_comm.h" |
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#include "devices.h" |
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#define TROUT_DEFAULT_BACKLIGHT_BRIGHTNESS 255 |
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#define MDDI_CLIENT_CORE_BASE 0x108000 |
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#define LCD_CONTROL_BLOCK_BASE 0x110000 |
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#define SPI_BLOCK_BASE 0x120000 |
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#define I2C_BLOCK_BASE 0x130000 |
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#define PWM_BLOCK_BASE 0x140000 |
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#define GPIO_BLOCK_BASE 0x150000 |
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#define SYSTEM_BLOCK1_BASE 0x160000 |
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#define SYSTEM_BLOCK2_BASE 0x170000 |
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) |
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#define SYSCLKENA (MDDI_CLIENT_CORE_BASE|0x2C) |
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#define PWM0OFF (PWM_BLOCK_BASE|0x1C) |
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|
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#define V_VDDE2E_VDD2_GPIO 0 |
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#define MDDI_RST_N 82 |
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|
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#define MDDICAP0 (MDDI_CLIENT_CORE_BASE|0x00) |
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#define MDDICAP1 (MDDI_CLIENT_CORE_BASE|0x04) |
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#define MDDICAP2 (MDDI_CLIENT_CORE_BASE|0x08) |
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#define MDDICAP3 (MDDI_CLIENT_CORE_BASE|0x0C) |
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#define MDCAPCHG (MDDI_CLIENT_CORE_BASE|0x10) |
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#define MDCRCERC (MDDI_CLIENT_CORE_BASE|0x14) |
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#define TTBUSSEL (MDDI_CLIENT_CORE_BASE|0x18) |
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#define DPSET0 (MDDI_CLIENT_CORE_BASE|0x1C) |
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#define DPSET1 (MDDI_CLIENT_CORE_BASE|0x20) |
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#define DPSUS (MDDI_CLIENT_CORE_BASE|0x24) |
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#define DPRUN (MDDI_CLIENT_CORE_BASE|0x28) |
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#define SYSCKENA (MDDI_CLIENT_CORE_BASE|0x2C) |
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#define TESTMODE (MDDI_CLIENT_CORE_BASE|0x30) |
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#define FIFOMONI (MDDI_CLIENT_CORE_BASE|0x34) |
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#define INTMONI (MDDI_CLIENT_CORE_BASE|0x38) |
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#define MDIOBIST (MDDI_CLIENT_CORE_BASE|0x3C) |
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#define MDIOPSET (MDDI_CLIENT_CORE_BASE|0x40) |
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#define BITMAP0 (MDDI_CLIENT_CORE_BASE|0x44) |
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#define BITMAP1 (MDDI_CLIENT_CORE_BASE|0x48) |
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#define BITMAP2 (MDDI_CLIENT_CORE_BASE|0x4C) |
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#define BITMAP3 (MDDI_CLIENT_CORE_BASE|0x50) |
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#define BITMAP4 (MDDI_CLIENT_CORE_BASE|0x54) |
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#define SRST (LCD_CONTROL_BLOCK_BASE|0x00) |
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#define PORT_ENB (LCD_CONTROL_BLOCK_BASE|0x04) |
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#define START (LCD_CONTROL_BLOCK_BASE|0x08) |
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#define PORT (LCD_CONTROL_BLOCK_BASE|0x0C) |
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#define CMN (LCD_CONTROL_BLOCK_BASE|0x10) |
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#define GAMMA (LCD_CONTROL_BLOCK_BASE|0x14) |
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#define INTFLG (LCD_CONTROL_BLOCK_BASE|0x18) |
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#define INTMSK (LCD_CONTROL_BLOCK_BASE|0x1C) |
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#define MPLFBUF (LCD_CONTROL_BLOCK_BASE|0x20) |
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#define HDE_LEFT (LCD_CONTROL_BLOCK_BASE|0x24) |
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#define VDE_TOP (LCD_CONTROL_BLOCK_BASE|0x28) |
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#define PXL (LCD_CONTROL_BLOCK_BASE|0x30) |
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#define HCYCLE (LCD_CONTROL_BLOCK_BASE|0x34) |
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#define HSW (LCD_CONTROL_BLOCK_BASE|0x38) |
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#define HDE_START (LCD_CONTROL_BLOCK_BASE|0x3C) |
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#define HDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x40) |
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#define VCYCLE (LCD_CONTROL_BLOCK_BASE|0x44) |
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#define VSW (LCD_CONTROL_BLOCK_BASE|0x48) |
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#define VDE_START (LCD_CONTROL_BLOCK_BASE|0x4C) |
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#define VDE_SIZE (LCD_CONTROL_BLOCK_BASE|0x50) |
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#define WAKEUP (LCD_CONTROL_BLOCK_BASE|0x54) |
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#define WSYN_DLY (LCD_CONTROL_BLOCK_BASE|0x58) |
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#define REGENB (LCD_CONTROL_BLOCK_BASE|0x5C) |
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#define VSYNIF (LCD_CONTROL_BLOCK_BASE|0x60) |
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#define WRSTB (LCD_CONTROL_BLOCK_BASE|0x64) |
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#define RDSTB (LCD_CONTROL_BLOCK_BASE|0x68) |
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#define ASY_DATA (LCD_CONTROL_BLOCK_BASE|0x6C) |
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#define ASY_DATB (LCD_CONTROL_BLOCK_BASE|0x70) |
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#define ASY_DATC (LCD_CONTROL_BLOCK_BASE|0x74) |
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#define ASY_DATD (LCD_CONTROL_BLOCK_BASE|0x78) |
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#define ASY_DATE (LCD_CONTROL_BLOCK_BASE|0x7C) |
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#define ASY_DATF (LCD_CONTROL_BLOCK_BASE|0x80) |
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#define ASY_DATG (LCD_CONTROL_BLOCK_BASE|0x84) |
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#define ASY_DATH (LCD_CONTROL_BLOCK_BASE|0x88) |
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#define ASY_CMDSET (LCD_CONTROL_BLOCK_BASE|0x8C) |
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#define SSICTL (SPI_BLOCK_BASE|0x00) |
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#define SSITIME (SPI_BLOCK_BASE|0x04) |
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#define SSITX (SPI_BLOCK_BASE|0x08) |
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#define SSIRX (SPI_BLOCK_BASE|0x0C) |
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#define SSIINTC (SPI_BLOCK_BASE|0x10) |
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#define SSIINTS (SPI_BLOCK_BASE|0x14) |
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#define SSIDBG1 (SPI_BLOCK_BASE|0x18) |
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#define SSIDBG2 (SPI_BLOCK_BASE|0x1C) |
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#define SSIID (SPI_BLOCK_BASE|0x20) |
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#define WKREQ (SYSTEM_BLOCK1_BASE|0x00) |
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#define CLKENB (SYSTEM_BLOCK1_BASE|0x04) |
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#define DRAMPWR (SYSTEM_BLOCK1_BASE|0x08) |
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#define INTMASK (SYSTEM_BLOCK1_BASE|0x0C) |
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#define GPIOSEL (SYSTEM_BLOCK2_BASE|0x00) |
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#define GPIODATA (GPIO_BLOCK_BASE|0x00) |
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#define GPIODIR (GPIO_BLOCK_BASE|0x04) |
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#define GPIOIS (GPIO_BLOCK_BASE|0x08) |
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#define GPIOIBE (GPIO_BLOCK_BASE|0x0C) |
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#define GPIOIEV (GPIO_BLOCK_BASE|0x10) |
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#define GPIOIE (GPIO_BLOCK_BASE|0x14) |
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#define GPIORIS (GPIO_BLOCK_BASE|0x18) |
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#define GPIOMIS (GPIO_BLOCK_BASE|0x1C) |
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#define GPIOIC (GPIO_BLOCK_BASE|0x20) |
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#define GPIOOMS (GPIO_BLOCK_BASE|0x24) |
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#define GPIOPC (GPIO_BLOCK_BASE|0x28) |
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#define GPIOID (GPIO_BLOCK_BASE|0x30) |
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#define SPI_WRITE(reg, val) \ |
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{ SSITX, 0x00010000 | (((reg) & 0xff) << 8) | ((val) & 0xff) }, \
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{ 0, 5 }, |
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#define SPI_WRITE1(reg) \ |
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{ SSITX, (reg) & 0xff }, \
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{ 0, 5 }, |
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struct mddi_table { |
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uint32_t reg; |
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uint32_t value; |
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}; |
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static struct mddi_table mddi_toshiba_init_table[] = { |
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{ DPSET0, 0x09e90046 }, |
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{ DPSET1, 0x00000118 }, |
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{ DPSUS, 0x00000000 }, |
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{ DPRUN, 0x00000001 }, |
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{ 1, 14 }, /* msleep 14 */ |
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{ SYSCKENA, 0x00000001 }, |
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{ CLKENB, 0x0000A1EF }, /* # SYS.CLKENB # Enable clocks for each module (without DCLK , i2cCLK) */ |
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{ GPIODATA, 0x02000200 }, /* # GPI .GPIODATA # GPIO2(RESET_LCD_N) set to 0 , GPIO3(eDRAM_Power) set to 0 */ |
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{ GPIODIR, 0x000030D }, /* 24D # GPI .GPIODIR # Select direction of GPIO port (0,2,3,6,9 output) */ |
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{ GPIOSEL, 0/*0x00000173*/}, /* # SYS.GPIOSEL # GPIO port multiplexing control */ |
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{ GPIOPC, 0x03C300C0 }, /* # GPI .GPIOPC # GPIO2,3 PD cut */ |
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{ WKREQ, 0x00000000 }, /* # SYS.WKREQ # Wake-up request event is VSYNC alignment */ |
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{ GPIOIBE, 0x000003FF }, |
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{ GPIOIS, 0x00000000 }, |
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{ GPIOIC, 0x000003FF }, |
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{ GPIOIE, 0x00000000 }, |
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{ GPIODATA, 0x00040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ |
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{ 1, 1 }, /* msleep 1 */ |
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{ GPIODATA, 0x02040004 }, /* # GPI .GPIODATA # eDRAM VD supply */ |
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{ DRAMPWR, 0x00000001 }, /* eDRAM power */ |
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}; |
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#define GPIOSEL_VWAKEINT (1U << 0) |
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#define INTMASK_VWAKEOUT (1U << 0) |
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static struct clk *gp_clk; |
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static int trout_new_backlight = 1; |
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static struct vreg *vreg_mddi_1v5; |
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static struct vreg *vreg_lcm_2v85; |
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static void trout_process_mddi_table(struct msm_mddi_client_data *client_data, |
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struct mddi_table *table, size_t count) |
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{ |
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int i; |
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for (i = 0; i < count; i++) { |
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uint32_t reg = table[i].reg; |
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uint32_t value = table[i].value; |
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if (reg == 0) |
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udelay(value); |
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else if (reg == 1) |
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msleep(value); |
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else |
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client_data->remote_write(client_data, value, reg); |
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} |
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} |
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static int trout_mddi_toshiba_client_init( |
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struct msm_mddi_bridge_platform_data *bridge_data, |
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struct msm_mddi_client_data *client_data) |
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{ |
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int panel_id; |
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client_data->auto_hibernate(client_data, 0); |
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trout_process_mddi_table(client_data, mddi_toshiba_init_table, |
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ARRAY_SIZE(mddi_toshiba_init_table)); |
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client_data->auto_hibernate(client_data, 1); |
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panel_id = (client_data->remote_read(client_data, GPIODATA) >> 4) & 3; |
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if (panel_id > 1) { |
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printk(KERN_WARNING "unknown panel id at mddi_enable\n"); |
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return -1; |
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} |
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return 0; |
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} |
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static int trout_mddi_toshiba_client_uninit( |
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struct msm_mddi_bridge_platform_data *bridge_data, |
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struct msm_mddi_client_data *client_data) |
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{ |
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return 0; |
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} |
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static struct resource resources_msm_fb[] = { |
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{ |
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.start = MSM_FB_BASE, |
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.end = MSM_FB_BASE + MSM_FB_SIZE, |
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.flags = IORESOURCE_MEM, |
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}, |
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}; |
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struct msm_mddi_bridge_platform_data toshiba_client_data = { |
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.init = trout_mddi_toshiba_client_init, |
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.uninit = trout_mddi_toshiba_client_uninit, |
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.fb_data = { |
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.xres = 320, |
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.yres = 480, |
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.width = 45, |
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.height = 67, |
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.output_format = 0, |
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}, |
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}; |
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static struct msm_mddi_platform_data mddi_pdata = { |
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.clk_rate = 122880000, |
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.fb_resource = resources_msm_fb, |
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.num_clients = 1, |
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.client_platform_data = { |
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{ |
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.product_id = (0xd263 << 16 | 0), |
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.name = "mddi_c_d263_0000", |
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.id = 0, |
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.client_data = &toshiba_client_data, |
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.clk_rate = 0, |
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}, |
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}, |
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}; |
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int __init trout_init_panel(void) |
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{ |
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int rc; |
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if (!machine_is_trout()) |
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return 0; |
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vreg_mddi_1v5 = vreg_get(0, "gp2"); |
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if (IS_ERR(vreg_mddi_1v5)) |
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return PTR_ERR(vreg_mddi_1v5); |
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vreg_lcm_2v85 = vreg_get(0, "gp4"); |
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if (IS_ERR(vreg_lcm_2v85)) |
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return PTR_ERR(vreg_lcm_2v85); |
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trout_new_backlight = system_rev >= 5; |
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if (trout_new_backlight) { |
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uint32_t config = PCOM_GPIO_CFG(27, 0, GPIO_OUTPUT, |
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GPIO_NO_PULL, GPIO_8MA); |
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msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); |
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} else { |
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uint32_t config = PCOM_GPIO_CFG(27, 1, GPIO_OUTPUT, |
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GPIO_NO_PULL, GPIO_8MA); |
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msm_proc_comm(PCOM_RPC_GPIO_TLMM_CONFIG_EX, &config, 0); |
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gp_clk = clk_get(NULL, "gp_clk"); |
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if (IS_ERR(gp_clk)) { |
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printk(KERN_ERR "trout_init_panel: could not get gp" |
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"clock\n"); |
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gp_clk = NULL; |
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} |
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rc = clk_set_rate(gp_clk, 19200000); |
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if (rc) |
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printk(KERN_ERR "trout_init_panel: set clock rate " |
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"failed\n"); |
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} |
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rc = platform_device_register(&msm_device_mdp); |
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if (rc) |
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return rc; |
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msm_device_mddi0.dev.platform_data = &mddi_pdata; |
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return platform_device_register(&msm_device_mddi0); |
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} |
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device_initcall(trout_init_panel); |
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@ -0,0 +1,426 @@ |
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/* Copyright (c) 2010, Code Aurora Forum. All rights reserved.
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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* |
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* You should have received a copy of the GNU General Public License |
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* along with this program; if not, write to the Free Software |
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* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA |
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* 02110-1301, USA. |
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* |
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*/ |
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#define pr_fmt(fmt) "%s: " fmt, __func__ |
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|
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#include <linux/bitmap.h> |
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#include <linux/bitops.h> |
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#include <linux/gpio.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/irq.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/spinlock.h> |
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#include <mach/msm_iomap.h> |
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#include "gpiomux.h" |
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/* Bits of interest in the GPIO_IN_OUT register.
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*/ |
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enum { |
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GPIO_IN = 0, |
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GPIO_OUT = 1 |
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}; |
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|
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/* Bits of interest in the GPIO_INTR_STATUS register.
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*/ |
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enum { |
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INTR_STATUS = 0, |
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}; |
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|
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/* Bits of interest in the GPIO_CFG register.
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*/ |
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enum { |
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GPIO_OE = 9, |
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}; |
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|
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/* Bits of interest in the GPIO_INTR_CFG register.
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* When a GPIO triggers, two separate decisions are made, controlled |
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* by two separate flags. |
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* |
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* - First, INTR_RAW_STATUS_EN controls whether or not the GPIO_INTR_STATUS |
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* register for that GPIO will be updated to reflect the triggering of that |
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* gpio. If this bit is 0, this register will not be updated. |
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* - Second, INTR_ENABLE controls whether an interrupt is triggered. |
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* |
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* If INTR_ENABLE is set and INTR_RAW_STATUS_EN is NOT set, an interrupt |
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* can be triggered but the status register will not reflect it. |
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*/ |
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enum { |
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INTR_ENABLE = 0, |
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INTR_POL_CTL = 1, |
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INTR_DECT_CTL = 2, |
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INTR_RAW_STATUS_EN = 3, |
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}; |
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|
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/* Codes of interest in GPIO_INTR_CFG_SU.
|
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*/ |
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enum { |
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TARGET_PROC_SCORPION = 4, |
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TARGET_PROC_NONE = 7, |
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}; |
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|
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|
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#define GPIO_INTR_CFG_SU(gpio) (MSM_TLMM_BASE + 0x0400 + (0x04 * (gpio))) |
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#define GPIO_CONFIG(gpio) (MSM_TLMM_BASE + 0x1000 + (0x10 * (gpio))) |
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#define GPIO_IN_OUT(gpio) (MSM_TLMM_BASE + 0x1004 + (0x10 * (gpio))) |
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#define GPIO_INTR_CFG(gpio) (MSM_TLMM_BASE + 0x1008 + (0x10 * (gpio))) |
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#define GPIO_INTR_STATUS(gpio) (MSM_TLMM_BASE + 0x100c + (0x10 * (gpio))) |
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|
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/**
|
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* struct msm_gpio_dev: the MSM8660 SoC GPIO device structure |
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* |
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* @enabled_irqs: a bitmap used to optimize the summary-irq handler. By |
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* keeping track of which gpios are unmasked as irq sources, we avoid |
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* having to do readl calls on hundreds of iomapped registers each time |
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* the summary interrupt fires in order to locate the active interrupts. |
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* |
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* @wake_irqs: a bitmap for tracking which interrupt lines are enabled |
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* as wakeup sources. When the device is suspended, interrupts which are |
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* not wakeup sources are disabled. |
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* |
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* @dual_edge_irqs: a bitmap used to track which irqs are configured |
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* as dual-edge, as this is not supported by the hardware and requires |
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* some special handling in the driver. |
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*/ |
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struct msm_gpio_dev { |
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struct gpio_chip gpio_chip; |
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DECLARE_BITMAP(enabled_irqs, NR_GPIO_IRQS); |
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DECLARE_BITMAP(wake_irqs, NR_GPIO_IRQS); |
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DECLARE_BITMAP(dual_edge_irqs, NR_GPIO_IRQS); |
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}; |
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|
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static DEFINE_SPINLOCK(tlmm_lock); |
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|
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static inline struct msm_gpio_dev *to_msm_gpio_dev(struct gpio_chip *chip) |
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{ |
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return container_of(chip, struct msm_gpio_dev, gpio_chip); |
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} |
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|
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static inline void set_gpio_bits(unsigned n, void __iomem *reg) |
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{ |
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writel(readl(reg) | n, reg); |
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} |
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|
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static inline void clear_gpio_bits(unsigned n, void __iomem *reg) |
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{ |
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writel(readl(reg) & ~n, reg); |
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} |
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|
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static int msm_gpio_get(struct gpio_chip *chip, unsigned offset) |
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{ |
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return readl(GPIO_IN_OUT(offset)) & BIT(GPIO_IN); |
||||
} |
||||
|
||||
static void msm_gpio_set(struct gpio_chip *chip, unsigned offset, int val) |
||||
{ |
||||
writel(val ? BIT(GPIO_OUT) : 0, GPIO_IN_OUT(offset)); |
||||
} |
||||
|
||||
static int msm_gpio_direction_input(struct gpio_chip *chip, unsigned offset) |
||||
{ |
||||
unsigned long irq_flags; |
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags); |
||||
clear_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); |
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
||||
return 0; |
||||
} |
||||
|
||||
static int msm_gpio_direction_output(struct gpio_chip *chip, |
||||
unsigned offset, |
||||
int val) |
||||
{ |
||||
unsigned long irq_flags; |
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags); |
||||
msm_gpio_set(chip, offset, val); |
||||
set_gpio_bits(BIT(GPIO_OE), GPIO_CONFIG(offset)); |
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
||||
return 0; |
||||
} |
||||
|
||||
static int msm_gpio_request(struct gpio_chip *chip, unsigned offset) |
||||
{ |
||||
return msm_gpiomux_get(chip->base + offset); |
||||
} |
||||
|
||||
static void msm_gpio_free(struct gpio_chip *chip, unsigned offset) |
||||
{ |
||||
msm_gpiomux_put(chip->base + offset); |
||||
} |
||||
|
||||
static int msm_gpio_to_irq(struct gpio_chip *chip, unsigned offset) |
||||
{ |
||||
return MSM_GPIO_TO_INT(chip->base + offset); |
||||
} |
||||
|
||||
static inline int msm_irq_to_gpio(struct gpio_chip *chip, unsigned irq) |
||||
{ |
||||
return irq - MSM_GPIO_TO_INT(chip->base); |
||||
} |
||||
|
||||
static struct msm_gpio_dev msm_gpio = { |
||||
.gpio_chip = { |
||||
.base = 0, |
||||
.ngpio = NR_GPIO_IRQS, |
||||
.direction_input = msm_gpio_direction_input, |
||||
.direction_output = msm_gpio_direction_output, |
||||
.get = msm_gpio_get, |
||||
.set = msm_gpio_set, |
||||
.to_irq = msm_gpio_to_irq, |
||||
.request = msm_gpio_request, |
||||
.free = msm_gpio_free, |
||||
}, |
||||
}; |
||||
|
||||
/* For dual-edge interrupts in software, since the hardware has no
|
||||
* such support: |
||||
* |
||||
* At appropriate moments, this function may be called to flip the polarity |
||||
* settings of both-edge irq lines to try and catch the next edge. |
||||
* |
||||
* The attempt is considered successful if: |
||||
* - the status bit goes high, indicating that an edge was caught, or |
||||
* - the input value of the gpio doesn't change during the attempt. |
||||
* If the value changes twice during the process, that would cause the first |
||||
* test to fail but would force the second, as two opposite |
||||
* transitions would cause a detection no matter the polarity setting. |
||||
* |
||||
* The do-loop tries to sledge-hammer closed the timing hole between |
||||
* the initial value-read and the polarity-write - if the line value changes |
||||
* during that window, an interrupt is lost, the new polarity setting is |
||||
* incorrect, and the first success test will fail, causing a retry. |
||||
* |
||||
* Algorithm comes from Google's msmgpio driver, see mach-msm/gpio.c. |
||||
*/ |
||||
static void msm_gpio_update_dual_edge_pos(unsigned gpio) |
||||
{ |
||||
int loop_limit = 100; |
||||
unsigned val, val2, intstat; |
||||
|
||||
do { |
||||
val = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); |
||||
if (val) |
||||
clear_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); |
||||
else |
||||
set_gpio_bits(BIT(INTR_POL_CTL), GPIO_INTR_CFG(gpio)); |
||||
val2 = readl(GPIO_IN_OUT(gpio)) & BIT(GPIO_IN); |
||||
intstat = readl(GPIO_INTR_STATUS(gpio)) & BIT(INTR_STATUS); |
||||
if (intstat || val == val2) |
||||
return; |
||||
} while (loop_limit-- > 0); |
||||
pr_err("dual-edge irq failed to stabilize, " |
||||
"interrupts dropped. %#08x != %#08x\n", |
||||
val, val2); |
||||
} |
||||
|
||||
static void msm_gpio_irq_ack(unsigned int irq) |
||||
{ |
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); |
||||
|
||||
writel(BIT(INTR_STATUS), GPIO_INTR_STATUS(gpio)); |
||||
if (test_bit(gpio, msm_gpio.dual_edge_irqs)) |
||||
msm_gpio_update_dual_edge_pos(gpio); |
||||
} |
||||
|
||||
static void msm_gpio_irq_mask(unsigned int irq) |
||||
{ |
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); |
||||
unsigned long irq_flags; |
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags); |
||||
writel(TARGET_PROC_NONE, GPIO_INTR_CFG_SU(gpio)); |
||||
clear_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); |
||||
__clear_bit(gpio, msm_gpio.enabled_irqs); |
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
||||
} |
||||
|
||||
static void msm_gpio_irq_unmask(unsigned int irq) |
||||
{ |
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); |
||||
unsigned long irq_flags; |
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags); |
||||
__set_bit(gpio, msm_gpio.enabled_irqs); |
||||
set_gpio_bits(INTR_RAW_STATUS_EN | INTR_ENABLE, GPIO_INTR_CFG(gpio)); |
||||
writel(TARGET_PROC_SCORPION, GPIO_INTR_CFG_SU(gpio)); |
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
||||
} |
||||
|
||||
static int msm_gpio_irq_set_type(unsigned int irq, unsigned int flow_type) |
||||
{ |
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); |
||||
unsigned long irq_flags; |
||||
uint32_t bits; |
||||
|
||||
spin_lock_irqsave(&tlmm_lock, irq_flags); |
||||
|
||||
bits = readl(GPIO_INTR_CFG(gpio)); |
||||
|
||||
if (flow_type & IRQ_TYPE_EDGE_BOTH) { |
||||
bits |= BIT(INTR_DECT_CTL); |
||||
irq_desc[irq].handle_irq = handle_edge_irq; |
||||
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
||||
__set_bit(gpio, msm_gpio.dual_edge_irqs); |
||||
else |
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs); |
||||
} else { |
||||
bits &= ~BIT(INTR_DECT_CTL); |
||||
irq_desc[irq].handle_irq = handle_level_irq; |
||||
__clear_bit(gpio, msm_gpio.dual_edge_irqs); |
||||
} |
||||
|
||||
if (flow_type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_LEVEL_HIGH)) |
||||
bits |= BIT(INTR_POL_CTL); |
||||
else |
||||
bits &= ~BIT(INTR_POL_CTL); |
||||
|
||||
writel(bits, GPIO_INTR_CFG(gpio)); |
||||
|
||||
if ((flow_type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH) |
||||
msm_gpio_update_dual_edge_pos(gpio); |
||||
|
||||
spin_unlock_irqrestore(&tlmm_lock, irq_flags); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
/*
|
||||
* When the summary IRQ is raised, any number of GPIO lines may be high. |
||||
* It is the job of the summary handler to find all those GPIO lines |
||||
* which have been set as summary IRQ lines and which are triggered, |
||||
* and to call their interrupt handlers. |
||||
*/ |
||||
static void msm_summary_irq_handler(unsigned int irq, struct irq_desc *desc) |
||||
{ |
||||
unsigned long i; |
||||
|
||||
for (i = find_first_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS); |
||||
i < NR_GPIO_IRQS; |
||||
i = find_next_bit(msm_gpio.enabled_irqs, NR_GPIO_IRQS, i + 1)) { |
||||
if (readl(GPIO_INTR_STATUS(i)) & BIT(INTR_STATUS)) |
||||
generic_handle_irq(msm_gpio_to_irq(&msm_gpio.gpio_chip, |
||||
i)); |
||||
} |
||||
desc->chip->ack(irq); |
||||
} |
||||
|
||||
static int msm_gpio_irq_set_wake(unsigned int irq, unsigned int on) |
||||
{ |
||||
int gpio = msm_irq_to_gpio(&msm_gpio.gpio_chip, irq); |
||||
|
||||
if (on) { |
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 1); |
||||
set_bit(gpio, msm_gpio.wake_irqs); |
||||
} else { |
||||
clear_bit(gpio, msm_gpio.wake_irqs); |
||||
if (bitmap_empty(msm_gpio.wake_irqs, NR_GPIO_IRQS)) |
||||
set_irq_wake(TLMM_SCSS_SUMMARY_IRQ, 0); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct irq_chip msm_gpio_irq_chip = { |
||||
.name = "msmgpio", |
||||
.mask = msm_gpio_irq_mask, |
||||
.unmask = msm_gpio_irq_unmask, |
||||
.ack = msm_gpio_irq_ack, |
||||
.set_type = msm_gpio_irq_set_type, |
||||
.set_wake = msm_gpio_irq_set_wake, |
||||
}; |
||||
|
||||
static int __devinit msm_gpio_probe(struct platform_device *dev) |
||||
{ |
||||
int i, irq, ret; |
||||
|
||||
bitmap_zero(msm_gpio.enabled_irqs, NR_GPIO_IRQS); |
||||
bitmap_zero(msm_gpio.wake_irqs, NR_GPIO_IRQS); |
||||
bitmap_zero(msm_gpio.dual_edge_irqs, NR_GPIO_IRQS); |
||||
msm_gpio.gpio_chip.label = dev->name; |
||||
ret = gpiochip_add(&msm_gpio.gpio_chip); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
for (i = 0; i < msm_gpio.gpio_chip.ngpio; ++i) { |
||||
irq = msm_gpio_to_irq(&msm_gpio.gpio_chip, i); |
||||
set_irq_chip(irq, &msm_gpio_irq_chip); |
||||
set_irq_handler(irq, handle_level_irq); |
||||
set_irq_flags(irq, IRQF_VALID); |
||||
} |
||||
|
||||
set_irq_chained_handler(TLMM_SCSS_SUMMARY_IRQ, |
||||
msm_summary_irq_handler); |
||||
return 0; |
||||
} |
||||
|
||||
static int __devexit msm_gpio_remove(struct platform_device *dev) |
||||
{ |
||||
int ret = gpiochip_remove(&msm_gpio.gpio_chip); |
||||
|
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
set_irq_handler(TLMM_SCSS_SUMMARY_IRQ, NULL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct platform_driver msm_gpio_driver = { |
||||
.probe = msm_gpio_probe, |
||||
.remove = __devexit_p(msm_gpio_remove), |
||||
.driver = { |
||||
.name = "msmgpio", |
||||
.owner = THIS_MODULE, |
||||
}, |
||||
}; |
||||
|
||||
static struct platform_device msm_device_gpio = { |
||||
.name = "msmgpio", |
||||
.id = -1, |
||||
}; |
||||
|
||||
static int __init msm_gpio_init(void) |
||||
{ |
||||
int rc; |
||||
|
||||
rc = platform_driver_register(&msm_gpio_driver); |
||||
if (!rc) { |
||||
rc = platform_device_register(&msm_device_gpio); |
||||
if (rc) |
||||
platform_driver_unregister(&msm_gpio_driver); |
||||
} |
||||
|
||||
return rc; |
||||
} |
||||
|
||||
static void __exit msm_gpio_exit(void) |
||||
{ |
||||
platform_device_unregister(&msm_device_gpio); |
||||
platform_driver_unregister(&msm_gpio_driver); |
||||
} |
||||
|
||||
postcore_initcall(msm_gpio_init); |
||||
module_exit(msm_gpio_exit); |
||||
|
||||
MODULE_AUTHOR("Gregory Bean <gbean@codeaurora.org>"); |
||||
MODULE_DESCRIPTION("Driver for Qualcomm MSM TLMMv2 SoC GPIOs"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
MODULE_ALIAS("platform:msmgpio"); |
||||
Loading…
Reference in new issue