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@ -374,6 +374,7 @@ ENTRY(alt_dtlb_miss) |
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movl r19=(((1 << IA64_MAX_PHYS_BITS) - 1) & ~0xfff) |
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mov r21=cr.ipsr |
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mov r31=pr |
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mov r24=PERCPU_ADDR |
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;;
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#ifdef CONFIG_DISABLE_VHPT |
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shr.u r22=r16,61 // get the region number into r21 |
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@ -386,22 +387,30 @@ ENTRY(alt_dtlb_miss) |
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(p8) mov r29=b0 // save b0 |
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(p8) br.cond.dptk dtlb_fault |
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#endif |
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cmp.ge p10,p11=r16,r24 // access to per_cpu_data? |
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tbit.z p12,p0=r16,61 // access to region 6? |
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mov r25=PERCPU_PAGE_SHIFT << 2 |
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mov r26=PERCPU_PAGE_SIZE |
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nop.m 0 |
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nop.b 0 |
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;;
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(p10) mov r19=IA64_KR(PER_CPU_DATA) |
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(p11) and r19=r19,r16 // clear non-ppn fields |
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extr.u r23=r21,IA64_PSR_CPL0_BIT,2 // extract psr.cpl |
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and r22=IA64_ISR_CODE_MASK,r20 // get the isr.code field |
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tbit.nz p6,p7=r20,IA64_ISR_SP_BIT // is speculation bit on? |
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shr.u r18=r16,57 // move address bit 61 to bit 4 |
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and r19=r19,r16 // clear ed, reserved bits, and PTE control bits |
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tbit.nz p9,p0=r20,IA64_ISR_NA_BIT // is non-access bit on? |
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;;
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andcm r18=0x10,r18 // bit 4=~address-bit(61) |
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(p10) sub r19=r19,r26 |
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(p10) mov cr.itir=r25 |
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cmp.ne p8,p0=r0,r23 |
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(p9) cmp.eq.or.andcm p6,p7=IA64_ISR_CODE_LFETCH,r22 // check isr.code field |
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(p12) dep r17=-1,r17,4,1 // set ma=UC for region 6 addr |
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(p8) br.cond.spnt page_fault |
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dep r21=-1,r21,IA64_PSR_ED_BIT,1 |
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or r19=r19,r17 // insert PTE control bits into r19 |
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;;
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or r19=r19,r18 // set bit 4 (uncached) if the access was to region 6 |
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or r19=r19,r17 // insert PTE control bits into r19 |
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(p6) mov cr.ipsr=r21 |
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;;
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(p7) itc.d r19 // insert the TLB entry |
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