Adding PHY driver support for USB 3.0 controller for Samsung's SoCs. Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com> Acked-by: Kukjin Kim <kgene.kim@samsung.com> Signed-off-by: Felipe Balbi <balbi@ti.com>tirimbino
Vivek Gautam
12 years ago
committed by
Felipe Balbi
parent
dc2377d0b0
commit
b527675817
@ -0,0 +1,349 @@ |
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/* linux/drivers/usb/phy/phy-samsung-usb3.c
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* |
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* Copyright (c) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com
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* |
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* Author: Vivek Gautam <gautam.vivek@samsung.com> |
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* |
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* Samsung USB 3.0 PHY transceiver; talks to DWC3 controller. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/usb/samsung_usb_phy.h> |
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#include <linux/platform_data/samsung-usbphy.h> |
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#include "phy-samsung-usb.h" |
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/*
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* Sets the phy clk as EXTREFCLK (XXTI) which is internal clock from clock core. |
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*/ |
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static u32 samsung_usb3phy_set_refclk(struct samsung_usbphy *sphy) |
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{ |
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u32 reg; |
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u32 refclk; |
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refclk = sphy->ref_clk_freq; |
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reg = PHYCLKRST_REFCLKSEL_EXT_REFCLK | |
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PHYCLKRST_FSEL(refclk); |
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switch (refclk) { |
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case FSEL_CLKSEL_50M: |
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_50M_REF | |
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PHYCLKRST_SSC_REFCLKSEL(0x00)); |
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break; |
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case FSEL_CLKSEL_20M: |
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF | |
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PHYCLKRST_SSC_REFCLKSEL(0x00)); |
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break; |
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case FSEL_CLKSEL_19200K: |
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF | |
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PHYCLKRST_SSC_REFCLKSEL(0x88)); |
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break; |
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case FSEL_CLKSEL_24M: |
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default: |
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reg |= (PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF | |
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PHYCLKRST_SSC_REFCLKSEL(0x88)); |
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break; |
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} |
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return reg; |
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} |
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static int samsung_exynos5_usb3phy_enable(struct samsung_usbphy *sphy) |
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{ |
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void __iomem *regs = sphy->regs; |
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u32 phyparam0; |
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u32 phyparam1; |
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u32 linksystem; |
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u32 phybatchg; |
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u32 phytest; |
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u32 phyclkrst; |
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/* Reset USB 3.0 PHY */ |
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writel(0x0, regs + EXYNOS5_DRD_PHYREG0); |
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phyparam0 = readl(regs + EXYNOS5_DRD_PHYPARAM0); |
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/* Select PHY CLK source */ |
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phyparam0 &= ~PHYPARAM0_REF_USE_PAD; |
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/* Set Loss-of-Signal Detector sensitivity */ |
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phyparam0 &= ~PHYPARAM0_REF_LOSLEVEL_MASK; |
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phyparam0 |= PHYPARAM0_REF_LOSLEVEL; |
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writel(phyparam0, regs + EXYNOS5_DRD_PHYPARAM0); |
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writel(0x0, regs + EXYNOS5_DRD_PHYRESUME); |
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/*
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* Setting the Frame length Adj value[6:1] to default 0x20 |
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* See xHCI 1.0 spec, 5.2.4 |
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*/ |
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linksystem = LINKSYSTEM_XHCI_VERSION_CONTROL | |
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LINKSYSTEM_FLADJ(0x20); |
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writel(linksystem, regs + EXYNOS5_DRD_LINKSYSTEM); |
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phyparam1 = readl(regs + EXYNOS5_DRD_PHYPARAM1); |
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/* Set Tx De-Emphasis level */ |
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phyparam1 &= ~PHYPARAM1_PCS_TXDEEMPH_MASK; |
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phyparam1 |= PHYPARAM1_PCS_TXDEEMPH; |
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writel(phyparam1, regs + EXYNOS5_DRD_PHYPARAM1); |
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phybatchg = readl(regs + EXYNOS5_DRD_PHYBATCHG); |
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phybatchg |= PHYBATCHG_UTMI_CLKSEL; |
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writel(phybatchg, regs + EXYNOS5_DRD_PHYBATCHG); |
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/* PHYTEST POWERDOWN Control */ |
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phytest = readl(regs + EXYNOS5_DRD_PHYTEST); |
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phytest &= ~(PHYTEST_POWERDOWN_SSP | |
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PHYTEST_POWERDOWN_HSP); |
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writel(phytest, regs + EXYNOS5_DRD_PHYTEST); |
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/* UTMI Power Control */ |
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writel(PHYUTMI_OTGDISABLE, regs + EXYNOS5_DRD_PHYUTMI); |
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phyclkrst = samsung_usb3phy_set_refclk(sphy); |
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phyclkrst |= PHYCLKRST_PORTRESET | |
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/* Digital power supply in normal operating mode */ |
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PHYCLKRST_RETENABLEN | |
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/* Enable ref clock for SS function */ |
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PHYCLKRST_REF_SSP_EN | |
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/* Enable spread spectrum */ |
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PHYCLKRST_SSC_EN | |
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/* Power down HS Bias and PLL blocks in suspend mode */ |
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PHYCLKRST_COMMONONN; |
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); |
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udelay(10); |
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phyclkrst &= ~(PHYCLKRST_PORTRESET); |
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); |
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return 0; |
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} |
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static void samsung_exynos5_usb3phy_disable(struct samsung_usbphy *sphy) |
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{ |
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u32 phyutmi; |
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u32 phyclkrst; |
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u32 phytest; |
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void __iomem *regs = sphy->regs; |
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phyutmi = PHYUTMI_OTGDISABLE | |
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PHYUTMI_FORCESUSPEND | |
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PHYUTMI_FORCESLEEP; |
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writel(phyutmi, regs + EXYNOS5_DRD_PHYUTMI); |
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/* Resetting the PHYCLKRST enable bits to reduce leakage current */ |
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phyclkrst = readl(regs + EXYNOS5_DRD_PHYCLKRST); |
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phyclkrst &= ~(PHYCLKRST_REF_SSP_EN | |
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PHYCLKRST_SSC_EN | |
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PHYCLKRST_COMMONONN); |
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writel(phyclkrst, regs + EXYNOS5_DRD_PHYCLKRST); |
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/* Control PHYTEST to remove leakage current */ |
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phytest = readl(regs + EXYNOS5_DRD_PHYTEST); |
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phytest |= (PHYTEST_POWERDOWN_SSP | |
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PHYTEST_POWERDOWN_HSP); |
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writel(phytest, regs + EXYNOS5_DRD_PHYTEST); |
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} |
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static int samsung_usb3phy_init(struct usb_phy *phy) |
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{ |
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struct samsung_usbphy *sphy; |
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unsigned long flags; |
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int ret = 0; |
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sphy = phy_to_sphy(phy); |
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/* Enable the phy clock */ |
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ret = clk_prepare_enable(sphy->clk); |
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if (ret) { |
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dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); |
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return ret; |
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} |
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spin_lock_irqsave(&sphy->lock, flags); |
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/* setting default phy-type for USB 3.0 */ |
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE); |
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/* Disable phy isolation */ |
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samsung_usbphy_set_isolation(sphy, false); |
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/* Initialize usb phy registers */ |
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samsung_exynos5_usb3phy_enable(sphy); |
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spin_unlock_irqrestore(&sphy->lock, flags); |
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/* Disable the phy clock */ |
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clk_disable_unprepare(sphy->clk); |
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return ret; |
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} |
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/*
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* The function passed to the usb driver for phy shutdown |
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*/ |
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static void samsung_usb3phy_shutdown(struct usb_phy *phy) |
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{ |
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struct samsung_usbphy *sphy; |
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unsigned long flags; |
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sphy = phy_to_sphy(phy); |
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if (clk_prepare_enable(sphy->clk)) { |
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dev_err(sphy->dev, "%s: clk_prepare_enable failed\n", __func__); |
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return; |
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} |
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spin_lock_irqsave(&sphy->lock, flags); |
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/* setting default phy-type for USB 3.0 */ |
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samsung_usbphy_set_type(&sphy->phy, USB_PHY_TYPE_DEVICE); |
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/* De-initialize usb phy registers */ |
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samsung_exynos5_usb3phy_disable(sphy); |
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/* Enable phy isolation */ |
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samsung_usbphy_set_isolation(sphy, true); |
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spin_unlock_irqrestore(&sphy->lock, flags); |
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clk_disable_unprepare(sphy->clk); |
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} |
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static int samsung_usb3phy_probe(struct platform_device *pdev) |
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{ |
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struct samsung_usbphy *sphy; |
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struct samsung_usbphy_data *pdata = pdev->dev.platform_data; |
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struct device *dev = &pdev->dev; |
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struct resource *phy_mem; |
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void __iomem *phy_base; |
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struct clk *clk; |
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int ret; |
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phy_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!phy_mem) { |
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dev_err(dev, "%s: missing mem resource\n", __func__); |
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return -ENODEV; |
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} |
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phy_base = devm_request_and_ioremap(dev, phy_mem); |
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if (!phy_base) { |
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dev_err(dev, "%s: register mapping failed\n", __func__); |
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return -ENXIO; |
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} |
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sphy = devm_kzalloc(dev, sizeof(*sphy), GFP_KERNEL); |
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if (!sphy) |
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return -ENOMEM; |
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clk = devm_clk_get(dev, "usbdrd30"); |
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if (IS_ERR(clk)) { |
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dev_err(dev, "Failed to get device clock\n"); |
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return PTR_ERR(clk); |
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} |
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sphy->dev = dev; |
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if (dev->of_node) { |
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ret = samsung_usbphy_parse_dt(sphy); |
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if (ret < 0) |
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return ret; |
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} else { |
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if (!pdata) { |
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dev_err(dev, "no platform data specified\n"); |
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return -EINVAL; |
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} |
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} |
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sphy->plat = pdata; |
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sphy->regs = phy_base; |
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sphy->clk = clk; |
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sphy->phy.dev = sphy->dev; |
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sphy->phy.label = "samsung-usb3phy"; |
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sphy->phy.init = samsung_usb3phy_init; |
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sphy->phy.shutdown = samsung_usb3phy_shutdown; |
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sphy->drv_data = samsung_usbphy_get_driver_data(pdev); |
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sphy->ref_clk_freq = samsung_usbphy_get_refclk_freq(sphy); |
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spin_lock_init(&sphy->lock); |
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platform_set_drvdata(pdev, sphy); |
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return usb_add_phy(&sphy->phy, USB_PHY_TYPE_USB3); |
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} |
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static int samsung_usb3phy_remove(struct platform_device *pdev) |
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{ |
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struct samsung_usbphy *sphy = platform_get_drvdata(pdev); |
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usb_remove_phy(&sphy->phy); |
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if (sphy->pmuregs) |
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iounmap(sphy->pmuregs); |
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if (sphy->sysreg) |
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iounmap(sphy->sysreg); |
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return 0; |
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} |
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static struct samsung_usbphy_drvdata usb3phy_exynos5 = { |
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.cpu_type = TYPE_EXYNOS5250, |
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.devphy_en_mask = EXYNOS_USBPHY_ENABLE, |
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}; |
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#ifdef CONFIG_OF |
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static const struct of_device_id samsung_usbphy_dt_match[] = { |
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{ |
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.compatible = "samsung,exynos5250-usb3phy", |
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.data = &usb3phy_exynos5 |
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}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(of, samsung_usbphy_dt_match); |
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#endif |
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static struct platform_device_id samsung_usbphy_driver_ids[] = { |
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{ |
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.name = "exynos5250-usb3phy", |
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.driver_data = (unsigned long)&usb3phy_exynos5, |
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}, |
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{}, |
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}; |
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MODULE_DEVICE_TABLE(platform, samsung_usbphy_driver_ids); |
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static struct platform_driver samsung_usb3phy_driver = { |
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.probe = samsung_usb3phy_probe, |
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.remove = samsung_usb3phy_remove, |
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.id_table = samsung_usbphy_driver_ids, |
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.driver = { |
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.name = "samsung-usb3phy", |
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.owner = THIS_MODULE, |
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.of_match_table = of_match_ptr(samsung_usbphy_dt_match), |
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}, |
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}; |
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module_platform_driver(samsung_usb3phy_driver); |
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MODULE_DESCRIPTION("Samsung USB 3.0 phy controller"); |
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MODULE_AUTHOR("Vivek Gautam <gautam.vivek@samsung.com>"); |
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MODULE_LICENSE("GPL"); |
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MODULE_ALIAS("platform:samsung-usb3phy"); |
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