msm: pcie: Add PCIe controller support for QCS405

Add PCIe controller support for QCS405 for RC mode.

Change-Id: I3aaa54ef24fc3d69ea536bca5e0903e6684dbab4
Signed-off-by: Rama Krishna Phani A <rphani@codeaurora.org>
Signed-off-by: Vijayavardhan Vennapusa <vvreddy@codeaurora.org>

Documentation/devicetree/bindings/pci/msm_pcie.txt

@@ -122,6 +122,7 @@ Optional Properties:
     and reset lines used by this controller.
   - reset-names: reset signal name strings sorted in the same order as the resets
     property.
+  - clock-output-names: name of the outgoing clock signal from the PHY PLL.
 
 =================
 Root Complex node

drivers/pci/host/pci-msm.c

@@ -17,6 +17,7 @@
 #include <linux/module.h>
 #include <linux/bitops.h>
 #include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/debugfs.h>
 #include <linux/delay.h>
 #include <linux/jiffies.h>
@@ -963,7 +964,7 @@ static void pcie_phy_init(struct msm_pcie_dev_t *dev)
 	struct msm_pcie_phy_info_t *phy_seq;
 
 	PCIE_DBG(dev,
-		"RC%d: Initializing 14nm QMP phy - 19.2MHz with Common Mode Clock (SSC ON)\n",
+		"RC%d: Initializing 14nm QMP phy - 19.2MHz or 28LP SNP - 100MHz\n",
 		dev->rc_idx);
 
 	if (dev->phy_sequence) {
@@ -3335,6 +3336,52 @@ static void msm_pcie_config_controller(struct msm_pcie_dev_t *dev)
 	}
 }
 
+/*
+ * Register a fixed rate pipe clock.
+ *
+ * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
+ * controls it. The <s>_pipe_clk coming out of the GCC is requested
+ * by the PHY driver for its operations.
+ * We register the <s>_pipe_clksrc here. The gcc driver takes care
+ * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
+ * Below picture shows this relationship.
+ *
+ *         +---------------+
+ *         |   PHY block   |<<---------------------------------------+
+ *         |               |                                         |
+ *         |   +-------+   |                   +-----+               |
+ *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
+ *    clk  |   +-------+   |                   +-----+
+ *         +---------------+
+ */
+static int phy_pipe_clk_register(struct msm_pcie_dev_t *dev,
+			struct platform_device *pdev)
+{
+	struct clk_fixed_rate *pipe_clk_fixed;
+	struct clk_init_data init = { };
+	int ret;
+
+	ret = of_property_read_string((&pdev->dev)->of_node,
+					"clock-output-names", &init.name);
+	if (ret) {
+		PCIE_DBG(dev, "No clock-output-names for RC%d\n",
+				dev->rc_idx);
+		return ret;
+	}
+
+	pipe_clk_fixed = devm_kzalloc(&pdev->dev,
+					sizeof(*pipe_clk_fixed), GFP_KERNEL);
+	if (!pipe_clk_fixed)
+		return -ENOMEM;
+
+	init.ops = &clk_fixed_rate_ops;
+
+	pipe_clk_fixed->fixed_rate = 250000000;
+	pipe_clk_fixed->hw.init = &init;
+
+	return devm_clk_hw_register(&pdev->dev, &pipe_clk_fixed->hw);
+}
+
 static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 					struct platform_device *pdev)
 {
@@ -3642,8 +3689,7 @@ static int msm_pcie_get_resources(struct msm_pcie_dev_t *dev,
 			PCIE_ERR(dev,
 				"PCIe: Failed to register bus client for RC%d (%s)\n",
 				dev->rc_idx, dev->pdev->name);
-			msm_bus_cl_clear_pdata(dev->bus_scale_table);
-			ret = -ENODEV;
+			ret = -EPROBE_DEFER;
 			goto out;
 		}
 	}
@@ -5745,6 +5791,16 @@ static int msm_pcie_probe(struct platform_device *pdev)
 
 	msm_pcie_dev[rc_idx].drv_ready = true;
 
+	/*
+	 * Register the pipe clock provided by phy.
+	 * See function description to see details of this pipe clock.
+	 */
+	ret = phy_pipe_clk_register(&msm_pcie_dev[rc_idx],
+						msm_pcie_dev[rc_idx].pdev);
+	if (ret)
+		PCIE_DBG(&msm_pcie_dev[rc_idx],
+			"PCIe:RC%d didn't register pipeclock source\n", rc_idx);
+
 	if (msm_pcie_dev[rc_idx].boot_option &
 			MSM_PCIE_NO_PROBE_ENUMERATION) {
 		PCIE_DBG(&msm_pcie_dev[rc_idx],