jenna
/
kernel_samsung_sm7125
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

MIPS: ath79: Introduce <dt-bindings/clock/ath79-clk.h>

Browse Source 
The include/dt-bindings/clock/ath79-clk.h header file
is introduced so we can use symbolic identifiers for SoC clocks.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Cc: Gabor Juhos <juhosg@openwrt.org>
Cc: Alban Bedel <albeu@free.fr>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: linux-mips@linux-mips.org
Cc: linux-clk@vger.kernel.org
Cc: devicetree@vger.kernel.org
Patchwork: https://patchwork.linux-mips.org/patch/12875/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
tirimbino
Antony Pavlov 9 years ago committed by Ralf Baechle
parent 83fe838466
commit af5ad0de22
3 changed files with 41 additions and 19 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
Show Stats Download Patch File Download Diff File
  1. 33
      arch/mips/ath79/clock.c
  2. 8
      arch/mips/boot/dts/qca/ar9132.dtsi
  3. 19
      include/dt-bindings/clock/ath79-clk.h

33
arch/mips/ath79/clock.c
Unescape View File

@ -18,6 +18,7 @@
#include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <dt-bindings/clock/ath79-clk.h>
#include <asm/div64.h>
@ -28,7 +29,7 @@
#define AR71XX_BASE_FREQ 40000000
#define AR724X_BASE_FREQ 40000000
static struct clk *clks[3];
static struct clk *clks[ATH79_CLK_END];
static struct clk_onecell_data clk_data = {
.clks = clks,
.clk_num = ARRAY_SIZE(clks),
@ -78,9 +79,9 @@ static void __init ar71xx_clocks_init(void)
ahb_rate = cpu_rate / div;
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
@ -114,9 +115,9 @@ static void __init ar724x_clocks_init(void)
ahb_rate = cpu_rate / div;
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ahb", NULL);
@ -176,9 +177,9 @@ static void __init ar933x_clocks_init(void)
}
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ahb", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@ -310,9 +311,9 @@ static void __init ar934x_clocks_init(void)
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);
@ -397,9 +398,9 @@ static void __init qca955x_clocks_init(void)
ahb_rate = cpu_pll / (postdiv + 1);
ath79_add_sys_clkdev("ref", ref_rate);
clks[0] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[1] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[2] = ath79_add_sys_clkdev("ahb", ahb_rate);
clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
clk_add_alias("wdt", NULL, "ref", NULL);
clk_add_alias("uart", NULL, "ref", NULL);

8
arch/mips/boot/dts/qca/ar9132.dtsi
Unescape View File

@ -1,3 +1,5 @@
#include <dt-bindings/clock/ath79-clk.h>
/ {
compatible = "qca,ar9132";
@ -57,7 +59,7 @@
reg = <0x18020000 0x20>;
interrupts = <3>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "uart";
reg-io-width = <4>;
@ -100,7 +102,7 @@
interrupts = <4>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "wdt";
};
@ -144,7 +146,7 @@
compatible = "qca,ar9132-spi", "qca,ar7100-spi";
reg = <0x1f000000 0x10>;
clocks = <&pll 2>;
clocks = <&pll ATH79_CLK_AHB>;
clock-names = "ahb";
status = "disabled";

19
include/dt-bindings/clock/ath79-clk.h
Unescape View File

@ -0,0 +1,19 @@
/*
* Copyright (C) 2014, 2016 Antony Pavlov <antonynpavlov@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
*/
#ifndef __DT_BINDINGS_ATH79_CLK_H
#define __DT_BINDINGS_ATH79_CLK_H
#define ATH79_CLK_CPU 0
#define ATH79_CLK_DDR 1
#define ATH79_CLK_AHB 2
#define ATH79_CLK_END 3
#endif /* __DT_BINDINGS_ATH79_CLK_H */
Write Preview
Loading…
Cancel
Save