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@ -20,7 +20,7 @@ |
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* reset while the Core B bit (on dual core parts) is cleared by |
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* the core reset. |
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*/ |
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__attribute__((l1_text)) |
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__attribute__ ((__l1_text__, __noreturn__)) |
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static void _bfin_reset(void) |
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{ |
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/* Wait for completion of "system" events such as cache line
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@ -30,7 +30,11 @@ static void _bfin_reset(void) |
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*/ |
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__builtin_bfin_ssync(); |
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while (1) { |
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/* The bootrom checks to see how it was reset and will
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* automatically perform a software reset for us when |
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* it starts executing after the core reset. |
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*/ |
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if (ANOMALY_05000353 || ANOMALY_05000386) { |
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/* Initiate System software reset. */ |
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bfin_write_SWRST(0x7); |
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@ -50,6 +54,11 @@ static void _bfin_reset(void) |
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/* Clear System software reset */ |
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bfin_write_SWRST(0); |
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/* The BF526 ROM will crash during reset */ |
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#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__) |
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bfin_read_SWRST(); |
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#endif |
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/* Wait for the SWRST write to complete. Cannot rely on SSYNC
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* though as the System state is all reset now. |
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*/ |
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@ -60,22 +69,17 @@ static void _bfin_reset(void) |
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: "a" (15 * 1) |
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: "LC1", "LB1", "LT1" |
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); |
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} |
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while (1) |
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/* Issue core reset */ |
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asm("raise 1"); |
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} |
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} |
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__attribute__ ((__noreturn__)) |
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static void bfin_reset(void) |
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{ |
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if (ANOMALY_05000353 || ANOMALY_05000386) |
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_bfin_reset(); |
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else |
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/* the bootrom checks to see how it was reset and will
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* automatically perform a software reset for us when |
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* it starts executing boot |
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*/ |
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asm("raise 1;"); |
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_bfin_reset(); |
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} |
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__attribute__((weak)) |
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