PCI device hotplug
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)
MPS (Max Payload Size)
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)
SR-IOV
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)
Virtualization
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)
Miscellaneous
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
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Merge tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci
Pull PCI changes from Bjorn Helgaas:
PCI device hotplug:
- Use PCIe native hotplug, not ACPI hotplug, when possible (Neil Horman)
- Assign resources on per-host bridge basis (Yinghai Lu)
MPS (Max Payload Size):
- Allow larger MPS settings below hotplug-capable Root Port (Yijing Wang)
- Add warnings about unsafe MPS settings (Yijing Wang)
- Simplify interface and messages (Bjorn Helgaas)
SR-IOV:
- Return -ENOSYS on non-SR-IOV devices (Stefan Assmann)
- Update NumVFs register when disabling SR-IOV (Yijing Wang)
Virtualization:
- Add bus and slot reset support (Alex Williamson)
- Fix ACS (Access Control Services) issues (Alex Williamson)
Miscellaneous:
- Simplify PCIe Capability accessors (Bjorn Helgaas)
- Add pcibios_pm_ops for arch-specific hibernate stuff (Sebastian Ott)
- Disable decoding during BAR sizing only when necessary (Zoltan Kiss)
- Delay enabling bridges until they're needed (Yinghai Lu)
- Split Designware support into Synopsys and Exynos parts (Jingoo Han)
- Convert class code to use dev_groups (Greg Kroah-Hartman)
- Cleanup Designware and Exynos I/O access wrappers (Seungwon Jeon)
- Fix bridge I/O window alignment (Bjorn Helgaas)
- Add pci_wait_for_pending_transaction() (Casey Leedom)
- Use devm_ioremap_resource() in Marvell driver (Tushar Behera)
* tag 'pci-v3.12-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (63 commits)
PCI/ACPI: Fix _OSC ordering to allow PCIe hotplug use when available
PCI: exynos: Add I/O access wrappers
PCI: designware: Drop "addr" arg from dw_pcie_readl_rc()/dw_pcie_writel_rc()
PCI: Remove pcie_cap_has_devctl()
PCI: Support PCIe Capability Slot registers only for ports with slots
PCI: Remove PCIe Capability version checks
PCI: Allow PCIe Capability link-related register access for switches
PCI: Add offsets of PCIe capability registers
PCI: Tidy bitmasks and spacing of PCIe capability definitions
PCI: Remove obsolete comment reference to pci_pcie_cap2()
PCI: Clarify PCI_EXP_TYPE_PCI_BRIDGE comment
PCI: Rename PCIe capability definitions to follow convention
PCI: Warn if unsafe MPS settings detected
PCI: Fix MPS peer-to-peer DMA comment syntax
PCI: Disable decoding for BAR sizing only when it was actually enabled
PCI: Add comment about needing pci_msi_off() even when CONFIG_PCI_MSI=n
PCI: Add pcibios_pm_ops for optional arch-specific hibernate functionality
PCI: Don't restrict MPS for slots below Root Ports
PCI: Simplify MPS test for Downstream Port
PCI: Remove unnecessary check for pcie_get_mps() failure
...
tirimbino
Linus Torvalds
12 years ago
commit
a923874198
@ -1,2 +1,3 @@ |
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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obj-$(CONFIG_PCIE_DW) += pcie-designware.o
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obj-$(CONFIG_PCI_EXYNOS) += pci-exynos.o
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obj-$(CONFIG_PCI_MVEBU) += pci-mvebu.o
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|
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@ -0,0 +1,552 @@ |
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/*
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* PCIe host controller driver for Samsung EXYNOS SoCs |
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* |
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* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
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* http://www.samsung.com
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* |
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* Author: Jingoo Han <jg1.han@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/delay.h> |
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#include <linux/gpio.h> |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of_gpio.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/resource.h> |
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#include <linux/signal.h> |
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#include <linux/types.h> |
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#include "pcie-designware.h" |
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#define to_exynos_pcie(x) container_of(x, struct exynos_pcie, pp) |
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struct exynos_pcie { |
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void __iomem *elbi_base; |
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void __iomem *phy_base; |
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void __iomem *block_base; |
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int reset_gpio; |
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struct clk *clk; |
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struct clk *bus_clk; |
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struct pcie_port pp; |
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}; |
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/* PCIe ELBI registers */ |
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#define PCIE_IRQ_PULSE 0x000 |
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#define IRQ_INTA_ASSERT (0x1 << 0) |
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#define IRQ_INTB_ASSERT (0x1 << 2) |
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#define IRQ_INTC_ASSERT (0x1 << 4) |
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#define IRQ_INTD_ASSERT (0x1 << 6) |
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#define PCIE_IRQ_LEVEL 0x004 |
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#define PCIE_IRQ_SPECIAL 0x008 |
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#define PCIE_IRQ_EN_PULSE 0x00c |
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#define PCIE_IRQ_EN_LEVEL 0x010 |
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#define PCIE_IRQ_EN_SPECIAL 0x014 |
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#define PCIE_PWR_RESET 0x018 |
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#define PCIE_CORE_RESET 0x01c |
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#define PCIE_CORE_RESET_ENABLE (0x1 << 0) |
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#define PCIE_STICKY_RESET 0x020 |
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#define PCIE_NONSTICKY_RESET 0x024 |
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#define PCIE_APP_INIT_RESET 0x028 |
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#define PCIE_APP_LTSSM_ENABLE 0x02c |
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#define PCIE_ELBI_RDLH_LINKUP 0x064 |
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#define PCIE_ELBI_LTSSM_ENABLE 0x1 |
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#define PCIE_ELBI_SLV_AWMISC 0x11c |
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#define PCIE_ELBI_SLV_ARMISC 0x120 |
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#define PCIE_ELBI_SLV_DBI_ENABLE (0x1 << 21) |
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|
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/* PCIe Purple registers */ |
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#define PCIE_PHY_GLOBAL_RESET 0x000 |
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#define PCIE_PHY_COMMON_RESET 0x004 |
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#define PCIE_PHY_CMN_REG 0x008 |
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#define PCIE_PHY_MAC_RESET 0x00c |
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#define PCIE_PHY_PLL_LOCKED 0x010 |
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#define PCIE_PHY_TRSVREG_RESET 0x020 |
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#define PCIE_PHY_TRSV_RESET 0x024 |
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/* PCIe PHY registers */ |
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#define PCIE_PHY_IMPEDANCE 0x004 |
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#define PCIE_PHY_PLL_DIV_0 0x008 |
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#define PCIE_PHY_PLL_BIAS 0x00c |
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#define PCIE_PHY_DCC_FEEDBACK 0x014 |
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#define PCIE_PHY_PLL_DIV_1 0x05c |
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#define PCIE_PHY_TRSV0_EMP_LVL 0x084 |
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#define PCIE_PHY_TRSV0_DRV_LVL 0x088 |
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#define PCIE_PHY_TRSV0_RXCDR 0x0ac |
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#define PCIE_PHY_TRSV0_LVCC 0x0dc |
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#define PCIE_PHY_TRSV1_EMP_LVL 0x144 |
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#define PCIE_PHY_TRSV1_RXCDR 0x16c |
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#define PCIE_PHY_TRSV1_LVCC 0x19c |
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#define PCIE_PHY_TRSV2_EMP_LVL 0x204 |
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#define PCIE_PHY_TRSV2_RXCDR 0x22c |
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#define PCIE_PHY_TRSV2_LVCC 0x25c |
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#define PCIE_PHY_TRSV3_EMP_LVL 0x2c4 |
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#define PCIE_PHY_TRSV3_RXCDR 0x2ec |
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#define PCIE_PHY_TRSV3_LVCC 0x31c |
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static inline void exynos_elb_writel(struct exynos_pcie *pcie, u32 val, u32 reg) |
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{ |
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writel(val, pcie->elbi_base + reg); |
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} |
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static inline u32 exynos_elb_readl(struct exynos_pcie *pcie, u32 reg) |
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{ |
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return readl(pcie->elbi_base + reg); |
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} |
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static inline void exynos_phy_writel(struct exynos_pcie *pcie, u32 val, u32 reg) |
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{ |
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writel(val, pcie->phy_base + reg); |
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} |
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static inline u32 exynos_phy_readl(struct exynos_pcie *pcie, u32 reg) |
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{ |
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return readl(pcie->phy_base + reg); |
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} |
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static inline void exynos_blk_writel(struct exynos_pcie *pcie, u32 val, u32 reg) |
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{ |
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writel(val, pcie->block_base + reg); |
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} |
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static inline u32 exynos_blk_readl(struct exynos_pcie *pcie, u32 reg) |
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{ |
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return readl(pcie->block_base + reg); |
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} |
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static void exynos_pcie_sideband_dbi_w_mode(struct pcie_port *pp, bool on) |
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{ |
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u32 val; |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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if (on) { |
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
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val |= PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
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} else { |
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_AWMISC); |
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_AWMISC); |
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} |
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} |
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static void exynos_pcie_sideband_dbi_r_mode(struct pcie_port *pp, bool on) |
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{ |
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u32 val; |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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if (on) { |
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
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val |= PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
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} else { |
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val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_SLV_ARMISC); |
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val &= ~PCIE_ELBI_SLV_DBI_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_ELBI_SLV_ARMISC); |
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} |
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} |
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static void exynos_pcie_assert_core_reset(struct pcie_port *pp) |
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{ |
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u32 val; |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
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val &= ~PCIE_CORE_RESET_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
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exynos_elb_writel(exynos_pcie, 0, PCIE_PWR_RESET); |
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exynos_elb_writel(exynos_pcie, 0, PCIE_STICKY_RESET); |
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exynos_elb_writel(exynos_pcie, 0, PCIE_NONSTICKY_RESET); |
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} |
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static void exynos_pcie_deassert_core_reset(struct pcie_port *pp) |
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{ |
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u32 val; |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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val = exynos_elb_readl(exynos_pcie, PCIE_CORE_RESET); |
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val |= PCIE_CORE_RESET_ENABLE; |
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exynos_elb_writel(exynos_pcie, val, PCIE_CORE_RESET); |
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exynos_elb_writel(exynos_pcie, 1, PCIE_STICKY_RESET); |
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exynos_elb_writel(exynos_pcie, 1, PCIE_NONSTICKY_RESET); |
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exynos_elb_writel(exynos_pcie, 1, PCIE_APP_INIT_RESET); |
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exynos_elb_writel(exynos_pcie, 0, PCIE_APP_INIT_RESET); |
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_MAC_RESET); |
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} |
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static void exynos_pcie_assert_phy_reset(struct pcie_port *pp) |
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{ |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_MAC_RESET); |
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_GLOBAL_RESET); |
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} |
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static void exynos_pcie_deassert_phy_reset(struct pcie_port *pp) |
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{ |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_GLOBAL_RESET); |
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exynos_elb_writel(exynos_pcie, 1, PCIE_PWR_RESET); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_CMN_REG); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSVREG_RESET); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_TRSV_RESET); |
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} |
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static void exynos_pcie_init_phy(struct pcie_port *pp) |
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{ |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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/* DCC feedback control off */ |
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exynos_phy_writel(exynos_pcie, 0x29, PCIE_PHY_DCC_FEEDBACK); |
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/* set TX/RX impedance */ |
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exynos_phy_writel(exynos_pcie, 0xd5, PCIE_PHY_IMPEDANCE); |
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/* set 50Mhz PHY clock */ |
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exynos_phy_writel(exynos_pcie, 0x14, PCIE_PHY_PLL_DIV_0); |
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exynos_phy_writel(exynos_pcie, 0x12, PCIE_PHY_PLL_DIV_1); |
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/* set TX Differential output for lane 0 */ |
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exynos_phy_writel(exynos_pcie, 0x7f, PCIE_PHY_TRSV0_DRV_LVL); |
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/* set TX Pre-emphasis Level Control for lane 0 to minimum */ |
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exynos_phy_writel(exynos_pcie, 0x0, PCIE_PHY_TRSV0_EMP_LVL); |
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/* set RX clock and data recovery bandwidth */ |
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exynos_phy_writel(exynos_pcie, 0xe7, PCIE_PHY_PLL_BIAS); |
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV0_RXCDR); |
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV1_RXCDR); |
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV2_RXCDR); |
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exynos_phy_writel(exynos_pcie, 0x82, PCIE_PHY_TRSV3_RXCDR); |
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/* change TX Pre-emphasis Level Control for lanes */ |
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV0_EMP_LVL); |
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV1_EMP_LVL); |
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV2_EMP_LVL); |
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exynos_phy_writel(exynos_pcie, 0x39, PCIE_PHY_TRSV3_EMP_LVL); |
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/* set LVCC */ |
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exynos_phy_writel(exynos_pcie, 0x20, PCIE_PHY_TRSV0_LVCC); |
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV1_LVCC); |
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV2_LVCC); |
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exynos_phy_writel(exynos_pcie, 0xa0, PCIE_PHY_TRSV3_LVCC); |
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} |
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static void exynos_pcie_assert_reset(struct pcie_port *pp) |
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{ |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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if (exynos_pcie->reset_gpio >= 0) |
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devm_gpio_request_one(pp->dev, exynos_pcie->reset_gpio, |
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GPIOF_OUT_INIT_HIGH, "RESET"); |
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return; |
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} |
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static int exynos_pcie_establish_link(struct pcie_port *pp) |
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{ |
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u32 val; |
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int count = 0; |
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struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
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if (dw_pcie_link_up(pp)) { |
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dev_err(pp->dev, "Link already up\n"); |
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return 0; |
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} |
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/* assert reset signals */ |
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exynos_pcie_assert_core_reset(pp); |
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exynos_pcie_assert_phy_reset(pp); |
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/* de-assert phy reset */ |
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exynos_pcie_deassert_phy_reset(pp); |
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/* initialize phy */ |
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exynos_pcie_init_phy(pp); |
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/* pulse for common reset */ |
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exynos_blk_writel(exynos_pcie, 1, PCIE_PHY_COMMON_RESET); |
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udelay(500); |
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exynos_blk_writel(exynos_pcie, 0, PCIE_PHY_COMMON_RESET); |
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/* de-assert core reset */ |
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exynos_pcie_deassert_core_reset(pp); |
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/* setup root complex */ |
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dw_pcie_setup_rc(pp); |
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/* assert reset signal */ |
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exynos_pcie_assert_reset(pp); |
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/* assert LTSSM enable */ |
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exynos_elb_writel(exynos_pcie, PCIE_ELBI_LTSSM_ENABLE, |
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PCIE_APP_LTSSM_ENABLE); |
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|
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/* check if the link is up or not */ |
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while (!dw_pcie_link_up(pp)) { |
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mdelay(100); |
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count++; |
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if (count == 10) { |
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while (exynos_phy_readl(exynos_pcie, |
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PCIE_PHY_PLL_LOCKED) == 0) { |
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val = exynos_blk_readl(exynos_pcie, |
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PCIE_PHY_PLL_LOCKED); |
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dev_info(pp->dev, "PLL Locked: 0x%x\n", val); |
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} |
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dev_err(pp->dev, "PCIe Link Fail\n"); |
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return -EINVAL; |
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} |
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} |
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dev_info(pp->dev, "Link up\n"); |
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return 0; |
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} |
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|
||||
static void exynos_pcie_clear_irq_pulse(struct pcie_port *pp) |
||||
{ |
||||
u32 val; |
||||
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
||||
|
||||
val = exynos_elb_readl(exynos_pcie, PCIE_IRQ_PULSE); |
||||
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_PULSE); |
||||
return; |
||||
} |
||||
|
||||
static void exynos_pcie_enable_irq_pulse(struct pcie_port *pp) |
||||
{ |
||||
u32 val; |
||||
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
||||
|
||||
/* enable INTX interrupt */ |
||||
val = IRQ_INTA_ASSERT | IRQ_INTB_ASSERT | |
||||
IRQ_INTC_ASSERT | IRQ_INTD_ASSERT, |
||||
exynos_elb_writel(exynos_pcie, val, PCIE_IRQ_EN_PULSE); |
||||
return; |
||||
} |
||||
|
||||
static irqreturn_t exynos_pcie_irq_handler(int irq, void *arg) |
||||
{ |
||||
struct pcie_port *pp = arg; |
||||
|
||||
exynos_pcie_clear_irq_pulse(pp); |
||||
return IRQ_HANDLED; |
||||
} |
||||
|
||||
static void exynos_pcie_enable_interrupts(struct pcie_port *pp) |
||||
{ |
||||
exynos_pcie_enable_irq_pulse(pp); |
||||
return; |
||||
} |
||||
|
||||
static inline void exynos_pcie_readl_rc(struct pcie_port *pp, |
||||
void __iomem *dbi_base, u32 *val) |
||||
{ |
||||
exynos_pcie_sideband_dbi_r_mode(pp, true); |
||||
*val = readl(dbi_base); |
||||
exynos_pcie_sideband_dbi_r_mode(pp, false); |
||||
return; |
||||
} |
||||
|
||||
static inline void exynos_pcie_writel_rc(struct pcie_port *pp, |
||||
u32 val, void __iomem *dbi_base) |
||||
{ |
||||
exynos_pcie_sideband_dbi_w_mode(pp, true); |
||||
writel(val, dbi_base); |
||||
exynos_pcie_sideband_dbi_w_mode(pp, false); |
||||
return; |
||||
} |
||||
|
||||
static int exynos_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, |
||||
u32 *val) |
||||
{ |
||||
int ret; |
||||
|
||||
exynos_pcie_sideband_dbi_r_mode(pp, true); |
||||
ret = cfg_read(pp->dbi_base + (where & ~0x3), where, size, val); |
||||
exynos_pcie_sideband_dbi_r_mode(pp, false); |
||||
return ret; |
||||
} |
||||
|
||||
static int exynos_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, |
||||
u32 val) |
||||
{ |
||||
int ret; |
||||
|
||||
exynos_pcie_sideband_dbi_w_mode(pp, true); |
||||
ret = cfg_write(pp->dbi_base + (where & ~0x3), where, size, val); |
||||
exynos_pcie_sideband_dbi_w_mode(pp, false); |
||||
return ret; |
||||
} |
||||
|
||||
static int exynos_pcie_link_up(struct pcie_port *pp) |
||||
{ |
||||
struct exynos_pcie *exynos_pcie = to_exynos_pcie(pp); |
||||
u32 val = exynos_elb_readl(exynos_pcie, PCIE_ELBI_RDLH_LINKUP); |
||||
|
||||
if (val == PCIE_ELBI_LTSSM_ENABLE) |
||||
return 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void exynos_pcie_host_init(struct pcie_port *pp) |
||||
{ |
||||
exynos_pcie_establish_link(pp); |
||||
exynos_pcie_enable_interrupts(pp); |
||||
} |
||||
|
||||
static struct pcie_host_ops exynos_pcie_host_ops = { |
||||
.readl_rc = exynos_pcie_readl_rc, |
||||
.writel_rc = exynos_pcie_writel_rc, |
||||
.rd_own_conf = exynos_pcie_rd_own_conf, |
||||
.wr_own_conf = exynos_pcie_wr_own_conf, |
||||
.link_up = exynos_pcie_link_up, |
||||
.host_init = exynos_pcie_host_init, |
||||
}; |
||||
|
||||
static int add_pcie_port(struct pcie_port *pp, struct platform_device *pdev) |
||||
{ |
||||
int ret; |
||||
|
||||
pp->irq = platform_get_irq(pdev, 1); |
||||
if (!pp->irq) { |
||||
dev_err(&pdev->dev, "failed to get irq\n"); |
||||
return -ENODEV; |
||||
} |
||||
ret = devm_request_irq(&pdev->dev, pp->irq, exynos_pcie_irq_handler, |
||||
IRQF_SHARED, "exynos-pcie", pp); |
||||
if (ret) { |
||||
dev_err(&pdev->dev, "failed to request irq\n"); |
||||
return ret; |
||||
} |
||||
|
||||
pp->root_bus_nr = -1; |
||||
pp->ops = &exynos_pcie_host_ops; |
||||
|
||||
spin_lock_init(&pp->conf_lock); |
||||
ret = dw_pcie_host_init(pp); |
||||
if (ret) { |
||||
dev_err(&pdev->dev, "failed to initialize host\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int __init exynos_pcie_probe(struct platform_device *pdev) |
||||
{ |
||||
struct exynos_pcie *exynos_pcie; |
||||
struct pcie_port *pp; |
||||
struct device_node *np = pdev->dev.of_node; |
||||
struct resource *elbi_base; |
||||
struct resource *phy_base; |
||||
struct resource *block_base; |
||||
int ret; |
||||
|
||||
exynos_pcie = devm_kzalloc(&pdev->dev, sizeof(*exynos_pcie), |
||||
GFP_KERNEL); |
||||
if (!exynos_pcie) { |
||||
dev_err(&pdev->dev, "no memory for exynos pcie\n"); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
pp = &exynos_pcie->pp; |
||||
|
||||
pp->dev = &pdev->dev; |
||||
|
||||
exynos_pcie->reset_gpio = of_get_named_gpio(np, "reset-gpio", 0); |
||||
|
||||
exynos_pcie->clk = devm_clk_get(&pdev->dev, "pcie"); |
||||
if (IS_ERR(exynos_pcie->clk)) { |
||||
dev_err(&pdev->dev, "Failed to get pcie rc clock\n"); |
||||
return PTR_ERR(exynos_pcie->clk); |
||||
} |
||||
ret = clk_prepare_enable(exynos_pcie->clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
exynos_pcie->bus_clk = devm_clk_get(&pdev->dev, "pcie_bus"); |
||||
if (IS_ERR(exynos_pcie->bus_clk)) { |
||||
dev_err(&pdev->dev, "Failed to get pcie bus clock\n"); |
||||
ret = PTR_ERR(exynos_pcie->bus_clk); |
||||
goto fail_clk; |
||||
} |
||||
ret = clk_prepare_enable(exynos_pcie->bus_clk); |
||||
if (ret) |
||||
goto fail_clk; |
||||
|
||||
elbi_base = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
exynos_pcie->elbi_base = devm_ioremap_resource(&pdev->dev, elbi_base); |
||||
if (IS_ERR(exynos_pcie->elbi_base)) |
||||
return PTR_ERR(exynos_pcie->elbi_base); |
||||
|
||||
phy_base = platform_get_resource(pdev, IORESOURCE_MEM, 1); |
||||
exynos_pcie->phy_base = devm_ioremap_resource(&pdev->dev, phy_base); |
||||
if (IS_ERR(exynos_pcie->phy_base)) |
||||
return PTR_ERR(exynos_pcie->phy_base); |
||||
|
||||
block_base = platform_get_resource(pdev, IORESOURCE_MEM, 2); |
||||
exynos_pcie->block_base = devm_ioremap_resource(&pdev->dev, block_base); |
||||
if (IS_ERR(exynos_pcie->block_base)) |
||||
return PTR_ERR(exynos_pcie->block_base); |
||||
|
||||
ret = add_pcie_port(pp, pdev); |
||||
if (ret < 0) |
||||
goto fail_bus_clk; |
||||
|
||||
platform_set_drvdata(pdev, exynos_pcie); |
||||
return 0; |
||||
|
||||
fail_bus_clk: |
||||
clk_disable_unprepare(exynos_pcie->bus_clk); |
||||
fail_clk: |
||||
clk_disable_unprepare(exynos_pcie->clk); |
||||
return ret; |
||||
} |
||||
|
||||
static int __exit exynos_pcie_remove(struct platform_device *pdev) |
||||
{ |
||||
struct exynos_pcie *exynos_pcie = platform_get_drvdata(pdev); |
||||
|
||||
clk_disable_unprepare(exynos_pcie->bus_clk); |
||||
clk_disable_unprepare(exynos_pcie->clk); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct of_device_id exynos_pcie_of_match[] = { |
||||
{ .compatible = "samsung,exynos5440-pcie", }, |
||||
{}, |
||||
}; |
||||
MODULE_DEVICE_TABLE(of, exynos_pcie_of_match); |
||||
|
||||
static struct platform_driver exynos_pcie_driver = { |
||||
.remove = __exit_p(exynos_pcie_remove), |
||||
.driver = { |
||||
.name = "exynos-pcie", |
||||
.owner = THIS_MODULE, |
||||
.of_match_table = of_match_ptr(exynos_pcie_of_match), |
||||
}, |
||||
}; |
||||
|
||||
/* Exynos PCIe driver does not allow module unload */ |
||||
|
||||
static int __init pcie_init(void) |
||||
{ |
||||
return platform_driver_probe(&exynos_pcie_driver, exynos_pcie_probe); |
||||
} |
||||
subsys_initcall(pcie_init); |
||||
|
||||
MODULE_AUTHOR("Jingoo Han <jg1.han@samsung.com>"); |
||||
MODULE_DESCRIPTION("Samsung PCIe host controller driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,65 @@ |
||||
/*
|
||||
* Synopsys Designware PCIe host controller driver |
||||
* |
||||
* Copyright (C) 2013 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com
|
||||
* |
||||
* Author: Jingoo Han <jg1.han@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
struct pcie_port_info { |
||||
u32 cfg0_size; |
||||
u32 cfg1_size; |
||||
u32 io_size; |
||||
u32 mem_size; |
||||
phys_addr_t io_bus_addr; |
||||
phys_addr_t mem_bus_addr; |
||||
}; |
||||
|
||||
struct pcie_port { |
||||
struct device *dev; |
||||
u8 root_bus_nr; |
||||
void __iomem *dbi_base; |
||||
u64 cfg0_base; |
||||
void __iomem *va_cfg0_base; |
||||
u64 cfg1_base; |
||||
void __iomem *va_cfg1_base; |
||||
u64 io_base; |
||||
u64 mem_base; |
||||
spinlock_t conf_lock; |
||||
struct resource cfg; |
||||
struct resource io; |
||||
struct resource mem; |
||||
struct pcie_port_info config; |
||||
int irq; |
||||
u32 lanes; |
||||
struct pcie_host_ops *ops; |
||||
}; |
||||
|
||||
struct pcie_host_ops { |
||||
void (*readl_rc)(struct pcie_port *pp, |
||||
void __iomem *dbi_base, u32 *val); |
||||
void (*writel_rc)(struct pcie_port *pp, |
||||
u32 val, void __iomem *dbi_base); |
||||
int (*rd_own_conf)(struct pcie_port *pp, int where, int size, u32 *val); |
||||
int (*wr_own_conf)(struct pcie_port *pp, int where, int size, u32 val); |
||||
int (*link_up)(struct pcie_port *pp); |
||||
void (*host_init)(struct pcie_port *pp); |
||||
}; |
||||
|
||||
extern unsigned long global_io_offset; |
||||
|
||||
int cfg_read(void __iomem *addr, int where, int size, u32 *val); |
||||
int cfg_write(void __iomem *addr, int where, int size, u32 val); |
||||
int dw_pcie_wr_own_conf(struct pcie_port *pp, int where, int size, u32 val); |
||||
int dw_pcie_rd_own_conf(struct pcie_port *pp, int where, int size, u32 *val); |
||||
int dw_pcie_link_up(struct pcie_port *pp); |
||||
void dw_pcie_setup_rc(struct pcie_port *pp); |
||||
int dw_pcie_host_init(struct pcie_port *pp); |
||||
int dw_pcie_setup(int nr, struct pci_sys_data *sys); |
||||
struct pci_bus *dw_pcie_scan_bus(int nr, struct pci_sys_data *sys); |
||||
int dw_pcie_map_irq(const struct pci_dev *dev, u8 slot, u8 pin); |
||||
Loading…
Reference in new issue