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@ -206,6 +206,97 @@ enum rk818_reg { |
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#define RK818_USB_ILMIN_2000MA 0x7 |
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#define RK818_USB_CHG_SD_VSEL_MASK 0x70 |
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/* RK805 */ |
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enum rk805_reg { |
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RK805_ID_DCDC1, |
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RK805_ID_DCDC2, |
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RK805_ID_DCDC3, |
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RK805_ID_DCDC4, |
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RK805_ID_LDO1, |
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RK805_ID_LDO2, |
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RK805_ID_LDO3, |
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}; |
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/* CONFIG REGISTER */ |
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#define RK805_VB_MON_REG 0x21 |
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#define RK805_THERMAL_REG 0x22 |
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/* POWER CHANNELS ENABLE REGISTER */ |
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#define RK805_DCDC_EN_REG 0x23 |
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#define RK805_SLP_DCDC_EN_REG 0x25 |
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#define RK805_SLP_LDO_EN_REG 0x26 |
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#define RK805_LDO_EN_REG 0x27 |
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/* BUCK AND LDO CONFIG REGISTER */ |
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#define RK805_BUCK_LDO_SLP_LP_EN_REG 0x2A |
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#define RK805_BUCK1_CONFIG_REG 0x2E |
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#define RK805_BUCK1_ON_VSEL_REG 0x2F |
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#define RK805_BUCK1_SLP_VSEL_REG 0x30 |
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#define RK805_BUCK2_CONFIG_REG 0x32 |
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#define RK805_BUCK2_ON_VSEL_REG 0x33 |
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#define RK805_BUCK2_SLP_VSEL_REG 0x34 |
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#define RK805_BUCK3_CONFIG_REG 0x36 |
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#define RK805_BUCK4_CONFIG_REG 0x37 |
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#define RK805_BUCK4_ON_VSEL_REG 0x38 |
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#define RK805_BUCK4_SLP_VSEL_REG 0x39 |
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#define RK805_LDO1_ON_VSEL_REG 0x3B |
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#define RK805_LDO1_SLP_VSEL_REG 0x3C |
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#define RK805_LDO2_ON_VSEL_REG 0x3D |
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#define RK805_LDO2_SLP_VSEL_REG 0x3E |
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#define RK805_LDO3_ON_VSEL_REG 0x3F |
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#define RK805_LDO3_SLP_VSEL_REG 0x40 |
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/* INTERRUPT REGISTER */ |
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#define RK805_PWRON_LP_INT_TIME_REG 0x47 |
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#define RK805_PWRON_DB_REG 0x48 |
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#define RK805_DEV_CTRL_REG 0x4B |
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#define RK805_INT_STS_REG 0x4C |
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#define RK805_INT_STS_MSK_REG 0x4D |
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#define RK805_GPIO_IO_POL_REG 0x50 |
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#define RK805_OUT_REG 0x52 |
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#define RK805_ON_SOURCE_REG 0xAE |
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#define RK805_OFF_SOURCE_REG 0xAF |
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#define RK805_NUM_REGULATORS 7 |
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#define RK805_PWRON_FALL_RISE_INT_EN 0x0 |
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#define RK805_PWRON_FALL_RISE_INT_MSK 0x81 |
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/* RK805 IRQ Definitions */ |
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#define RK805_IRQ_PWRON_RISE 0 |
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#define RK805_IRQ_VB_LOW 1 |
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#define RK805_IRQ_PWRON 2 |
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#define RK805_IRQ_PWRON_LP 3 |
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#define RK805_IRQ_HOTDIE 4 |
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#define RK805_IRQ_RTC_ALARM 5 |
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#define RK805_IRQ_RTC_PERIOD 6 |
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#define RK805_IRQ_PWRON_FALL 7 |
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#define RK805_IRQ_PWRON_RISE_MSK BIT(0) |
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#define RK805_IRQ_VB_LOW_MSK BIT(1) |
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#define RK805_IRQ_PWRON_MSK BIT(2) |
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#define RK805_IRQ_PWRON_LP_MSK BIT(3) |
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#define RK805_IRQ_HOTDIE_MSK BIT(4) |
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#define RK805_IRQ_RTC_ALARM_MSK BIT(5) |
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#define RK805_IRQ_RTC_PERIOD_MSK BIT(6) |
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#define RK805_IRQ_PWRON_FALL_MSK BIT(7) |
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#define RK805_PWR_RISE_INT_STATUS BIT(0) |
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#define RK805_VB_LOW_INT_STATUS BIT(1) |
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#define RK805_PWRON_INT_STATUS BIT(2) |
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#define RK805_PWRON_LP_INT_STATUS BIT(3) |
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#define RK805_HOTDIE_INT_STATUS BIT(4) |
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#define RK805_ALARM_INT_STATUS BIT(5) |
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#define RK805_PERIOD_INT_STATUS BIT(6) |
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#define RK805_PWR_FALL_INT_STATUS BIT(7) |
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#define RK805_BUCK1_2_ILMAX_MASK (3 << 6) |
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#define RK805_BUCK3_4_ILMAX_MASK (3 << 3) |
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#define RK805_RTC_PERIOD_INT_MASK (1 << 6) |
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#define RK805_RTC_ALARM_INT_MASK (1 << 5) |
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#define RK805_INT_ALARM_EN (1 << 3) |
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#define RK805_INT_TIMER_EN (1 << 2) |
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/* RK808 IRQ Definitions */ |
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#define RK808_IRQ_VOUT_LO 0 |
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#define RK808_IRQ_VB_LO 1 |
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@ -298,7 +389,14 @@ enum rk818_reg { |
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#define VOUT_LO_INT BIT(0) |
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#define CLK32KOUT2_EN BIT(0) |
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#define TEMP115C 0x0c |
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#define TEMP_HOTDIE_MSK 0x0c |
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#define SLP_SD_MSK (0x3 << 2) |
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#define SHUTDOWN_FUN (0x2 << 2) |
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#define SLEEP_FUN (0x1 << 2) |
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#define RK8XX_ID_MSK 0xfff0 |
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#define FPWM_MODE BIT(7) |
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enum { |
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BUCK_ILMIN_50MA, |
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BUCK_ILMIN_100MA, |
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@ -322,6 +420,28 @@ enum { |
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}; |
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enum { |
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RK805_BUCK1_2_ILMAX_2500MA, |
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RK805_BUCK1_2_ILMAX_3000MA, |
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RK805_BUCK1_2_ILMAX_3500MA, |
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RK805_BUCK1_2_ILMAX_4000MA, |
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}; |
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enum { |
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RK805_BUCK3_ILMAX_1500MA, |
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RK805_BUCK3_ILMAX_2000MA, |
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RK805_BUCK3_ILMAX_2500MA, |
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RK805_BUCK3_ILMAX_3000MA, |
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}; |
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enum { |
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RK805_BUCK4_ILMAX_2000MA, |
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RK805_BUCK4_ILMAX_2500MA, |
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RK805_BUCK4_ILMAX_3000MA, |
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RK805_BUCK4_ILMAX_3500MA, |
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}; |
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enum { |
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RK805_ID = 0x8050, |
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RK808_ID = 0x0000, |
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RK818_ID = 0x8181, |
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}; |
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