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ARM: tegra: modify ULPI reset GPIO properties

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1. All Tegra20 ULPI reset GPIO DT properties are modified to indicate active
low nature of the GPIO.
2. Placed USB PHY DT node immediately below the EHCI controller DT nodes
and corrected reg value in the name of USB PHY DT node.

Signed-off-by: Venu Byravarasu <vbyravarasu@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
tirimbino
Venu Byravarasu 12 years ago committed by Stephen Warren
parent d400f209b4
commit 9dffe3be3f
6 changed files with 30 additions and 26 deletions
Show all changes Ignore whitespace when comparing lines Ignore changes in amount of whitespace Ignore changes in whitespace at EOL
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  1. 6
      arch/arm/boot/dts/tegra20-colibri-512.dtsi
  2. 10
      arch/arm/boot/dts/tegra20-harmony.dts
  3. 10
      arch/arm/boot/dts/tegra20-paz00.dts
  4. 10
      arch/arm/boot/dts/tegra20-seaboard.dts
  5. 10
      arch/arm/boot/dts/tegra20-trimslice.dts
  6. 10
      arch/arm/boot/dts/tegra20-ventana.dts

6
arch/arm/boot/dts/tegra20-colibri-512.dtsi
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@ -449,7 +449,11 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
sdhci@c8000600 {

10
arch/arm/boot/dts/tegra20-harmony.dts
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@ -430,15 +430,15 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb@c5008000 {
status = "okay";
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb@c5008000 {
status = "okay";
};
sdhci@c8000200 {

10
arch/arm/boot/dts/tegra20-paz00.dts
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@ -429,15 +429,15 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
};
usb@c5008000 {
status = "okay";
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {

10
arch/arm/boot/dts/tegra20-seaboard.dts
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@ -571,15 +571,15 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb@c5008000 {
status = "okay";
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {

10
arch/arm/boot/dts/tegra20-trimslice.dts
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@ -316,15 +316,15 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
};
usb@c5008000 {
status = "okay";
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 168 1>; /* gpio PV0, active low */
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 168 0>; /* gpio PV0 */
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {

10
arch/arm/boot/dts/tegra20-ventana.dts
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@ -507,15 +507,15 @@
usb@c5004000 {
status = "okay";
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb@c5008000 {
status = "okay";
usb-phy@c5004000 {
nvidia,phy-reset-gpio = <&gpio 169 1>; /* gpio PV1, active low */
};
usb-phy@c5004400 {
nvidia,phy-reset-gpio = <&gpio 169 0>; /* gpio PV1 */
usb@c5008000 {
status = "okay";
};
sdhci@c8000000 {

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