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@ -84,11 +84,6 @@ struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev) |
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return pi; |
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} |
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u32 sumo_get_xclk(struct radeon_device *rdev) |
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{ |
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return rdev->clock.spll.reference_freq; |
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} |
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static void sumo_gfx_clockgating_enable(struct radeon_device *rdev, bool enable) |
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{ |
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if (enable) |
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@ -124,7 +119,7 @@ static void sumo_mg_clockgating_enable(struct radeon_device *rdev, bool enable) |
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static void sumo_program_git(struct radeon_device *rdev) |
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{ |
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u32 p, u; |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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r600_calculate_u_and_p(SUMO_GICST_DFLT, |
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xclk, 16, &p, &u); |
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@ -135,7 +130,7 @@ static void sumo_program_git(struct radeon_device *rdev) |
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static void sumo_program_grsd(struct radeon_device *rdev) |
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{ |
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u32 p, u; |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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u32 grs = 256 * 25 / 100; |
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r600_calculate_u_and_p(1, xclk, 14, &p, &u); |
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@ -155,7 +150,7 @@ static void sumo_gfx_powergating_initialize(struct radeon_device *rdev) |
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u32 p, u; |
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u32 p_c, p_p, d_p; |
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u32 r_t, i_t; |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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if (rdev->family == CHIP_PALM) { |
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p_c = 4; |
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@ -319,7 +314,7 @@ static void sumo_calculate_bsp(struct radeon_device *rdev, |
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u32 high_clk) |
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{ |
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struct sumo_power_info *pi = sumo_get_pi(rdev); |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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pi->pasi = 65535 * 100 / high_clk; |
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pi->asi = 65535 * 100 / high_clk; |
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@ -466,7 +461,7 @@ void sumo_clear_vc(struct radeon_device *rdev) |
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void sumo_program_sstp(struct radeon_device *rdev) |
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{ |
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u32 p, u; |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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r600_calculate_u_and_p(SUMO_SST_DFLT, |
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xclk, 16, &p, &u); |
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@ -909,7 +904,7 @@ static void sumo_start_am(struct radeon_device *rdev) |
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static void sumo_program_ttp(struct radeon_device *rdev) |
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{ |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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u32 p, u; |
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u32 cg_sclk_dpm_ctrl_5 = RREG32(CG_SCLK_DPM_CTRL_5); |
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@ -955,7 +950,7 @@ static void sumo_program_dc_hto(struct radeon_device *rdev) |
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{ |
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u32 cg_sclk_dpm_ctrl_4 = RREG32(CG_SCLK_DPM_CTRL_4); |
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u32 p, u; |
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u32 xclk = sumo_get_xclk(rdev); |
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u32 xclk = radeon_get_xclk(rdev); |
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r600_calculate_u_and_p(100000, |
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xclk, 14, &p, &u); |
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