-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iQIcBAABAgAGBQJS4dWNAAoJEI9vqH3mFV2sargP/RCdVvdJm3TxYcNYoKAw6kTs wn1AWQ1vnu77YIoG2YamWytakahvB5v4Elm5UbHc49eCIFb/+wJpvxLNKbAtY0EP bRllFETalWnPnZO0R0tTvEikpDfzM7/OGYCjuOmTeyata6/KOxVsusTjvar28NPA gVp9BwHKZyk5NORkvW3RBRbfga9slUXqbg4rPhD3gFxLpe8aGuO6T6HazBfRadQM pI0zq2VE59LSEyuZrreHiq5EYvmp+eBFR8bJhQp1lnpKc4lMJm5JKYPY+jlPPtu0 bPYLexjb42Gz2KbDtqLqTnd6GEPj50RS15tr9BTX9n3uCd0sIBO46K5FXVy+ALxr DXbyU6R1miZ01Il0A2IuC2j1cVdXb7nSytP35lLRQ9WCXua4HwQO0LL9KPAf9N0X WKlNPEkOr9XR9lO/1JcYVZgsygF/hHGgImf5AEfTVdtWpAj3bhMBhqFuKo0/h6vr 7PwQCTaiL2Hks+d8YS2VyrQy3DMg48MbYmfdriJQFKKzhdyHEhvlnawP5uoIVfAC s43cvj6EsbUdRULf5qKDupQFJpM15qpmYiLizHFIfUTiTQGI0WMaA76rZMqZ2AsQ z0q2edzUV8nBQFdR74eKKPF1QJyXihiaXzug+SZqPdvXKfjPrF+5eZ7/EvuaEBZy qS7PIt5nkTeZ4stP/SWV =JT1d -----END PGP SIGNATURE----- Merge tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux Pull Xtensa patches from Chris Zankel: "The major changes are adding support for SMP for Xtensa, fixing and cleaning up the ISS (simulator) network driver, and better support for device trees" * tag 'xtensa-next-20140123' of git://github.com/czankel/xtensa-linux: (40 commits) xtensa: implement ndelay xtensa: clean up udelay xtensa: enable HAVE_PERF_EVENTS xtensa: remap io area defined in device tree xtensa: support default device tree buses xtensa: initialize device tree clock sources xtensa: xtfpga: fix definitions of platform devices xtensa: standardize devicetree cpu compatible strings xtensa: avoid duplicate of IO range definitions xtensa: fix ATOMCTL register documentation xtensa: Enable irqs after cpu is set online xtensa: ISS: raise network polling rate to 10 times/sec xtensa: remove unused XTENSA_ISS_NETWORK Kconfig parameter xtensa: ISS: avoid simple_strtoul usage xtensa: Switch to sched_clock_register() xtensa: implement CPU hotplug xtensa: add SMP support xtensa: add MX irqchip xtensa: clear timer IRQ unconditionally in its handler xtensa: clean up do_interrupt/do_IRQ ...tirimbino
Linus Torvalds
11 years ago
commit
9b83d851a2
@ -0,0 +1,147 @@ |
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/*
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* Atomic futex routines |
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* |
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* Based on the PowerPC implementataion |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* Copyright (C) 2013 TangoTec Ltd. |
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* |
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* Baruch Siach <baruch@tkos.co.il> |
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*/ |
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#ifndef _ASM_XTENSA_FUTEX_H |
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#define _ASM_XTENSA_FUTEX_H |
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#ifdef __KERNEL__ |
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#include <linux/futex.h> |
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#include <linux/uaccess.h> |
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#include <linux/errno.h> |
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#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg) \ |
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__asm__ __volatile( \
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"1: l32i %0, %2, 0\n" \
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insn "\n" \
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" wsr %0, scompare1\n" \
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"2: s32c1i %1, %2, 0\n" \
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" bne %1, %0, 1b\n" \
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" movi %1, 0\n" \
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"3:\n" \
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" .section .fixup,\"ax\"\n" \
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" .align 4\n" \
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"4: .long 3b\n" \
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"5: l32r %0, 4b\n" \
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" movi %1, %3\n" \
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" jx %0\n" \
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" .previous\n" \
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" .section __ex_table,\"a\"\n" \
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" .long 1b,5b,2b,5b\n" \
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" .previous\n" \
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: "=&r" (oldval), "=&r" (ret) \
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: "r" (uaddr), "I" (-EFAULT), "r" (oparg) \
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: "memory") |
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static inline int futex_atomic_op_inuser(int encoded_op, u32 __user *uaddr) |
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{ |
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int op = (encoded_op >> 28) & 7; |
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int cmp = (encoded_op >> 24) & 15; |
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int oparg = (encoded_op << 8) >> 20; |
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int cmparg = (encoded_op << 20) >> 20; |
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int oldval = 0, ret; |
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if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28)) |
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oparg = 1 << oparg; |
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
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return -EFAULT; |
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#if !XCHAL_HAVE_S32C1I |
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return -ENOSYS; |
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#endif |
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pagefault_disable(); |
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switch (op) { |
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case FUTEX_OP_SET: |
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__futex_atomic_op("mov %1, %4", ret, oldval, uaddr, oparg); |
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break; |
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case FUTEX_OP_ADD: |
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__futex_atomic_op("add %1, %0, %4", ret, oldval, uaddr, |
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oparg); |
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break; |
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case FUTEX_OP_OR: |
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__futex_atomic_op("or %1, %0, %4", ret, oldval, uaddr, |
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oparg); |
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break; |
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case FUTEX_OP_ANDN: |
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__futex_atomic_op("and %1, %0, %4", ret, oldval, uaddr, |
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~oparg); |
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break; |
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case FUTEX_OP_XOR: |
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__futex_atomic_op("xor %1, %0, %4", ret, oldval, uaddr, |
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oparg); |
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break; |
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default: |
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ret = -ENOSYS; |
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} |
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pagefault_enable(); |
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if (ret) |
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return ret; |
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switch (cmp) { |
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case FUTEX_OP_CMP_EQ: return (oldval == cmparg); |
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case FUTEX_OP_CMP_NE: return (oldval != cmparg); |
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case FUTEX_OP_CMP_LT: return (oldval < cmparg); |
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case FUTEX_OP_CMP_GE: return (oldval >= cmparg); |
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case FUTEX_OP_CMP_LE: return (oldval <= cmparg); |
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case FUTEX_OP_CMP_GT: return (oldval > cmparg); |
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} |
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return -ENOSYS; |
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} |
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static inline int |
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futex_atomic_cmpxchg_inatomic(u32 *uval, u32 __user *uaddr, |
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u32 oldval, u32 newval) |
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{ |
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int ret = 0; |
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u32 prev; |
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if (!access_ok(VERIFY_WRITE, uaddr, sizeof(u32))) |
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return -EFAULT; |
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#if !XCHAL_HAVE_S32C1I |
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return -ENOSYS; |
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#endif |
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__asm__ __volatile__ ( |
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" # futex_atomic_cmpxchg_inatomic\n" |
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"1: l32i %1, %3, 0\n" |
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" mov %0, %5\n" |
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" wsr %1, scompare1\n" |
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"2: s32c1i %0, %3, 0\n" |
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"3:\n" |
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" .section .fixup,\"ax\"\n" |
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" .align 4\n" |
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"4: .long 3b\n" |
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"5: l32r %1, 4b\n" |
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" movi %0, %6\n" |
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" jx %1\n" |
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" .previous\n" |
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" .section __ex_table,\"a\"\n" |
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" .long 1b,5b,2b,5b\n" |
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" .previous\n" |
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: "+r" (ret), "=&r" (prev), "+m" (*uaddr) |
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: "r" (uaddr), "r" (oldval), "r" (newval), "I" (-EFAULT) |
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: "memory"); |
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*uval = prev; |
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return ret; |
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} |
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#endif /* __KERNEL__ */ |
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#endif /* _ASM_XTENSA_FUTEX_H */ |
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@ -0,0 +1,46 @@ |
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/*
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* Xtensa MX interrupt distributor |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2008 - 2013 Tensilica Inc. |
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*/ |
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#ifndef _XTENSA_MXREGS_H |
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#define _XTENSA_MXREGS_H |
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/*
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* RER/WER at, as Read/write external register |
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* at: value |
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* as: address |
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* |
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* Address Value |
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* 00nn 0...0p..p Interrupt Routing, route IRQ n to processor p |
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* 01pp 0...0d..d 16 bits (d) 'ored' as single IPI to processor p |
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* 0180 0...0m..m Clear enable specified by mask (m) |
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* 0184 0...0m..m Set enable specified by mask (m) |
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* 0190 0...0x..x 8-bit IPI partition register |
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* VVVVVVVVPPPPUUUUUUUUUUUUUUUUU |
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* V (10-bit) Release/Version |
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* P ( 4-bit) Number of cores - 1 |
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* U (18-bit) ID |
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* 01a0 i.......i 32-bit ConfigID |
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* 0200 0...0m..m RunStall core 'n' |
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* 0220 c Cache coherency enabled |
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*/ |
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#define MIROUT(irq) (0x000 + (irq)) |
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#define MIPICAUSE(cpu) (0x100 + (cpu)) |
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#define MIPISET(cause) (0x140 + (cause)) |
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#define MIENG 0x180 |
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#define MIENGSET 0x184 |
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#define MIASG 0x188 /* Read Global Assert Register */ |
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#define MIASGSET 0x18c /* Set Global Addert Regiter */ |
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#define MIPIPART 0x190 |
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#define SYSCFGID 0x1a0 |
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#define MPSCORE 0x200 |
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#define CCON 0x220 |
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#endif /* _XTENSA_MXREGS_H */ |
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@ -0,0 +1,4 @@ |
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#ifndef __ASM_XTENSA_PERF_EVENT_H |
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#define __ASM_XTENSA_PERF_EVENT_H |
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#endif /* __ASM_XTENSA_PERF_EVENT_H */ |
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@ -1,27 +1,43 @@ |
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/*
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* include/asm-xtensa/smp.h |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2001 - 2005 Tensilica Inc. |
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* Copyright (C) 2001 - 2013 Tensilica Inc. |
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*/ |
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#ifndef _XTENSA_SMP_H |
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#define _XTENSA_SMP_H |
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extern struct xtensa_cpuinfo boot_cpu_data; |
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#ifdef CONFIG_SMP |
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#define cpu_data (&boot_cpu_data) |
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#define current_cpu_data boot_cpu_data |
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#define raw_smp_processor_id() (current_thread_info()->cpu) |
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#define cpu_logical_map(cpu) (cpu) |
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struct xtensa_cpuinfo { |
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unsigned long *pgd_cache; |
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unsigned long *pte_cache; |
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unsigned long pgtable_cache_sz; |
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struct start_info { |
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unsigned long stack; |
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}; |
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extern struct start_info start_info; |
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#define cpu_logical_map(cpu) (cpu) |
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struct cpumask; |
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void arch_send_call_function_ipi_mask(const struct cpumask *mask); |
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void arch_send_call_function_single_ipi(int cpu); |
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void smp_init_cpus(void); |
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void secondary_init_irq(void); |
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void ipi_init(void); |
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struct seq_file; |
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void show_ipi_list(struct seq_file *p, int prec); |
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#ifdef CONFIG_HOTPLUG_CPU |
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void __cpu_die(unsigned int cpu); |
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int __cpu_disable(void); |
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void cpu_die(void); |
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void cpu_restart(void); |
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#endif /* CONFIG_HOTPLUG_CPU */ |
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#endif /* CONFIG_SMP */ |
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#endif /* _XTENSA_SMP_H */ |
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@ -0,0 +1,20 @@ |
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#ifndef __ASM_SPINLOCK_TYPES_H |
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#define __ASM_SPINLOCK_TYPES_H |
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#ifndef __LINUX_SPINLOCK_TYPES_H |
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# error "please don't include this file directly" |
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#endif |
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typedef struct { |
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volatile unsigned int slock; |
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} arch_spinlock_t; |
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#define __ARCH_SPIN_LOCK_UNLOCKED { 0 } |
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typedef struct { |
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volatile unsigned int lock; |
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} arch_rwlock_t; |
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#define __ARCH_RW_LOCK_UNLOCKED { 0 } |
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#endif |
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@ -0,0 +1,85 @@ |
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/* |
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* Xtensa Secondary Processors startup code. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2001 - 2013 Tensilica Inc. |
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* |
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* Joe Taylor <joe@tensilica.com>
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* Chris Zankel <chris@zankel.net>
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* Marc Gauthier <marc@tensilica.com, marc@alumni.uwaterloo.ca>
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* Pete Delaney <piet@tensilica.com>
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*/ |
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#include <linux/linkage.h> |
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#include <asm/cacheasm.h> |
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#include <asm/initialize_mmu.h> |
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#include <asm/mxregs.h> |
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#include <asm/regs.h> |
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.section .SecondaryResetVector.text, "ax" |
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ENTRY(_SecondaryResetVector) |
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_j _SetupOCD |
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.begin no-absolute-literals |
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.literal_position |
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_SetupOCD: |
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/* |
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* Initialize WB, WS, and clear PS.EXCM (to allow loop instructions). |
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* Set Interrupt Level just below XCHAL_DEBUGLEVEL to allow |
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* xt-gdb to single step via DEBUG exceptions received directly |
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* by ocd. |
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*/ |
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movi a1, 1 |
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movi a0, 0 |
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wsr a1, windowstart |
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wsr a0, windowbase |
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rsync |
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movi a1, LOCKLEVEL |
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wsr a1, ps |
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rsync |
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_SetupMMU: |
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Offset = _SetupMMU - _SecondaryResetVector |
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#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX |
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initialize_mmu |
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#endif |
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/* |
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* Start Secondary Processors with NULL pointer to boot params. |
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*/ |
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movi a2, 0 # a2 == NULL |
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movi a3, _startup |
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jx a3 |
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.end no-absolute-literals |
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.section .SecondaryResetVector.remapped_text, "ax" |
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.global _RemappedSecondaryResetVector
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.org 0 # Need to do org before literals |
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_RemappedSecondaryResetVector: |
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.begin no-absolute-literals |
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.literal_position |
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_j _RemappedSetupMMU |
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. = _RemappedSecondaryResetVector + Offset |
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_RemappedSetupMMU: |
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#ifdef CONFIG_INITIALIZE_XTENSA_MMU_INSIDE_VMLINUX |
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initialize_mmu |
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#endif |
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.end no-absolute-literals |
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@ -0,0 +1,592 @@ |
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/*
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* Xtensa SMP support functions. |
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* |
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* This file is subject to the terms and conditions of the GNU General Public |
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* License. See the file "COPYING" in the main directory of this archive |
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* for more details. |
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* |
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* Copyright (C) 2008 - 2013 Tensilica Inc. |
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* |
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* Chris Zankel <chris@zankel.net> |
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* Joe Taylor <joe@tensilica.com> |
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* Pete Delaney <piet@tensilica.com |
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*/ |
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#include <linux/cpu.h> |
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#include <linux/cpumask.h> |
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#include <linux/delay.h> |
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#include <linux/init.h> |
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#include <linux/interrupt.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irq.h> |
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#include <linux/kdebug.h> |
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#include <linux/module.h> |
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#include <linux/reboot.h> |
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#include <linux/seq_file.h> |
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#include <linux/smp.h> |
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#include <linux/thread_info.h> |
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|
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#include <asm/cacheflush.h> |
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#include <asm/kdebug.h> |
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#include <asm/mmu_context.h> |
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#include <asm/mxregs.h> |
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#include <asm/platform.h> |
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#include <asm/tlbflush.h> |
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#include <asm/traps.h> |
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|
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#ifdef CONFIG_SMP |
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# if XCHAL_HAVE_S32C1I == 0 |
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# error "The S32C1I option is required for SMP." |
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# endif |
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#endif |
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static void system_invalidate_dcache_range(unsigned long start, |
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unsigned long size); |
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static void system_flush_invalidate_dcache_range(unsigned long start, |
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unsigned long size); |
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|
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/* IPI (Inter Process Interrupt) */ |
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#define IPI_IRQ 0 |
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static irqreturn_t ipi_interrupt(int irq, void *dev_id); |
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static struct irqaction ipi_irqaction = { |
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.handler = ipi_interrupt, |
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.flags = IRQF_PERCPU, |
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.name = "ipi", |
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}; |
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|
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void ipi_init(void) |
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{ |
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unsigned irq = irq_create_mapping(NULL, IPI_IRQ); |
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setup_irq(irq, &ipi_irqaction); |
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} |
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|
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static inline unsigned int get_core_count(void) |
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{ |
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/* Bits 18..21 of SYSCFGID contain the core count minus 1. */ |
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unsigned int syscfgid = get_er(SYSCFGID); |
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return ((syscfgid >> 18) & 0xf) + 1; |
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} |
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|
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static inline int get_core_id(void) |
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{ |
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/* Bits 0...18 of SYSCFGID contain the core id */ |
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unsigned int core_id = get_er(SYSCFGID); |
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return core_id & 0x3fff; |
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} |
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|
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void __init smp_prepare_cpus(unsigned int max_cpus) |
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{ |
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unsigned i; |
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|
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for (i = 0; i < max_cpus; ++i) |
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set_cpu_present(i, true); |
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} |
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|
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void __init smp_init_cpus(void) |
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{ |
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unsigned i; |
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unsigned int ncpus = get_core_count(); |
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unsigned int core_id = get_core_id(); |
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|
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pr_info("%s: Core Count = %d\n", __func__, ncpus); |
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pr_info("%s: Core Id = %d\n", __func__, core_id); |
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|
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for (i = 0; i < ncpus; ++i) |
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set_cpu_possible(i, true); |
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} |
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|
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void __init smp_prepare_boot_cpu(void) |
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{ |
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unsigned int cpu = smp_processor_id(); |
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BUG_ON(cpu != 0); |
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cpu_asid_cache(cpu) = ASID_USER_FIRST; |
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} |
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|
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void __init smp_cpus_done(unsigned int max_cpus) |
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{ |
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} |
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|
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static int boot_secondary_processors = 1; /* Set with xt-gdb via .xt-gdb */ |
||||
static DECLARE_COMPLETION(cpu_running); |
||||
|
||||
void secondary_start_kernel(void) |
||||
{ |
||||
struct mm_struct *mm = &init_mm; |
||||
unsigned int cpu = smp_processor_id(); |
||||
|
||||
init_mmu(); |
||||
|
||||
#ifdef CONFIG_DEBUG_KERNEL |
||||
if (boot_secondary_processors == 0) { |
||||
pr_debug("%s: boot_secondary_processors:%d; Hanging cpu:%d\n", |
||||
__func__, boot_secondary_processors, cpu); |
||||
for (;;) |
||||
__asm__ __volatile__ ("waiti " __stringify(LOCKLEVEL)); |
||||
} |
||||
|
||||
pr_debug("%s: boot_secondary_processors:%d; Booting cpu:%d\n", |
||||
__func__, boot_secondary_processors, cpu); |
||||
#endif |
||||
/* Init EXCSAVE1 */ |
||||
|
||||
secondary_trap_init(); |
||||
|
||||
/* All kernel threads share the same mm context. */ |
||||
|
||||
atomic_inc(&mm->mm_users); |
||||
atomic_inc(&mm->mm_count); |
||||
current->active_mm = mm; |
||||
cpumask_set_cpu(cpu, mm_cpumask(mm)); |
||||
enter_lazy_tlb(mm, current); |
||||
|
||||
preempt_disable(); |
||||
trace_hardirqs_off(); |
||||
|
||||
calibrate_delay(); |
||||
|
||||
notify_cpu_starting(cpu); |
||||
|
||||
secondary_init_irq(); |
||||
local_timer_setup(cpu); |
||||
|
||||
set_cpu_online(cpu, true); |
||||
|
||||
local_irq_enable(); |
||||
|
||||
complete(&cpu_running); |
||||
|
||||
cpu_startup_entry(CPUHP_ONLINE); |
||||
} |
||||
|
||||
static void mx_cpu_start(void *p) |
||||
{ |
||||
unsigned cpu = (unsigned)p; |
||||
unsigned long run_stall_mask = get_er(MPSCORE); |
||||
|
||||
set_er(run_stall_mask & ~(1u << cpu), MPSCORE); |
||||
pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", |
||||
__func__, cpu, run_stall_mask, get_er(MPSCORE)); |
||||
} |
||||
|
||||
static void mx_cpu_stop(void *p) |
||||
{ |
||||
unsigned cpu = (unsigned)p; |
||||
unsigned long run_stall_mask = get_er(MPSCORE); |
||||
|
||||
set_er(run_stall_mask | (1u << cpu), MPSCORE); |
||||
pr_debug("%s: cpu: %d, run_stall_mask: %lx ---> %lx\n", |
||||
__func__, cpu, run_stall_mask, get_er(MPSCORE)); |
||||
} |
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU |
||||
unsigned long cpu_start_id __cacheline_aligned; |
||||
#endif |
||||
unsigned long cpu_start_ccount; |
||||
|
||||
static int boot_secondary(unsigned int cpu, struct task_struct *ts) |
||||
{ |
||||
unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
||||
unsigned long ccount; |
||||
int i; |
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU |
||||
cpu_start_id = cpu; |
||||
system_flush_invalidate_dcache_range( |
||||
(unsigned long)&cpu_start_id, sizeof(cpu_start_id)); |
||||
#endif |
||||
smp_call_function_single(0, mx_cpu_start, (void *)cpu, 1); |
||||
|
||||
for (i = 0; i < 2; ++i) { |
||||
do |
||||
ccount = get_ccount(); |
||||
while (!ccount); |
||||
|
||||
cpu_start_ccount = ccount; |
||||
|
||||
while (time_before(jiffies, timeout)) { |
||||
mb(); |
||||
if (!cpu_start_ccount) |
||||
break; |
||||
} |
||||
|
||||
if (cpu_start_ccount) { |
||||
smp_call_function_single(0, mx_cpu_stop, |
||||
(void *)cpu, 1); |
||||
cpu_start_ccount = 0; |
||||
return -EIO; |
||||
} |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
int __cpu_up(unsigned int cpu, struct task_struct *idle) |
||||
{ |
||||
int ret = 0; |
||||
|
||||
if (cpu_asid_cache(cpu) == 0) |
||||
cpu_asid_cache(cpu) = ASID_USER_FIRST; |
||||
|
||||
start_info.stack = (unsigned long)task_pt_regs(idle); |
||||
wmb(); |
||||
|
||||
pr_debug("%s: Calling wakeup_secondary(cpu:%d, idle:%p, sp: %08lx)\n", |
||||
__func__, cpu, idle, start_info.stack); |
||||
|
||||
ret = boot_secondary(cpu, idle); |
||||
if (ret == 0) { |
||||
wait_for_completion_timeout(&cpu_running, |
||||
msecs_to_jiffies(1000)); |
||||
if (!cpu_online(cpu)) |
||||
ret = -EIO; |
||||
} |
||||
|
||||
if (ret) |
||||
pr_err("CPU %u failed to boot\n", cpu); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
#ifdef CONFIG_HOTPLUG_CPU |
||||
|
||||
/*
|
||||
* __cpu_disable runs on the processor to be shutdown. |
||||
*/ |
||||
int __cpu_disable(void) |
||||
{ |
||||
unsigned int cpu = smp_processor_id(); |
||||
|
||||
/*
|
||||
* Take this CPU offline. Once we clear this, we can't return, |
||||
* and we must not schedule until we're ready to give up the cpu. |
||||
*/ |
||||
set_cpu_online(cpu, false); |
||||
|
||||
/*
|
||||
* OK - migrate IRQs away from this CPU |
||||
*/ |
||||
migrate_irqs(); |
||||
|
||||
/*
|
||||
* Flush user cache and TLB mappings, and then remove this CPU |
||||
* from the vm mask set of all processes. |
||||
*/ |
||||
local_flush_cache_all(); |
||||
local_flush_tlb_all(); |
||||
invalidate_page_directory(); |
||||
|
||||
clear_tasks_mm_cpumask(cpu); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void platform_cpu_kill(unsigned int cpu) |
||||
{ |
||||
smp_call_function_single(0, mx_cpu_stop, (void *)cpu, true); |
||||
} |
||||
|
||||
/*
|
||||
* called on the thread which is asking for a CPU to be shutdown - |
||||
* waits until shutdown has completed, or it is timed out. |
||||
*/ |
||||
void __cpu_die(unsigned int cpu) |
||||
{ |
||||
unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
||||
while (time_before(jiffies, timeout)) { |
||||
system_invalidate_dcache_range((unsigned long)&cpu_start_id, |
||||
sizeof(cpu_start_id)); |
||||
if (cpu_start_id == -cpu) { |
||||
platform_cpu_kill(cpu); |
||||
return; |
||||
} |
||||
} |
||||
pr_err("CPU%u: unable to kill\n", cpu); |
||||
} |
||||
|
||||
void arch_cpu_idle_dead(void) |
||||
{ |
||||
cpu_die(); |
||||
} |
||||
/*
|
||||
* Called from the idle thread for the CPU which has been shutdown. |
||||
* |
||||
* Note that we disable IRQs here, but do not re-enable them |
||||
* before returning to the caller. This is also the behaviour |
||||
* of the other hotplug-cpu capable cores, so presumably coming |
||||
* out of idle fixes this. |
||||
*/ |
||||
void __ref cpu_die(void) |
||||
{ |
||||
idle_task_exit(); |
||||
local_irq_disable(); |
||||
__asm__ __volatile__( |
||||
" movi a2, cpu_restart\n" |
||||
" jx a2\n"); |
||||
} |
||||
|
||||
#endif /* CONFIG_HOTPLUG_CPU */ |
||||
|
||||
enum ipi_msg_type { |
||||
IPI_RESCHEDULE = 0, |
||||
IPI_CALL_FUNC, |
||||
IPI_CPU_STOP, |
||||
IPI_MAX |
||||
}; |
||||
|
||||
static const struct { |
||||
const char *short_text; |
||||
const char *long_text; |
||||
} ipi_text[] = { |
||||
{ .short_text = "RES", .long_text = "Rescheduling interrupts" }, |
||||
{ .short_text = "CAL", .long_text = "Function call interrupts" }, |
||||
{ .short_text = "DIE", .long_text = "CPU shutdown interrupts" }, |
||||
}; |
||||
|
||||
struct ipi_data { |
||||
unsigned long ipi_count[IPI_MAX]; |
||||
}; |
||||
|
||||
static DEFINE_PER_CPU(struct ipi_data, ipi_data); |
||||
|
||||
static void send_ipi_message(const struct cpumask *callmask, |
||||
enum ipi_msg_type msg_id) |
||||
{ |
||||
int index; |
||||
unsigned long mask = 0; |
||||
|
||||
for_each_cpu(index, callmask) |
||||
if (index != smp_processor_id()) |
||||
mask |= 1 << index; |
||||
|
||||
set_er(mask, MIPISET(msg_id)); |
||||
} |
||||
|
||||
void arch_send_call_function_ipi_mask(const struct cpumask *mask) |
||||
{ |
||||
send_ipi_message(mask, IPI_CALL_FUNC); |
||||
} |
||||
|
||||
void arch_send_call_function_single_ipi(int cpu) |
||||
{ |
||||
send_ipi_message(cpumask_of(cpu), IPI_CALL_FUNC); |
||||
} |
||||
|
||||
void smp_send_reschedule(int cpu) |
||||
{ |
||||
send_ipi_message(cpumask_of(cpu), IPI_RESCHEDULE); |
||||
} |
||||
|
||||
void smp_send_stop(void) |
||||
{ |
||||
struct cpumask targets; |
||||
|
||||
cpumask_copy(&targets, cpu_online_mask); |
||||
cpumask_clear_cpu(smp_processor_id(), &targets); |
||||
send_ipi_message(&targets, IPI_CPU_STOP); |
||||
} |
||||
|
||||
static void ipi_cpu_stop(unsigned int cpu) |
||||
{ |
||||
set_cpu_online(cpu, false); |
||||
machine_halt(); |
||||
} |
||||
|
||||
irqreturn_t ipi_interrupt(int irq, void *dev_id) |
||||
{ |
||||
unsigned int cpu = smp_processor_id(); |
||||
struct ipi_data *ipi = &per_cpu(ipi_data, cpu); |
||||
unsigned int msg; |
||||
unsigned i; |
||||
|
||||
msg = get_er(MIPICAUSE(cpu)); |
||||
for (i = 0; i < IPI_MAX; i++) |
||||
if (msg & (1 << i)) { |
||||
set_er(1 << i, MIPICAUSE(cpu)); |
||||
++ipi->ipi_count[i]; |
||||
} |
||||
|
||||
if (msg & (1 << IPI_RESCHEDULE)) |
||||
scheduler_ipi(); |
||||
if (msg & (1 << IPI_CALL_FUNC)) |
||||
generic_smp_call_function_interrupt(); |
||||
if (msg & (1 << IPI_CPU_STOP)) |
||||
ipi_cpu_stop(cpu); |
||||
|
||||
return IRQ_HANDLED; |
||||
} |
||||
|
||||
void show_ipi_list(struct seq_file *p, int prec) |
||||
{ |
||||
unsigned int cpu; |
||||
unsigned i; |
||||
|
||||
for (i = 0; i < IPI_MAX; ++i) { |
||||
seq_printf(p, "%*s:", prec, ipi_text[i].short_text); |
||||
for_each_online_cpu(cpu) |
||||
seq_printf(p, " %10lu", |
||||
per_cpu(ipi_data, cpu).ipi_count[i]); |
||||
seq_printf(p, " %s\n", ipi_text[i].long_text); |
||||
} |
||||
} |
||||
|
||||
int setup_profiling_timer(unsigned int multiplier) |
||||
{ |
||||
pr_debug("setup_profiling_timer %d\n", multiplier); |
||||
return 0; |
||||
} |
||||
|
||||
/* TLB flush functions */ |
||||
|
||||
struct flush_data { |
||||
struct vm_area_struct *vma; |
||||
unsigned long addr1; |
||||
unsigned long addr2; |
||||
}; |
||||
|
||||
static void ipi_flush_tlb_all(void *arg) |
||||
{ |
||||
local_flush_tlb_all(); |
||||
} |
||||
|
||||
void flush_tlb_all(void) |
||||
{ |
||||
on_each_cpu(ipi_flush_tlb_all, NULL, 1); |
||||
} |
||||
|
||||
static void ipi_flush_tlb_mm(void *arg) |
||||
{ |
||||
local_flush_tlb_mm(arg); |
||||
} |
||||
|
||||
void flush_tlb_mm(struct mm_struct *mm) |
||||
{ |
||||
on_each_cpu(ipi_flush_tlb_mm, mm, 1); |
||||
} |
||||
|
||||
static void ipi_flush_tlb_page(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
local_flush_tlb_page(fd->vma, fd->addr1); |
||||
} |
||||
|
||||
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr) |
||||
{ |
||||
struct flush_data fd = { |
||||
.vma = vma, |
||||
.addr1 = addr, |
||||
}; |
||||
on_each_cpu(ipi_flush_tlb_page, &fd, 1); |
||||
} |
||||
|
||||
static void ipi_flush_tlb_range(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
local_flush_tlb_range(fd->vma, fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
void flush_tlb_range(struct vm_area_struct *vma, |
||||
unsigned long start, unsigned long end) |
||||
{ |
||||
struct flush_data fd = { |
||||
.vma = vma, |
||||
.addr1 = start, |
||||
.addr2 = end, |
||||
}; |
||||
on_each_cpu(ipi_flush_tlb_range, &fd, 1); |
||||
} |
||||
|
||||
/* Cache flush functions */ |
||||
|
||||
static void ipi_flush_cache_all(void *arg) |
||||
{ |
||||
local_flush_cache_all(); |
||||
} |
||||
|
||||
void flush_cache_all(void) |
||||
{ |
||||
on_each_cpu(ipi_flush_cache_all, NULL, 1); |
||||
} |
||||
|
||||
static void ipi_flush_cache_page(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
local_flush_cache_page(fd->vma, fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
void flush_cache_page(struct vm_area_struct *vma, |
||||
unsigned long address, unsigned long pfn) |
||||
{ |
||||
struct flush_data fd = { |
||||
.vma = vma, |
||||
.addr1 = address, |
||||
.addr2 = pfn, |
||||
}; |
||||
on_each_cpu(ipi_flush_cache_page, &fd, 1); |
||||
} |
||||
|
||||
static void ipi_flush_cache_range(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
local_flush_cache_range(fd->vma, fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
void flush_cache_range(struct vm_area_struct *vma, |
||||
unsigned long start, unsigned long end) |
||||
{ |
||||
struct flush_data fd = { |
||||
.vma = vma, |
||||
.addr1 = start, |
||||
.addr2 = end, |
||||
}; |
||||
on_each_cpu(ipi_flush_cache_range, &fd, 1); |
||||
} |
||||
|
||||
static void ipi_flush_icache_range(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
local_flush_icache_range(fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
void flush_icache_range(unsigned long start, unsigned long end) |
||||
{ |
||||
struct flush_data fd = { |
||||
.addr1 = start, |
||||
.addr2 = end, |
||||
}; |
||||
on_each_cpu(ipi_flush_icache_range, &fd, 1); |
||||
} |
||||
|
||||
/* ------------------------------------------------------------------------- */ |
||||
|
||||
static void ipi_invalidate_dcache_range(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
__invalidate_dcache_range(fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
static void system_invalidate_dcache_range(unsigned long start, |
||||
unsigned long size) |
||||
{ |
||||
struct flush_data fd = { |
||||
.addr1 = start, |
||||
.addr2 = size, |
||||
}; |
||||
on_each_cpu(ipi_invalidate_dcache_range, &fd, 1); |
||||
} |
||||
|
||||
static void ipi_flush_invalidate_dcache_range(void *arg) |
||||
{ |
||||
struct flush_data *fd = arg; |
||||
__flush_invalidate_dcache_range(fd->addr1, fd->addr2); |
||||
} |
||||
|
||||
static void system_flush_invalidate_dcache_range(unsigned long start, |
||||
unsigned long size) |
||||
{ |
||||
struct flush_data fd = { |
||||
.addr1 = start, |
||||
.addr2 = size, |
||||
}; |
||||
on_each_cpu(ipi_flush_invalidate_dcache_range, &fd, 1); |
||||
} |
||||
@ -0,0 +1,164 @@ |
||||
/*
|
||||
* Xtensa MX interrupt distributor |
||||
* |
||||
* Copyright (C) 2002 - 2013 Tensilica, Inc. |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
*/ |
||||
|
||||
#include <linux/interrupt.h> |
||||
#include <linux/irqdomain.h> |
||||
#include <linux/irq.h> |
||||
#include <linux/of.h> |
||||
|
||||
#include <asm/mxregs.h> |
||||
|
||||
#include "irqchip.h" |
||||
|
||||
#define HW_IRQ_IPI_COUNT 2 |
||||
#define HW_IRQ_MX_BASE 2 |
||||
#define HW_IRQ_EXTERN_BASE 3 |
||||
|
||||
static DEFINE_PER_CPU(unsigned int, cached_irq_mask); |
||||
|
||||
static int xtensa_mx_irq_map(struct irq_domain *d, unsigned int irq, |
||||
irq_hw_number_t hw) |
||||
{ |
||||
if (hw < HW_IRQ_IPI_COUNT) { |
||||
struct irq_chip *irq_chip = d->host_data; |
||||
irq_set_chip_and_handler_name(irq, irq_chip, |
||||
handle_percpu_irq, "ipi"); |
||||
irq_set_status_flags(irq, IRQ_LEVEL); |
||||
return 0; |
||||
} |
||||
return xtensa_irq_map(d, irq, hw); |
||||
} |
||||
|
||||
/*
|
||||
* Device Tree IRQ specifier translation function which works with one or |
||||
* two cell bindings. First cell value maps directly to the hwirq number. |
||||
* Second cell if present specifies whether hwirq number is external (1) or |
||||
* internal (0). |
||||
*/ |
||||
static int xtensa_mx_irq_domain_xlate(struct irq_domain *d, |
||||
struct device_node *ctrlr, |
||||
const u32 *intspec, unsigned int intsize, |
||||
unsigned long *out_hwirq, unsigned int *out_type) |
||||
{ |
||||
return xtensa_irq_domain_xlate(intspec, intsize, |
||||
intspec[0], intspec[0] + HW_IRQ_EXTERN_BASE, |
||||
out_hwirq, out_type); |
||||
} |
||||
|
||||
static const struct irq_domain_ops xtensa_mx_irq_domain_ops = { |
||||
.xlate = xtensa_mx_irq_domain_xlate, |
||||
.map = xtensa_mx_irq_map, |
||||
}; |
||||
|
||||
void secondary_init_irq(void) |
||||
{ |
||||
__this_cpu_write(cached_irq_mask, |
||||
XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
||||
XCHAL_INTTYPE_MASK_EXTERN_LEVEL); |
||||
set_sr(XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
||||
XCHAL_INTTYPE_MASK_EXTERN_LEVEL, intenable); |
||||
} |
||||
|
||||
static void xtensa_mx_irq_mask(struct irq_data *d) |
||||
{ |
||||
unsigned int mask = 1u << d->hwirq; |
||||
|
||||
if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
||||
XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { |
||||
set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - |
||||
HW_IRQ_MX_BASE), MIENG); |
||||
} else { |
||||
mask = __this_cpu_read(cached_irq_mask) & ~mask; |
||||
__this_cpu_write(cached_irq_mask, mask); |
||||
set_sr(mask, intenable); |
||||
} |
||||
} |
||||
|
||||
static void xtensa_mx_irq_unmask(struct irq_data *d) |
||||
{ |
||||
unsigned int mask = 1u << d->hwirq; |
||||
|
||||
if (mask & (XCHAL_INTTYPE_MASK_EXTERN_EDGE | |
||||
XCHAL_INTTYPE_MASK_EXTERN_LEVEL)) { |
||||
set_er(1u << (xtensa_get_ext_irq_no(d->hwirq) - |
||||
HW_IRQ_MX_BASE), MIENGSET); |
||||
} else { |
||||
mask |= __this_cpu_read(cached_irq_mask); |
||||
__this_cpu_write(cached_irq_mask, mask); |
||||
set_sr(mask, intenable); |
||||
} |
||||
} |
||||
|
||||
static void xtensa_mx_irq_enable(struct irq_data *d) |
||||
{ |
||||
variant_irq_enable(d->hwirq); |
||||
xtensa_mx_irq_unmask(d); |
||||
} |
||||
|
||||
static void xtensa_mx_irq_disable(struct irq_data *d) |
||||
{ |
||||
xtensa_mx_irq_mask(d); |
||||
variant_irq_disable(d->hwirq); |
||||
} |
||||
|
||||
static void xtensa_mx_irq_ack(struct irq_data *d) |
||||
{ |
||||
set_sr(1 << d->hwirq, intclear); |
||||
} |
||||
|
||||
static int xtensa_mx_irq_retrigger(struct irq_data *d) |
||||
{ |
||||
set_sr(1 << d->hwirq, intset); |
||||
return 1; |
||||
} |
||||
|
||||
static int xtensa_mx_irq_set_affinity(struct irq_data *d, |
||||
const struct cpumask *dest, bool force) |
||||
{ |
||||
unsigned mask = 1u << cpumask_any(dest); |
||||
|
||||
set_er(mask, MIROUT(d->hwirq - HW_IRQ_MX_BASE)); |
||||
return 0; |
||||
|
||||
} |
||||
|
||||
static struct irq_chip xtensa_mx_irq_chip = { |
||||
.name = "xtensa-mx", |
||||
.irq_enable = xtensa_mx_irq_enable, |
||||
.irq_disable = xtensa_mx_irq_disable, |
||||
.irq_mask = xtensa_mx_irq_mask, |
||||
.irq_unmask = xtensa_mx_irq_unmask, |
||||
.irq_ack = xtensa_mx_irq_ack, |
||||
.irq_retrigger = xtensa_mx_irq_retrigger, |
||||
.irq_set_affinity = xtensa_mx_irq_set_affinity, |
||||
}; |
||||
|
||||
int __init xtensa_mx_init_legacy(struct device_node *interrupt_parent) |
||||
{ |
||||
struct irq_domain *root_domain = |
||||
irq_domain_add_legacy(NULL, NR_IRQS, 0, 0, |
||||
&xtensa_mx_irq_domain_ops, |
||||
&xtensa_mx_irq_chip); |
||||
irq_set_default_host(root_domain); |
||||
secondary_init_irq(); |
||||
return 0; |
||||
} |
||||
|
||||
static int __init xtensa_mx_init(struct device_node *np, |
||||
struct device_node *interrupt_parent) |
||||
{ |
||||
struct irq_domain *root_domain = |
||||
irq_domain_add_linear(np, NR_IRQS, &xtensa_mx_irq_domain_ops, |
||||
&xtensa_mx_irq_chip); |
||||
irq_set_default_host(root_domain); |
||||
secondary_init_irq(); |
||||
return 0; |
||||
} |
||||
IRQCHIP_DECLARE(xtensa_mx_irq_chip, "cdns,xtensa-mx", xtensa_mx_init); |
||||
@ -0,0 +1,108 @@ |
||||
/*
|
||||
* Xtensa built-in interrupt controller |
||||
* |
||||
* Copyright (C) 2002 - 2013 Tensilica, Inc. |
||||
* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
* |
||||
* Chris Zankel <chris@zankel.net> |
||||
* Kevin Chea |
||||
*/ |
||||
|
||||
#include <linux/interrupt.h> |
||||
#include <linux/irqdomain.h> |
||||
#include <linux/irq.h> |
||||
#include <linux/of.h> |
||||
|
||||
#include "irqchip.h" |
||||
|
||||
unsigned int cached_irq_mask; |
||||
|
||||
/*
|
||||
* Device Tree IRQ specifier translation function which works with one or |
||||
* two cell bindings. First cell value maps directly to the hwirq number. |
||||
* Second cell if present specifies whether hwirq number is external (1) or |
||||
* internal (0). |
||||
*/ |
||||
static int xtensa_pic_irq_domain_xlate(struct irq_domain *d, |
||||
struct device_node *ctrlr, |
||||
const u32 *intspec, unsigned int intsize, |
||||
unsigned long *out_hwirq, unsigned int *out_type) |
||||
{ |
||||
return xtensa_irq_domain_xlate(intspec, intsize, |
||||
intspec[0], intspec[0], |
||||
out_hwirq, out_type); |
||||
} |
||||
|
||||
static const struct irq_domain_ops xtensa_irq_domain_ops = { |
||||
.xlate = xtensa_pic_irq_domain_xlate, |
||||
.map = xtensa_irq_map, |
||||
}; |
||||
|
||||
static void xtensa_irq_mask(struct irq_data *d) |
||||
{ |
||||
cached_irq_mask &= ~(1 << d->hwirq); |
||||
set_sr(cached_irq_mask, intenable); |
||||
} |
||||
|
||||
static void xtensa_irq_unmask(struct irq_data *d) |
||||
{ |
||||
cached_irq_mask |= 1 << d->hwirq; |
||||
set_sr(cached_irq_mask, intenable); |
||||
} |
||||
|
||||
static void xtensa_irq_enable(struct irq_data *d) |
||||
{ |
||||
variant_irq_enable(d->hwirq); |
||||
xtensa_irq_unmask(d); |
||||
} |
||||
|
||||
static void xtensa_irq_disable(struct irq_data *d) |
||||
{ |
||||
xtensa_irq_mask(d); |
||||
variant_irq_disable(d->hwirq); |
||||
} |
||||
|
||||
static void xtensa_irq_ack(struct irq_data *d) |
||||
{ |
||||
set_sr(1 << d->hwirq, intclear); |
||||
} |
||||
|
||||
static int xtensa_irq_retrigger(struct irq_data *d) |
||||
{ |
||||
set_sr(1 << d->hwirq, intset); |
||||
return 1; |
||||
} |
||||
|
||||
static struct irq_chip xtensa_irq_chip = { |
||||
.name = "xtensa", |
||||
.irq_enable = xtensa_irq_enable, |
||||
.irq_disable = xtensa_irq_disable, |
||||
.irq_mask = xtensa_irq_mask, |
||||
.irq_unmask = xtensa_irq_unmask, |
||||
.irq_ack = xtensa_irq_ack, |
||||
.irq_retrigger = xtensa_irq_retrigger, |
||||
}; |
||||
|
||||
int __init xtensa_pic_init_legacy(struct device_node *interrupt_parent) |
||||
{ |
||||
struct irq_domain *root_domain = |
||||
irq_domain_add_legacy(NULL, NR_IRQS, 0, 0, |
||||
&xtensa_irq_domain_ops, &xtensa_irq_chip); |
||||
irq_set_default_host(root_domain); |
||||
return 0; |
||||
} |
||||
|
||||
static int __init xtensa_pic_init(struct device_node *np, |
||||
struct device_node *interrupt_parent) |
||||
{ |
||||
struct irq_domain *root_domain = |
||||
irq_domain_add_linear(np, NR_IRQS, &xtensa_irq_domain_ops, |
||||
&xtensa_irq_chip); |
||||
irq_set_default_host(root_domain); |
||||
return 0; |
||||
} |
||||
IRQCHIP_DECLARE(xtensa_irq_chip, "cdns,xtensa-pic", xtensa_pic_init); |
||||
@ -0,0 +1,17 @@ |
||||
/*
|
||||
* Xtensa MX interrupt distributor |
||||
* |
||||
* Copyright (C) 2002 - 2013 Tensilica, Inc. |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
*/ |
||||
|
||||
#ifndef __LINUX_IRQCHIP_XTENSA_MX_H |
||||
#define __LINUX_IRQCHIP_XTENSA_MX_H |
||||
|
||||
struct device_node; |
||||
int xtensa_mx_init_legacy(struct device_node *interrupt_parent); |
||||
|
||||
#endif /* __LINUX_IRQCHIP_XTENSA_MX_H */ |
||||
@ -0,0 +1,18 @@ |
||||
/*
|
||||
* Xtensa built-in interrupt controller |
||||
* |
||||
* Copyright (C) 2002 - 2013 Tensilica, Inc. |
||||
* Copyright (C) 1992, 1998 Linus Torvalds, Ingo Molnar |
||||
* |
||||
* This file is subject to the terms and conditions of the GNU General Public |
||||
* License. See the file "COPYING" in the main directory of this archive |
||||
* for more details. |
||||
*/ |
||||
|
||||
#ifndef __LINUX_IRQCHIP_XTENSA_PIC_H |
||||
#define __LINUX_IRQCHIP_XTENSA_PIC_H |
||||
|
||||
struct device_node; |
||||
int xtensa_pic_init_legacy(struct device_node *interrupt_parent); |
||||
|
||||
#endif /* __LINUX_IRQCHIP_XTENSA_PIC_H */ |
||||
Loading…
Reference in new issue