@ -35,6 +35,7 @@
* DMA descriptor defines .
*/
# define TXD_DESC_SIZE (4 * sizeof(__le32))
# define RXD_DESC_SIZE (4 * sizeof(__le32))
/*
* TX descriptor format for TX , PRIO and Beacon Ring .
@ -72,10 +73,60 @@
# define TXD_W3_UCO FIELD32(0x40000000)
# define TXD_W3_ICO FIELD32(0x80000000)
/*
* RX descriptor format for RX Ring .
*/
/*
* Word0
*/
# define RXD_W0_SDP0 FIELD32(0xffffffff)
/*
* Word1
*/
# define RXD_W1_SDL1 FIELD32(0x00003fff)
# define RXD_W1_SDL0 FIELD32(0x3fff0000)
# define RXD_W1_LS0 FIELD32(0x40000000)
# define RXD_W1_DMA_DONE FIELD32(0x80000000)
/*
* Word2
*/
# define RXD_W2_SDP1 FIELD32(0xffffffff)
/*
* Word3
* AMSDU : RX with 802.3 header , not 802.11 header .
* DECRYPTED : This frame is being decrypted .
*/
# define RXD_W3_BA FIELD32(0x00000001)
# define RXD_W3_DATA FIELD32(0x00000002)
# define RXD_W3_NULLDATA FIELD32(0x00000004)
# define RXD_W3_FRAG FIELD32(0x00000008)
# define RXD_W3_UNICAST_TO_ME FIELD32(0x00000010)
# define RXD_W3_MULTICAST FIELD32(0x00000020)
# define RXD_W3_BROADCAST FIELD32(0x00000040)
# define RXD_W3_MY_BSS FIELD32(0x00000080)
# define RXD_W3_CRC_ERROR FIELD32(0x00000100)
# define RXD_W3_CIPHER_ERROR FIELD32(0x00000600)
# define RXD_W3_AMSDU FIELD32(0x00000800)
# define RXD_W3_HTC FIELD32(0x00001000)
# define RXD_W3_RSSI FIELD32(0x00002000)
# define RXD_W3_L2PAD FIELD32(0x00004000)
# define RXD_W3_AMPDU FIELD32(0x00008000)
# define RXD_W3_DECRYPTED FIELD32(0x00010000)
# define RXD_W3_PLCP_SIGNAL FIELD32(0x00020000)
# define RXD_W3_PLCP_RSSI FIELD32(0x00040000)
/* TX descriptor initialization */
__le32 * rt2800mmio_get_txwi ( struct queue_entry * entry ) ;
void rt2800mmio_write_tx_desc ( struct queue_entry * entry ,
struct txentry_desc * txdesc ) ;
/* RX control handlers */
void rt2800mmio_fill_rxdone ( struct queue_entry * entry ,
struct rxdone_entry_desc * rxdesc ) ;
# endif /* RT2800MMIO_H */