The legacy HAVE_PWM Kconfig symbol is finally being retired. Thanks a lot to Sascha Hauer for doing that. Three new drivers are added: Freescale FTM, Cirrus Logic CLPS711X and Intel Low Power Subsystem. An assortment of fixes and cleanups rounds things off for this release cycle. -----BEGIN PGP SIGNATURE----- Version: GnuPG v2.0.22 (GNU/Linux) iQIcBAABAgAGBQJTPmXoAAoJEN0jrNd/PrOhSacQAKNpqWHpFdFuhqpO6dvmqYj3 dvf6EDMnNaOS+TjbCvwP5awAiBhTbJRaTclP1lXXXOnzHvzeeYWhS2ESp4Yl8mRx GRHj5OxmquaVPY5HN+6guVyCrgq4R2sxPU1P2VoPhhomhvP2VuEBbD/ddudC3e2k /e9BuBhUB9eaur6d+vKX7Bnz09wf+ASobgIisjyyqSYysDgE82BAanX/knnLIyQL RKCsz75w14rIxU/f8EML8EMnWiGINYpP+M/NGtPvcNBBOX9DkdzBvSvcbm+gS6ma g2P+zsJgxhUpvvmzhqUumADUU8BWo/P1Y/6FQGRku6EmmJQQspTvDvOs1jCauouC 5vUA41Jwh+4+AKeNWN28tDlh9i5kKYdzYP5SeRcM9mW1SI7AIFmg62lxdus7ZnBB e8UFd26kp/hZxXPdDVHtQi9y5Z5kn4axutVpbISuW5P9z1HF9bFOVHKQVlk7D6uz EqqiYLdW/MxrmBq+v35biwx6afk3zJ8Qas/MmVIVTcLcLDTFLPEm4EawwcRZo8F3 Jh4p4IHxjEgLYcwVBNOe4ZBJg10fM1gmh18dDTyri759HE1mpi4/DwTGcv3iK4AU njv4Q+qBq9QkY2ktw3qCkTDcwiM9jm+FHfdyKXeR5+CjfOf61/CF+N1jBQ8ZMrb7 XIRHle+mvL/RYpPDML/P =pbF+ -----END PGP SIGNATURE----- Merge tag 'pwm/for-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm Pull pwm changes from Thierry Reding: "The legacy HAVE_PWM Kconfig symbol is finally being retired. Thanks a lot to Sascha Hauer for doing that. Three new drivers are added: Freescale FTM, Cirrus Logic CLPS711X and Intel Low Power Subsystem. An assortment of fixes and cleanups rounds things off for this release cycle" * tag 'pwm/for-3.15-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/thierry.reding/linux-pwm: pwm: pxa: Constify OF match table pwm: pxa: Fix typo "pwm" -> "PWM" Revert "pwm: pxa: Use of_match_ptr()" pwm: add support for Intel Low Power Subsystem PWM pwm: Add CLPS711X PWM support pwm: atmel: correct CDTY calculation pwm: atmel: Fix polarity handling Documentation: Add device tree bindings for Freescale FTM PWM. pwm: Add Freescale FTM PWM driver support pwm: pxa: Use of_match_ptr() pwm: samsung: Use SIMPLE_DEV_PM_OPS macro pwm: renesas-tpu: Add dependency on HAS_IOMEM pwm: Remove obsolete HAVE_PWM Kconfig symboltirimbino
Linus Torvalds
11 years ago
commit
9712d3c377
@ -0,0 +1,16 @@ |
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* Cirris Logic CLPS711X PWM controller |
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|
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Required properties: |
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- compatible: Shall contain "cirrus,clps711x-pwm". |
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- reg: Physical base address and length of the controller's registers. |
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- clocks: phandle + clock specifier pair of the PWM reference clock. |
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- #pwm-cells: Should be 1. The cell specifies the index of the channel. |
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|
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Example: |
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pwm: pwm@80000400 { |
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compatible = "cirrus,ep7312-pwm", |
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"cirrus,clps711x-pwm"; |
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reg = <0x80000400 0x4>; |
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clocks = <&clks 8>; |
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#pwm-cells = <1>; |
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}; |
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@ -0,0 +1,35 @@ |
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Freescale FlexTimer Module (FTM) PWM controller |
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|
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Required properties: |
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- compatible: Should be "fsl,vf610-ftm-pwm". |
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- reg: Physical base address and length of the controller's registers |
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- #pwm-cells: Should be 3. See pwm.txt in this directory for a description of |
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the cells format. |
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- clock-names: Should include the following module clock source entries: |
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"ftm_sys" (module clock, also can be used as counter clock), |
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"ftm_ext" (external counter clock), |
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"ftm_fix" (fixed counter clock), |
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"ftm_cnt_clk_en" (external and fixed counter clock enable/disable). |
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- clocks: Must contain a phandle and clock specifier for each entry in |
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clock-names, please see clock/clock-bindings.txt for details of the property |
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values. |
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- pinctrl-names: Must contain a "default" entry. |
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- pinctrl-NNN: One property must exist for each entry in pinctrl-names. |
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See pinctrl/pinctrl-bindings.txt for details of the property values. |
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|
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|
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Example: |
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pwm0: pwm@40038000 { |
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compatible = "fsl,vf610-ftm-pwm"; |
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reg = <0x40038000 0x1000>; |
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#pwm-cells = <3>; |
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clock-names = "ftm_sys", "ftm_ext", |
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"ftm_fix", "ftm_cnt_clk_en"; |
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clocks = <&clks VF610_CLK_FTM0>, |
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<&clks VF610_CLK_FTM0_EXT_SEL>, |
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<&clks VF610_CLK_FTM0_FIX_SEL>, |
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<&clks VF610_CLK_FTM0_EXT_FIX_EN>; |
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pinctrl-names = "default"; |
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pinctrl-0 = <&pinctrl_pwm0_1>; |
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}; |
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@ -0,0 +1,176 @@ |
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/*
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* Cirrus Logic CLPS711X PWM driver |
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* |
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* Copyright (C) 2014 Alexander Shiyan <shc_work@mail.ru> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/io.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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|
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struct clps711x_chip { |
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struct pwm_chip chip; |
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void __iomem *pmpcon; |
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struct clk *clk; |
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spinlock_t lock; |
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}; |
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|
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static inline struct clps711x_chip *to_clps711x_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct clps711x_chip, chip); |
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} |
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|
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static void clps711x_pwm_update_val(struct clps711x_chip *priv, u32 n, u32 v) |
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{ |
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/* PWM0 - bits 4..7, PWM1 - bits 8..11 */ |
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u32 shift = (n + 1) * 4; |
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unsigned long flags; |
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u32 tmp; |
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spin_lock_irqsave(&priv->lock, flags); |
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tmp = readl(priv->pmpcon); |
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tmp &= ~(0xf << shift); |
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tmp |= v << shift; |
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writel(tmp, priv->pmpcon); |
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spin_unlock_irqrestore(&priv->lock, flags); |
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} |
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static unsigned int clps711x_get_duty(struct pwm_device *pwm, unsigned int v) |
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{ |
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/* Duty cycle 0..15 max */ |
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return DIV_ROUND_CLOSEST(v * 0xf, pwm_get_period(pwm)); |
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} |
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|
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static int clps711x_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct clps711x_chip *priv = to_clps711x_chip(chip); |
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unsigned int freq = clk_get_rate(priv->clk); |
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if (!freq) |
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return -EINVAL; |
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/* Store constant period value */ |
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pwm_set_period(pwm, DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq)); |
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return 0; |
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} |
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|
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static int clps711x_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
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int duty_ns, int period_ns) |
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{ |
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struct clps711x_chip *priv = to_clps711x_chip(chip); |
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unsigned int duty; |
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if (period_ns != pwm_get_period(pwm)) |
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return -EINVAL; |
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duty = clps711x_get_duty(pwm, duty_ns); |
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clps711x_pwm_update_val(priv, pwm->hwpwm, duty); |
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return 0; |
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} |
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|
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static int clps711x_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct clps711x_chip *priv = to_clps711x_chip(chip); |
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unsigned int duty; |
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duty = clps711x_get_duty(pwm, pwm_get_duty_cycle(pwm)); |
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clps711x_pwm_update_val(priv, pwm->hwpwm, duty); |
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return 0; |
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} |
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static void clps711x_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct clps711x_chip *priv = to_clps711x_chip(chip); |
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clps711x_pwm_update_val(priv, pwm->hwpwm, 0); |
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} |
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static const struct pwm_ops clps711x_pwm_ops = { |
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.request = clps711x_pwm_request, |
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.config = clps711x_pwm_config, |
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.enable = clps711x_pwm_enable, |
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.disable = clps711x_pwm_disable, |
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.owner = THIS_MODULE, |
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}; |
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static struct pwm_device *clps711x_pwm_xlate(struct pwm_chip *chip, |
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const struct of_phandle_args *args) |
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{ |
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if (args->args[0] >= chip->npwm) |
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return ERR_PTR(-EINVAL); |
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return pwm_request_from_chip(chip, args->args[0], NULL); |
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} |
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static int clps711x_pwm_probe(struct platform_device *pdev) |
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{ |
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struct clps711x_chip *priv; |
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struct resource *res; |
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priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); |
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if (!priv) |
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return -ENOMEM; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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priv->pmpcon = devm_ioremap_resource(&pdev->dev, res); |
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if (IS_ERR(priv->pmpcon)) |
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return PTR_ERR(priv->pmpcon); |
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priv->clk = devm_clk_get(&pdev->dev, NULL); |
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if (IS_ERR(priv->clk)) |
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return PTR_ERR(priv->clk); |
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priv->chip.ops = &clps711x_pwm_ops; |
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priv->chip.dev = &pdev->dev; |
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priv->chip.base = -1; |
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priv->chip.npwm = 2; |
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priv->chip.of_xlate = clps711x_pwm_xlate; |
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priv->chip.of_pwm_n_cells = 1; |
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spin_lock_init(&priv->lock); |
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platform_set_drvdata(pdev, priv); |
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return pwmchip_add(&priv->chip); |
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} |
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static int clps711x_pwm_remove(struct platform_device *pdev) |
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{ |
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struct clps711x_chip *priv = platform_get_drvdata(pdev); |
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return pwmchip_remove(&priv->chip); |
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} |
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static const struct of_device_id __maybe_unused clps711x_pwm_dt_ids[] = { |
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{ .compatible = "cirrus,clps711x-pwm", }, |
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{ } |
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}; |
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MODULE_DEVICE_TABLE(of, clps711x_pwm_dt_ids); |
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static struct platform_driver clps711x_pwm_driver = { |
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.driver = { |
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.name = "clps711x-pwm", |
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.owner = THIS_MODULE, |
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.of_match_table = of_match_ptr(clps711x_pwm_dt_ids), |
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}, |
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.probe = clps711x_pwm_probe, |
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.remove = clps711x_pwm_remove, |
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}; |
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module_platform_driver(clps711x_pwm_driver); |
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MODULE_AUTHOR("Alexander Shiyan <shc_work@mail.ru>"); |
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MODULE_DESCRIPTION("Cirrus Logic CLPS711X PWM driver"); |
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MODULE_LICENSE("GPL"); |
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@ -0,0 +1,495 @@ |
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/*
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* Freescale FlexTimer Module (FTM) PWM Driver |
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* |
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* Copyright 2012-2013 Freescale Semiconductor, Inc. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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*/ |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/mutex.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/pwm.h> |
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#include <linux/slab.h> |
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#define FTM_SC 0x00 |
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#define FTM_SC_CLK_MASK 0x3 |
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#define FTM_SC_CLK_SHIFT 3 |
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#define FTM_SC_CLK(c) (((c) + 1) << FTM_SC_CLK_SHIFT) |
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#define FTM_SC_PS_MASK 0x7 |
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#define FTM_SC_PS_SHIFT 0 |
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#define FTM_CNT 0x04 |
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#define FTM_MOD 0x08 |
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#define FTM_CSC_BASE 0x0C |
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#define FTM_CSC_MSB BIT(5) |
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#define FTM_CSC_MSA BIT(4) |
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#define FTM_CSC_ELSB BIT(3) |
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#define FTM_CSC_ELSA BIT(2) |
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#define FTM_CSC(_channel) (FTM_CSC_BASE + ((_channel) * 8)) |
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#define FTM_CV_BASE 0x10 |
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#define FTM_CV(_channel) (FTM_CV_BASE + ((_channel) * 8)) |
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#define FTM_CNTIN 0x4C |
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#define FTM_STATUS 0x50 |
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#define FTM_MODE 0x54 |
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#define FTM_MODE_FTMEN BIT(0) |
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#define FTM_MODE_INIT BIT(2) |
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#define FTM_MODE_PWMSYNC BIT(3) |
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#define FTM_SYNC 0x58 |
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#define FTM_OUTINIT 0x5C |
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#define FTM_OUTMASK 0x60 |
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#define FTM_COMBINE 0x64 |
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#define FTM_DEADTIME 0x68 |
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#define FTM_EXTTRIG 0x6C |
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#define FTM_POL 0x70 |
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#define FTM_FMS 0x74 |
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#define FTM_FILTER 0x78 |
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#define FTM_FLTCTRL 0x7C |
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#define FTM_QDCTRL 0x80 |
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#define FTM_CONF 0x84 |
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#define FTM_FLTPOL 0x88 |
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#define FTM_SYNCONF 0x8C |
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#define FTM_INVCTRL 0x90 |
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#define FTM_SWOCTRL 0x94 |
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#define FTM_PWMLOAD 0x98 |
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enum fsl_pwm_clk { |
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FSL_PWM_CLK_SYS, |
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FSL_PWM_CLK_FIX, |
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FSL_PWM_CLK_EXT, |
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FSL_PWM_CLK_CNTEN, |
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FSL_PWM_CLK_MAX |
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}; |
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struct fsl_pwm_chip { |
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struct pwm_chip chip; |
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struct mutex lock; |
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unsigned int use_count; |
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unsigned int cnt_select; |
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unsigned int clk_ps; |
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void __iomem *base; |
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int period_ns; |
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struct clk *clk[FSL_PWM_CLK_MAX]; |
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}; |
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|
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static inline struct fsl_pwm_chip *to_fsl_chip(struct pwm_chip *chip) |
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{ |
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return container_of(chip, struct fsl_pwm_chip, chip); |
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} |
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|
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static int fsl_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
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|
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return clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); |
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} |
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|
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static void fsl_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm) |
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{ |
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struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
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|
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clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); |
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} |
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|
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static int fsl_pwm_calculate_default_ps(struct fsl_pwm_chip *fpc, |
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enum fsl_pwm_clk index) |
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{ |
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unsigned long sys_rate, cnt_rate; |
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unsigned long long ratio; |
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|
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sys_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_SYS]); |
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if (!sys_rate) |
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return -EINVAL; |
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|
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cnt_rate = clk_get_rate(fpc->clk[fpc->cnt_select]); |
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if (!cnt_rate) |
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return -EINVAL; |
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|
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switch (index) { |
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case FSL_PWM_CLK_SYS: |
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fpc->clk_ps = 1; |
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break; |
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case FSL_PWM_CLK_FIX: |
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ratio = 2 * cnt_rate - 1; |
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do_div(ratio, sys_rate); |
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fpc->clk_ps = ratio; |
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break; |
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case FSL_PWM_CLK_EXT: |
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ratio = 4 * cnt_rate - 1; |
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do_div(ratio, sys_rate); |
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fpc->clk_ps = ratio; |
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break; |
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default: |
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return -EINVAL; |
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} |
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|
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return 0; |
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} |
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|
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static unsigned long fsl_pwm_calculate_cycles(struct fsl_pwm_chip *fpc, |
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unsigned long period_ns) |
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{ |
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unsigned long long c, c0; |
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|
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c = clk_get_rate(fpc->clk[fpc->cnt_select]); |
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c = c * period_ns; |
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do_div(c, 1000000000UL); |
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|
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do { |
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c0 = c; |
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do_div(c0, (1 << fpc->clk_ps)); |
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if (c0 <= 0xFFFF) |
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return (unsigned long)c0; |
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} while (++fpc->clk_ps < 8); |
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|
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return 0; |
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} |
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|
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static unsigned long fsl_pwm_calculate_period_cycles(struct fsl_pwm_chip *fpc, |
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unsigned long period_ns, |
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enum fsl_pwm_clk index) |
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{ |
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int ret; |
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|
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ret = fsl_pwm_calculate_default_ps(fpc, index); |
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if (ret) { |
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dev_err(fpc->chip.dev, |
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"failed to calculate default prescaler: %d\n", |
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ret); |
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return 0; |
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} |
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|
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return fsl_pwm_calculate_cycles(fpc, period_ns); |
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} |
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|
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static unsigned long fsl_pwm_calculate_period(struct fsl_pwm_chip *fpc, |
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unsigned long period_ns) |
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{ |
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enum fsl_pwm_clk m0, m1; |
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unsigned long fix_rate, ext_rate, cycles; |
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|
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cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, |
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FSL_PWM_CLK_SYS); |
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if (cycles) { |
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fpc->cnt_select = FSL_PWM_CLK_SYS; |
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return cycles; |
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} |
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|
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fix_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_FIX]); |
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ext_rate = clk_get_rate(fpc->clk[FSL_PWM_CLK_EXT]); |
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|
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if (fix_rate > ext_rate) { |
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m0 = FSL_PWM_CLK_FIX; |
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m1 = FSL_PWM_CLK_EXT; |
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} else { |
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m0 = FSL_PWM_CLK_EXT; |
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m1 = FSL_PWM_CLK_FIX; |
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} |
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|
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cycles = fsl_pwm_calculate_period_cycles(fpc, period_ns, m0); |
||||
if (cycles) { |
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fpc->cnt_select = m0; |
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return cycles; |
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} |
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|
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fpc->cnt_select = m1; |
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|
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return fsl_pwm_calculate_period_cycles(fpc, period_ns, m1); |
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} |
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|
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static unsigned long fsl_pwm_calculate_duty(struct fsl_pwm_chip *fpc, |
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unsigned long period_ns, |
||||
unsigned long duty_ns) |
||||
{ |
||||
unsigned long long val, duty; |
||||
|
||||
val = readl(fpc->base + FTM_MOD); |
||||
duty = duty_ns * (val + 1); |
||||
do_div(duty, period_ns); |
||||
|
||||
return (unsigned long)duty; |
||||
} |
||||
|
||||
static int fsl_pwm_config(struct pwm_chip *chip, struct pwm_device *pwm, |
||||
int duty_ns, int period_ns) |
||||
{ |
||||
struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
||||
u32 val, period, duty; |
||||
|
||||
mutex_lock(&fpc->lock); |
||||
|
||||
/*
|
||||
* The Freescale FTM controller supports only a single period for |
||||
* all PWM channels, therefore incompatible changes need to be |
||||
* refused. |
||||
*/ |
||||
if (fpc->period_ns && fpc->period_ns != period_ns) { |
||||
dev_err(fpc->chip.dev, |
||||
"conflicting period requested for PWM %u\n", |
||||
pwm->hwpwm); |
||||
mutex_unlock(&fpc->lock); |
||||
return -EBUSY; |
||||
} |
||||
|
||||
if (!fpc->period_ns && duty_ns) { |
||||
period = fsl_pwm_calculate_period(fpc, period_ns); |
||||
if (!period) { |
||||
dev_err(fpc->chip.dev, "failed to calculate period\n"); |
||||
mutex_unlock(&fpc->lock); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
val = readl(fpc->base + FTM_SC); |
||||
val &= ~(FTM_SC_PS_MASK << FTM_SC_PS_SHIFT); |
||||
val |= fpc->clk_ps; |
||||
writel(val, fpc->base + FTM_SC); |
||||
writel(period - 1, fpc->base + FTM_MOD); |
||||
|
||||
fpc->period_ns = period_ns; |
||||
} |
||||
|
||||
mutex_unlock(&fpc->lock); |
||||
|
||||
duty = fsl_pwm_calculate_duty(fpc, period_ns, duty_ns); |
||||
|
||||
writel(FTM_CSC_MSB | FTM_CSC_ELSB, fpc->base + FTM_CSC(pwm->hwpwm)); |
||||
writel(duty, fpc->base + FTM_CV(pwm->hwpwm)); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int fsl_pwm_set_polarity(struct pwm_chip *chip, |
||||
struct pwm_device *pwm, |
||||
enum pwm_polarity polarity) |
||||
{ |
||||
struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
||||
u32 val; |
||||
|
||||
val = readl(fpc->base + FTM_POL); |
||||
|
||||
if (polarity == PWM_POLARITY_INVERSED) |
||||
val |= BIT(pwm->hwpwm); |
||||
else |
||||
val &= ~BIT(pwm->hwpwm); |
||||
|
||||
writel(val, fpc->base + FTM_POL); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int fsl_counter_clock_enable(struct fsl_pwm_chip *fpc) |
||||
{ |
||||
u32 val; |
||||
int ret; |
||||
|
||||
if (fpc->use_count != 0) |
||||
return 0; |
||||
|
||||
/* select counter clock source */ |
||||
val = readl(fpc->base + FTM_SC); |
||||
val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); |
||||
val |= FTM_SC_CLK(fpc->cnt_select); |
||||
writel(val, fpc->base + FTM_SC); |
||||
|
||||
ret = clk_prepare_enable(fpc->clk[fpc->cnt_select]); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_CNTEN]); |
||||
if (ret) { |
||||
clk_disable_unprepare(fpc->clk[fpc->cnt_select]); |
||||
return ret; |
||||
} |
||||
|
||||
fpc->use_count++; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int fsl_pwm_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
||||
{ |
||||
struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
||||
u32 val; |
||||
int ret; |
||||
|
||||
mutex_lock(&fpc->lock); |
||||
val = readl(fpc->base + FTM_OUTMASK); |
||||
val &= ~BIT(pwm->hwpwm); |
||||
writel(val, fpc->base + FTM_OUTMASK); |
||||
|
||||
ret = fsl_counter_clock_enable(fpc); |
||||
mutex_unlock(&fpc->lock); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void fsl_counter_clock_disable(struct fsl_pwm_chip *fpc) |
||||
{ |
||||
u32 val; |
||||
|
||||
/*
|
||||
* already disabled, do nothing |
||||
*/ |
||||
if (fpc->use_count == 0) |
||||
return; |
||||
|
||||
/* there are still users, so can't disable yet */ |
||||
if (--fpc->use_count > 0) |
||||
return; |
||||
|
||||
/* no users left, disable PWM counter clock */ |
||||
val = readl(fpc->base + FTM_SC); |
||||
val &= ~(FTM_SC_CLK_MASK << FTM_SC_CLK_SHIFT); |
||||
writel(val, fpc->base + FTM_SC); |
||||
|
||||
clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_CNTEN]); |
||||
clk_disable_unprepare(fpc->clk[fpc->cnt_select]); |
||||
} |
||||
|
||||
static void fsl_pwm_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
||||
{ |
||||
struct fsl_pwm_chip *fpc = to_fsl_chip(chip); |
||||
u32 val; |
||||
|
||||
mutex_lock(&fpc->lock); |
||||
val = readl(fpc->base + FTM_OUTMASK); |
||||
val |= BIT(pwm->hwpwm); |
||||
writel(val, fpc->base + FTM_OUTMASK); |
||||
|
||||
fsl_counter_clock_disable(fpc); |
||||
|
||||
val = readl(fpc->base + FTM_OUTMASK); |
||||
|
||||
if ((val & 0xFF) == 0xFF) |
||||
fpc->period_ns = 0; |
||||
|
||||
mutex_unlock(&fpc->lock); |
||||
} |
||||
|
||||
static const struct pwm_ops fsl_pwm_ops = { |
||||
.request = fsl_pwm_request, |
||||
.free = fsl_pwm_free, |
||||
.config = fsl_pwm_config, |
||||
.set_polarity = fsl_pwm_set_polarity, |
||||
.enable = fsl_pwm_enable, |
||||
.disable = fsl_pwm_disable, |
||||
.owner = THIS_MODULE, |
||||
}; |
||||
|
||||
static int fsl_pwm_init(struct fsl_pwm_chip *fpc) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = clk_prepare_enable(fpc->clk[FSL_PWM_CLK_SYS]); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
writel(0x00, fpc->base + FTM_CNTIN); |
||||
writel(0x00, fpc->base + FTM_OUTINIT); |
||||
writel(0xFF, fpc->base + FTM_OUTMASK); |
||||
|
||||
clk_disable_unprepare(fpc->clk[FSL_PWM_CLK_SYS]); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int fsl_pwm_probe(struct platform_device *pdev) |
||||
{ |
||||
struct fsl_pwm_chip *fpc; |
||||
struct resource *res; |
||||
int ret; |
||||
|
||||
fpc = devm_kzalloc(&pdev->dev, sizeof(*fpc), GFP_KERNEL); |
||||
if (!fpc) |
||||
return -ENOMEM; |
||||
|
||||
mutex_init(&fpc->lock); |
||||
|
||||
fpc->chip.dev = &pdev->dev; |
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
fpc->base = devm_ioremap_resource(&pdev->dev, res); |
||||
if (IS_ERR(fpc->base)) |
||||
return PTR_ERR(fpc->base); |
||||
|
||||
fpc->clk[FSL_PWM_CLK_SYS] = devm_clk_get(&pdev->dev, "ftm_sys"); |
||||
if (IS_ERR(fpc->clk[FSL_PWM_CLK_SYS])) { |
||||
dev_err(&pdev->dev, "failed to get \"ftm_sys\" clock\n"); |
||||
return PTR_ERR(fpc->clk[FSL_PWM_CLK_SYS]); |
||||
} |
||||
|
||||
fpc->clk[FSL_PWM_CLK_FIX] = devm_clk_get(fpc->chip.dev, "ftm_fix"); |
||||
if (IS_ERR(fpc->clk[FSL_PWM_CLK_FIX])) |
||||
return PTR_ERR(fpc->clk[FSL_PWM_CLK_FIX]); |
||||
|
||||
fpc->clk[FSL_PWM_CLK_EXT] = devm_clk_get(fpc->chip.dev, "ftm_ext"); |
||||
if (IS_ERR(fpc->clk[FSL_PWM_CLK_EXT])) |
||||
return PTR_ERR(fpc->clk[FSL_PWM_CLK_EXT]); |
||||
|
||||
fpc->clk[FSL_PWM_CLK_CNTEN] = |
||||
devm_clk_get(fpc->chip.dev, "ftm_cnt_clk_en"); |
||||
if (IS_ERR(fpc->clk[FSL_PWM_CLK_CNTEN])) |
||||
return PTR_ERR(fpc->clk[FSL_PWM_CLK_CNTEN]); |
||||
|
||||
fpc->chip.ops = &fsl_pwm_ops; |
||||
fpc->chip.of_xlate = of_pwm_xlate_with_flags; |
||||
fpc->chip.of_pwm_n_cells = 3; |
||||
fpc->chip.base = -1; |
||||
fpc->chip.npwm = 8; |
||||
|
||||
ret = pwmchip_add(&fpc->chip); |
||||
if (ret < 0) { |
||||
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
platform_set_drvdata(pdev, fpc); |
||||
|
||||
return fsl_pwm_init(fpc); |
||||
} |
||||
|
||||
static int fsl_pwm_remove(struct platform_device *pdev) |
||||
{ |
||||
struct fsl_pwm_chip *fpc = platform_get_drvdata(pdev); |
||||
|
||||
return pwmchip_remove(&fpc->chip); |
||||
} |
||||
|
||||
static const struct of_device_id fsl_pwm_dt_ids[] = { |
||||
{ .compatible = "fsl,vf610-ftm-pwm", }, |
||||
{ /* sentinel */ } |
||||
}; |
||||
MODULE_DEVICE_TABLE(of, fsl_pwm_dt_ids); |
||||
|
||||
static struct platform_driver fsl_pwm_driver = { |
||||
.driver = { |
||||
.name = "fsl-ftm-pwm", |
||||
.of_match_table = fsl_pwm_dt_ids, |
||||
}, |
||||
.probe = fsl_pwm_probe, |
||||
.remove = fsl_pwm_remove, |
||||
}; |
||||
module_platform_driver(fsl_pwm_driver); |
||||
|
||||
MODULE_DESCRIPTION("Freescale FlexTimer Module PWM Driver"); |
||||
MODULE_AUTHOR("Xiubo Li <Li.Xiubo@freescale.com>"); |
||||
MODULE_ALIAS("platform:fsl-ftm-pwm"); |
||||
MODULE_LICENSE("GPL"); |
||||
@ -0,0 +1,183 @@ |
||||
/*
|
||||
* Intel Low Power Subsystem PWM controller driver |
||||
* |
||||
* Copyright (C) 2014, Intel Corporation |
||||
* Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
||||
* Author: Chew Kean Ho <kean.ho.chew@intel.com> |
||||
* Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
||||
* Author: Chew Chiau Ee <chiau.ee.chew@intel.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#include <linux/acpi.h> |
||||
#include <linux/clk.h> |
||||
#include <linux/device.h> |
||||
#include <linux/kernel.h> |
||||
#include <linux/module.h> |
||||
#include <linux/pwm.h> |
||||
#include <linux/platform_device.h> |
||||
|
||||
#define PWM 0x00000000 |
||||
#define PWM_ENABLE BIT(31) |
||||
#define PWM_SW_UPDATE BIT(30) |
||||
#define PWM_BASE_UNIT_SHIFT 8 |
||||
#define PWM_BASE_UNIT_MASK 0x00ffff00 |
||||
#define PWM_ON_TIME_DIV_MASK 0x000000ff |
||||
#define PWM_DIVISION_CORRECTION 0x2 |
||||
#define PWM_LIMIT (0x8000 + PWM_DIVISION_CORRECTION) |
||||
#define NSECS_PER_SEC 1000000000UL |
||||
|
||||
struct pwm_lpss_chip { |
||||
struct pwm_chip chip; |
||||
void __iomem *regs; |
||||
struct clk *clk; |
||||
}; |
||||
|
||||
static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
||||
{ |
||||
return container_of(chip, struct pwm_lpss_chip, chip); |
||||
} |
||||
|
||||
static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
||||
int duty_ns, int period_ns) |
||||
{ |
||||
struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
||||
u8 on_time_div; |
||||
unsigned long c; |
||||
unsigned long long base_unit, freq = NSECS_PER_SEC; |
||||
u32 ctrl; |
||||
|
||||
do_div(freq, period_ns); |
||||
|
||||
/* The equation is: base_unit = ((freq / c) * 65536) + correction */ |
||||
base_unit = freq * 65536; |
||||
|
||||
c = clk_get_rate(lpwm->clk); |
||||
if (!c) |
||||
return -EINVAL; |
||||
|
||||
do_div(base_unit, c); |
||||
base_unit += PWM_DIVISION_CORRECTION; |
||||
if (base_unit > PWM_LIMIT) |
||||
return -EINVAL; |
||||
|
||||
if (duty_ns <= 0) |
||||
duty_ns = 1; |
||||
on_time_div = 255 - (255 * duty_ns / period_ns); |
||||
|
||||
ctrl = readl(lpwm->regs + PWM); |
||||
ctrl &= ~(PWM_BASE_UNIT_MASK | PWM_ON_TIME_DIV_MASK); |
||||
ctrl |= (u16) base_unit << PWM_BASE_UNIT_SHIFT; |
||||
ctrl |= on_time_div; |
||||
/* request PWM to update on next cycle */ |
||||
ctrl |= PWM_SW_UPDATE; |
||||
writel(ctrl, lpwm->regs + PWM); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
||||
{ |
||||
struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
||||
u32 ctrl; |
||||
int ret; |
||||
|
||||
ret = clk_prepare_enable(lpwm->clk); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ctrl = readl(lpwm->regs + PWM); |
||||
writel(ctrl | PWM_ENABLE, lpwm->regs + PWM); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
||||
{ |
||||
struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
||||
u32 ctrl; |
||||
|
||||
ctrl = readl(lpwm->regs + PWM); |
||||
writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); |
||||
|
||||
clk_disable_unprepare(lpwm->clk); |
||||
} |
||||
|
||||
static const struct pwm_ops pwm_lpss_ops = { |
||||
.config = pwm_lpss_config, |
||||
.enable = pwm_lpss_enable, |
||||
.disable = pwm_lpss_disable, |
||||
.owner = THIS_MODULE, |
||||
}; |
||||
|
||||
static const struct acpi_device_id pwm_lpss_acpi_match[] = { |
||||
{ "80860F09", 0 }, |
||||
{ }, |
||||
}; |
||||
MODULE_DEVICE_TABLE(acpi, pwm_lpss_acpi_match); |
||||
|
||||
static int pwm_lpss_probe(struct platform_device *pdev) |
||||
{ |
||||
struct pwm_lpss_chip *lpwm; |
||||
struct resource *r; |
||||
int ret; |
||||
|
||||
lpwm = devm_kzalloc(&pdev->dev, sizeof(*lpwm), GFP_KERNEL); |
||||
if (!lpwm) |
||||
return -ENOMEM; |
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
|
||||
lpwm->regs = devm_ioremap_resource(&pdev->dev, r); |
||||
if (IS_ERR(lpwm->regs)) |
||||
return PTR_ERR(lpwm->regs); |
||||
|
||||
lpwm->clk = devm_clk_get(&pdev->dev, NULL); |
||||
if (IS_ERR(lpwm->clk)) { |
||||
dev_err(&pdev->dev, "failed to get PWM clock\n"); |
||||
return PTR_ERR(lpwm->clk); |
||||
} |
||||
|
||||
lpwm->chip.dev = &pdev->dev; |
||||
lpwm->chip.ops = &pwm_lpss_ops; |
||||
lpwm->chip.base = -1; |
||||
lpwm->chip.npwm = 1; |
||||
|
||||
ret = pwmchip_add(&lpwm->chip); |
||||
if (ret) { |
||||
dev_err(&pdev->dev, "failed to add PWM chip: %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
platform_set_drvdata(pdev, lpwm); |
||||
return 0; |
||||
} |
||||
|
||||
static int pwm_lpss_remove(struct platform_device *pdev) |
||||
{ |
||||
struct pwm_lpss_chip *lpwm = platform_get_drvdata(pdev); |
||||
u32 ctrl; |
||||
|
||||
ctrl = readl(lpwm->regs + PWM); |
||||
writel(ctrl & ~PWM_ENABLE, lpwm->regs + PWM); |
||||
|
||||
return pwmchip_remove(&lpwm->chip); |
||||
} |
||||
|
||||
static struct platform_driver pwm_lpss_driver = { |
||||
.driver = { |
||||
.name = "pwm-lpss", |
||||
.acpi_match_table = pwm_lpss_acpi_match, |
||||
}, |
||||
.probe = pwm_lpss_probe, |
||||
.remove = pwm_lpss_remove, |
||||
}; |
||||
module_platform_driver(pwm_lpss_driver); |
||||
|
||||
MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
||||
MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
MODULE_ALIAS("platform:pwm-lpss"); |
||||
Loading…
Reference in new issue