This patch introduces the SAMA5 support and a generic board file for SAMA5 devices. It also updates the PMC driver to manage clock division which is a requirement since some peripherals can't work at the bus frequency on SAMA5. Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>tirimbino
Ludovic Desroches
12 years ago
committed by
Nicolas Ferre
parent
8f0cdcc570
commit
8f4b47949f
@ -0,0 +1,86 @@ |
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/*
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* Setup code for SAMA5 Evaluation Kits with Device Tree support |
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* |
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* Copyright (C) 2013 Atmel, |
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* 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
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* |
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* Licensed under GPLv2 or later. |
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*/ |
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#include <linux/types.h> |
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#include <linux/init.h> |
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#include <linux/module.h> |
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#include <linux/gpio.h> |
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#include <linux/micrel_phy.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_platform.h> |
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#include <linux/phy.h> |
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#include <asm/setup.h> |
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#include <asm/irq.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include <asm/mach/irq.h> |
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#include "at91_aic.h" |
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#include "generic.h" |
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static const struct of_device_id irq_of_match[] __initconst = { |
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{ .compatible = "atmel,sama5d3-aic", .data = at91_aic5_of_init }, |
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{ /*sentinel*/ } |
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}; |
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static void __init at91_dt_init_irq(void) |
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{ |
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of_irq_init(irq_of_match); |
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} |
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static int ksz9021rn_phy_fixup(struct phy_device *phy) |
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{ |
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int value; |
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#define GMII_RCCPSR 260 |
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#define GMII_RRDPSR 261 |
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#define GMII_ERCR 11 |
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#define GMII_ERDWR 12 |
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/* Set delay values */ |
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value = GMII_RCCPSR | 0x8000; |
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phy_write(phy, GMII_ERCR, value); |
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value = 0xF2F4; |
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phy_write(phy, GMII_ERDWR, value); |
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value = GMII_RRDPSR | 0x8000; |
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phy_write(phy, GMII_ERCR, value); |
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value = 0x2222; |
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phy_write(phy, GMII_ERDWR, value); |
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return 0; |
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} |
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static void __init sama5_dt_device_init(void) |
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{ |
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if (of_machine_is_compatible("atmel,sama5d3xcm")) |
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phy_register_fixup_for_uid(PHY_ID_KSZ9021, MICREL_PHY_ID_MASK, |
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ksz9021rn_phy_fixup); |
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of_platform_populate(NULL, of_default_bus_match_table, NULL, NULL); |
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} |
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static const char *sama5_dt_board_compat[] __initdata = { |
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"atmel,sama5", |
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NULL |
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}; |
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DT_MACHINE_START(sama5_dt, "Atmel SAMA5 (Device Tree)") |
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/* Maintainer: Atmel */ |
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.init_time = at91sam926x_pit_init, |
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.map_io = at91_map_io, |
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.handle_irq = at91_aic5_handle_irq, |
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.init_early = at91_dt_initialize, |
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.init_irq = at91_dt_init_irq, |
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.init_machine = sama5_dt_device_init, |
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.dt_compat = sama5_dt_board_compat, |
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MACHINE_END |
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@ -0,0 +1,73 @@ |
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/*
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* Chip-specific header file for the SAMA5D3 family |
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* |
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* Copyright (C) 2013 Atmel, |
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* 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
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* |
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* Common definitions. |
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* Based on SAMA5D3 datasheet. |
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* |
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* Licensed under GPLv2 or later. |
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*/ |
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#ifndef SAMA5D3_H |
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#define SAMA5D3_H |
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/*
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* Peripheral identifiers/interrupts. |
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*/ |
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#define AT91_ID_FIQ 0 /* Advanced Interrupt Controller (FIQ) */ |
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#define AT91_ID_SYS 1 /* System Peripherals */ |
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#define SAMA5D3_ID_DBGU 2 /* debug Unit (usually no special interrupt line) */ |
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#define AT91_ID_PIT 3 /* PIT */ |
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#define SAMA5D3_ID_WDT 4 /* Watchdog Timer Interrupt */ |
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#define SAMA5D3_ID_HSMC 5 /* Static Memory Controller */ |
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#define SAMA5D3_ID_PIOA 6 /* PIOA */ |
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#define SAMA5D3_ID_PIOB 7 /* PIOB */ |
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#define SAMA5D3_ID_PIOC 8 /* PIOC */ |
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#define SAMA5D3_ID_PIOD 9 /* PIOD */ |
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#define SAMA5D3_ID_PIOE 10 /* PIOE */ |
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#define SAMA5D3_ID_SMD 11 /* SMD Soft Modem */ |
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#define SAMA5D3_ID_USART0 12 /* USART0 */ |
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#define SAMA5D3_ID_USART1 13 /* USART1 */ |
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#define SAMA5D3_ID_USART2 14 /* USART2 */ |
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#define SAMA5D3_ID_USART3 15 /* USART3 */ |
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#define SAMA5D3_ID_UART0 16 /* UART 0 */ |
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#define SAMA5D3_ID_UART1 17 /* UART 1 */ |
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#define SAMA5D3_ID_TWI0 18 /* Two-Wire Interface 0 */ |
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#define SAMA5D3_ID_TWI1 19 /* Two-Wire Interface 1 */ |
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#define SAMA5D3_ID_TWI2 20 /* Two-Wire Interface 2 */ |
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#define SAMA5D3_ID_HSMCI0 21 /* MCI */ |
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#define SAMA5D3_ID_HSMCI1 22 /* MCI */ |
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#define SAMA5D3_ID_HSMCI2 23 /* MCI */ |
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#define SAMA5D3_ID_SPI0 24 /* Serial Peripheral Interface 0 */ |
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#define SAMA5D3_ID_SPI1 25 /* Serial Peripheral Interface 1 */ |
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#define SAMA5D3_ID_TC0 26 /* Timer Counter 0 */ |
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#define SAMA5D3_ID_TC1 27 /* Timer Counter 2 */ |
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#define SAMA5D3_ID_PWM 28 /* Pulse Width Modulation Controller */ |
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#define SAMA5D3_ID_ADC 29 /* Touch Screen ADC Controller */ |
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#define SAMA5D3_ID_DMA0 30 /* DMA Controller 0 */ |
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#define SAMA5D3_ID_DMA1 31 /* DMA Controller 1 */ |
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#define SAMA5D3_ID_UHPHS 32 /* USB Host High Speed */ |
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#define SAMA5D3_ID_UDPHS 33 /* USB Device High Speed */ |
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#define SAMA5D3_ID_GMAC 34 /* Gigabit Ethernet MAC */ |
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#define SAMA5D3_ID_EMAC 35 /* Ethernet MAC */ |
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#define SAMA5D3_ID_LCDC 36 /* LCD Controller */ |
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#define SAMA5D3_ID_ISI 37 /* Image Sensor Interface */ |
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#define SAMA5D3_ID_SSC0 38 /* Synchronous Serial Controller 0 */ |
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#define SAMA5D3_ID_SSC1 39 /* Synchronous Serial Controller 1 */ |
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#define SAMA5D3_ID_CAN0 40 /* CAN Controller 0 */ |
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#define SAMA5D3_ID_CAN1 41 /* CAN Controller 1 */ |
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#define SAMA5D3_ID_SHA 42 /* Secure Hash Algorithm */ |
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#define SAMA5D3_ID_AES 43 /* Advanced Encryption Standard */ |
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#define SAMA5D3_ID_TDES 44 /* Triple Data Encryption Standard */ |
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#define SAMA5D3_ID_TRNG 45 /* True Random Generator Number */ |
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#define SAMA5D3_ID_IRQ0 47 /* Advanced Interrupt Controller (IRQ0) */ |
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/*
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* Internal Memory |
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*/ |
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#define SAMA5D3_SRAM_BASE 0x00300000 /* Internal SRAM base address */ |
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#define SAMA5D3_SRAM_SIZE (128 * SZ_1K) /* Internal SRAM size (128Kb) */ |
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#endif |
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@ -0,0 +1,377 @@ |
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/*
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* Chip-specific setup code for the SAMA5D3 family |
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* |
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* Copyright (C) 2013 Atmel, |
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* 2013 Ludovic Desroches <ludovic.desroches@atmel.com> |
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* |
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* Licensed under GPLv2 or later. |
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*/ |
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#include <linux/module.h> |
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#include <linux/dma-mapping.h> |
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#include <asm/irq.h> |
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#include <asm/mach/arch.h> |
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#include <asm/mach/map.h> |
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#include <mach/sama5d3.h> |
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#include <mach/at91_pmc.h> |
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#include <mach/cpu.h> |
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#include "soc.h" |
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#include "generic.h" |
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#include "clock.h" |
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#include "sam9_smc.h" |
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/* --------------------------------------------------------------------
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* Clocks |
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* -------------------------------------------------------------------- */ |
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/*
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* The peripheral clocks. |
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*/ |
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static struct clk pioA_clk = { |
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.name = "pioA_clk", |
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.pid = SAMA5D3_ID_PIOA, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk pioB_clk = { |
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.name = "pioB_clk", |
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.pid = SAMA5D3_ID_PIOB, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk pioC_clk = { |
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.name = "pioC_clk", |
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.pid = SAMA5D3_ID_PIOC, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk pioD_clk = { |
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.name = "pioD_clk", |
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.pid = SAMA5D3_ID_PIOD, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk pioE_clk = { |
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.name = "pioE_clk", |
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.pid = SAMA5D3_ID_PIOE, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk usart0_clk = { |
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.name = "usart0_clk", |
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.pid = SAMA5D3_ID_USART0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk usart1_clk = { |
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.name = "usart1_clk", |
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.pid = SAMA5D3_ID_USART1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk usart2_clk = { |
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.name = "usart2_clk", |
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.pid = SAMA5D3_ID_USART2, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk usart3_clk = { |
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.name = "usart3_clk", |
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.pid = SAMA5D3_ID_USART3, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk uart0_clk = { |
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.name = "uart0_clk", |
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.pid = SAMA5D3_ID_UART0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk uart1_clk = { |
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.name = "uart1_clk", |
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.pid = SAMA5D3_ID_UART1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk twi0_clk = { |
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.name = "twi0_clk", |
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.pid = SAMA5D3_ID_TWI0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk twi1_clk = { |
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.name = "twi1_clk", |
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.pid = SAMA5D3_ID_TWI1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk twi2_clk = { |
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.name = "twi2_clk", |
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.pid = SAMA5D3_ID_TWI2, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk mmc0_clk = { |
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.name = "mci0_clk", |
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.pid = SAMA5D3_ID_HSMCI0, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk mmc1_clk = { |
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.name = "mci1_clk", |
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.pid = SAMA5D3_ID_HSMCI1, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk mmc2_clk = { |
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.name = "mci2_clk", |
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.pid = SAMA5D3_ID_HSMCI2, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk spi0_clk = { |
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.name = "spi0_clk", |
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.pid = SAMA5D3_ID_SPI0, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk spi1_clk = { |
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.name = "spi1_clk", |
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.pid = SAMA5D3_ID_SPI1, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk tcb0_clk = { |
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.name = "tcb0_clk", |
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.pid = SAMA5D3_ID_TC0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk tcb1_clk = { |
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.name = "tcb1_clk", |
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.pid = SAMA5D3_ID_TC1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk adc_clk = { |
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.name = "adc_clk", |
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.pid = SAMA5D3_ID_ADC, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk adc_op_clk = { |
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.name = "adc_op_clk", |
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.type = CLK_TYPE_PERIPHERAL, |
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.rate_hz = 5000000, |
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}; |
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static struct clk dma0_clk = { |
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.name = "dma0_clk", |
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.pid = SAMA5D3_ID_DMA0, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk dma1_clk = { |
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.name = "dma1_clk", |
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.pid = SAMA5D3_ID_DMA1, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk uhphs_clk = { |
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.name = "uhphs", |
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.pid = SAMA5D3_ID_UHPHS, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk udphs_clk = { |
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.name = "udphs_clk", |
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.pid = SAMA5D3_ID_UDPHS, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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/* gmac only for sama5d33, sama5d34, sama5d35 */ |
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static struct clk macb0_clk = { |
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.name = "macb0_clk", |
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.pid = SAMA5D3_ID_GMAC, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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/* emac only for sama5d31, sama5d35 */ |
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static struct clk macb1_clk = { |
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.name = "macb1_clk", |
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.pid = SAMA5D3_ID_EMAC, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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/* lcd only for sama5d31, sama5d33, sama5d34 */ |
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static struct clk lcdc_clk = { |
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.name = "lcdc_clk", |
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.pid = SAMA5D3_ID_LCDC, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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/* isi only for sama5d33, sama5d35 */ |
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static struct clk isi_clk = { |
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.name = "isi_clk", |
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.pid = SAMA5D3_ID_ISI, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk can0_clk = { |
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.name = "can0_clk", |
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.pid = SAMA5D3_ID_CAN0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk can1_clk = { |
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.name = "can1_clk", |
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.pid = SAMA5D3_ID_CAN1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk ssc0_clk = { |
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.name = "ssc0_clk", |
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.pid = SAMA5D3_ID_SSC0, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk ssc1_clk = { |
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.name = "ssc1_clk", |
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.pid = SAMA5D3_ID_SSC1, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV2, |
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}; |
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static struct clk sha_clk = { |
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.name = "sha_clk", |
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.pid = SAMA5D3_ID_SHA, |
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.type = CLK_TYPE_PERIPHERAL, |
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.div = AT91_PMC_PCR_DIV8, |
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}; |
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static struct clk aes_clk = { |
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.name = "aes_clk", |
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.pid = SAMA5D3_ID_AES, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk tdes_clk = { |
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.name = "tdes_clk", |
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.pid = SAMA5D3_ID_TDES, |
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.type = CLK_TYPE_PERIPHERAL, |
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}; |
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static struct clk *periph_clocks[] __initdata = { |
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&pioA_clk, |
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&pioB_clk, |
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&pioC_clk, |
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&pioD_clk, |
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&pioE_clk, |
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&usart0_clk, |
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&usart1_clk, |
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&usart2_clk, |
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&usart3_clk, |
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&uart0_clk, |
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&uart1_clk, |
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&twi0_clk, |
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&twi1_clk, |
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&twi2_clk, |
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&mmc0_clk, |
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&mmc1_clk, |
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&mmc2_clk, |
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&spi0_clk, |
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&spi1_clk, |
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&tcb0_clk, |
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&tcb1_clk, |
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&adc_clk, |
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&adc_op_clk, |
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&dma0_clk, |
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&dma1_clk, |
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&uhphs_clk, |
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&udphs_clk, |
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&macb0_clk, |
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&macb1_clk, |
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&lcdc_clk, |
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&isi_clk, |
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&can0_clk, |
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&can1_clk, |
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&ssc0_clk, |
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&ssc1_clk, |
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&sha_clk, |
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&aes_clk, |
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&tdes_clk, |
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}; |
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static struct clk pck0 = { |
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.name = "pck0", |
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.pmc_mask = AT91_PMC_PCK0, |
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.type = CLK_TYPE_PROGRAMMABLE, |
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.id = 0, |
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}; |
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static struct clk pck1 = { |
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.name = "pck1", |
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.pmc_mask = AT91_PMC_PCK1, |
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.type = CLK_TYPE_PROGRAMMABLE, |
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.id = 1, |
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}; |
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static struct clk pck2 = { |
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.name = "pck2", |
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.pmc_mask = AT91_PMC_PCK2, |
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.type = CLK_TYPE_PROGRAMMABLE, |
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.id = 2, |
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}; |
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|
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static struct clk_lookup periph_clocks_lookups[] = { |
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/* lookup table for DT entries */ |
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CLKDEV_CON_DEV_ID("usart", "ffffee00.serial", &mck), |
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CLKDEV_CON_DEV_ID(NULL, "fffff200.gpio", &pioA_clk), |
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CLKDEV_CON_DEV_ID(NULL, "fffff400.gpio", &pioB_clk), |
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CLKDEV_CON_DEV_ID(NULL, "fffff600.gpio", &pioC_clk), |
||||
CLKDEV_CON_DEV_ID(NULL, "fffff800.gpio", &pioD_clk), |
||||
CLKDEV_CON_DEV_ID(NULL, "fffffa00.gpio", &pioE_clk), |
||||
CLKDEV_CON_DEV_ID("usart", "f001c000.serial", &usart0_clk), |
||||
CLKDEV_CON_DEV_ID("usart", "f0020000.serial", &usart1_clk), |
||||
CLKDEV_CON_DEV_ID("usart", "f8020000.serial", &usart2_clk), |
||||
CLKDEV_CON_DEV_ID("usart", "f8024000.serial", &usart3_clk), |
||||
CLKDEV_CON_DEV_ID(NULL, "f0014000.i2c", &twi0_clk), |
||||
CLKDEV_CON_DEV_ID(NULL, "f0018000.i2c", &twi1_clk), |
||||
CLKDEV_CON_DEV_ID(NULL, "f801c000.i2c", &twi2_clk), |
||||
CLKDEV_CON_DEV_ID("mci_clk", "f0000000.mmc", &mmc0_clk), |
||||
CLKDEV_CON_DEV_ID("mci_clk", "f8000000.mmc", &mmc1_clk), |
||||
CLKDEV_CON_DEV_ID("mci_clk", "f8004000.mmc", &mmc2_clk), |
||||
CLKDEV_CON_DEV_ID("spi_clk", "f0004000.spi", &spi0_clk), |
||||
CLKDEV_CON_DEV_ID("spi_clk", "f8008000.spi", &spi1_clk), |
||||
CLKDEV_CON_DEV_ID("t0_clk", "f0010000.timer", &tcb0_clk), |
||||
CLKDEV_CON_DEV_ID("t0_clk", "f8014000.timer", &tcb1_clk), |
||||
CLKDEV_CON_DEV_ID("tsc_clk", "f8018000.tsadcc", &adc_clk), |
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffe600.dma-controller", &dma0_clk), |
||||
CLKDEV_CON_DEV_ID("dma_clk", "ffffe800.dma-controller", &dma1_clk), |
||||
CLKDEV_CON_DEV_ID("hclk", "600000.ohci", &uhphs_clk), |
||||
CLKDEV_CON_DEV_ID("ohci_clk", "600000.ohci", &uhphs_clk), |
||||
CLKDEV_CON_DEV_ID("ehci_clk", "700000.ehci", &uhphs_clk), |
||||
CLKDEV_CON_DEV_ID("pclk", "500000.gadget", &udphs_clk), |
||||
CLKDEV_CON_DEV_ID("hclk", "500000.gadget", &utmi_clk), |
||||
CLKDEV_CON_DEV_ID("hclk", "f0028000.ethernet", &macb0_clk), |
||||
CLKDEV_CON_DEV_ID("pclk", "f0028000.ethernet", &macb0_clk), |
||||
CLKDEV_CON_DEV_ID("hclk", "f802c000.ethernet", &macb1_clk), |
||||
CLKDEV_CON_DEV_ID("pclk", "f802c000.ethernet", &macb1_clk), |
||||
CLKDEV_CON_DEV_ID("pclk", "f0008000.ssc", &ssc0_clk), |
||||
CLKDEV_CON_DEV_ID("pclk", "f000c000.ssc", &ssc1_clk), |
||||
CLKDEV_CON_DEV_ID("can_clk", "f000c000.can", &can0_clk), |
||||
CLKDEV_CON_DEV_ID("can_clk", "f8010000.can", &can1_clk), |
||||
CLKDEV_CON_DEV_ID("sha_clk", "f8034000.sha", &sha_clk), |
||||
CLKDEV_CON_DEV_ID("aes_clk", "f8038000.aes", &aes_clk), |
||||
CLKDEV_CON_DEV_ID("tdes_clk", "f803c000.tdes", &tdes_clk), |
||||
}; |
||||
|
||||
static void __init sama5d3_register_clocks(void) |
||||
{ |
||||
int i; |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(periph_clocks); i++) |
||||
clk_register(periph_clocks[i]); |
||||
|
||||
clkdev_add_table(periph_clocks_lookups, |
||||
ARRAY_SIZE(periph_clocks_lookups)); |
||||
|
||||
clk_register(&pck0); |
||||
clk_register(&pck1); |
||||
clk_register(&pck2); |
||||
} |
||||
|
||||
/* --------------------------------------------------------------------
|
||||
* AT91SAM9x5 processor initialization |
||||
* -------------------------------------------------------------------- */ |
||||
|
||||
static void __init sama5d3_map_io(void) |
||||
{ |
||||
at91_init_sram(0, SAMA5D3_SRAM_BASE, SAMA5D3_SRAM_SIZE); |
||||
} |
||||
|
||||
AT91_SOC_START(sama5d3) |
||||
.map_io = sama5d3_map_io, |
||||
.register_clocks = sama5d3_register_clocks, |
||||
AT91_SOC_END |
||||
Loading…
Reference in new issue