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@ -15,27 +15,17 @@ |
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defined(CONFIG_CPU_SUBTYPE_SH7709) |
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# define SCPCR 0xA4000116 /* 16 bit SCI and SCIF */ |
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# define SCPDR 0xA4000136 /* 8 bit SCI and SCIF */ |
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) |
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# define SCIF0 0xA4400000 |
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# define SCIF2 0xA4410000 |
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# define SCSMR_Ir 0xA44A0000 |
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# define IRDA_SCIF SCIF0 |
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# define SCPCR 0xA4000116 |
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# define SCPDR 0xA4000136 |
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/* Set the clock source,
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* SCIF2 (0xA4410000) -> External clock, SCK pin used as clock input |
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* SCIF0 (0xA4400000) -> Internal clock, SCK pin as serial clock output |
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*/ |
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# define SCSCR_INIT(port) (port->mapbase == SCIF2) ? 0xF3 : 0xF0 |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7720) || \ |
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) |
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# define SCSCR_INIT(port) 0x0030 /* TIE=0,RIE=0,TE=1,RE=1 */ |
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# define PORT_PTCR 0xA405011EUL |
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# define PORT_PVCR 0xA4050122UL |
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# define SCIF_ORER 0x0200 /* overrun error bit */ |
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@ -43,7 +33,6 @@ |
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# define SCSPTR1 0xFFE0001C /* 8 bit SCIF */ |
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
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defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
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defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
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@ -53,39 +42,31 @@ |
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# define SCSPTR1 0xffe0001c /* 8 bit SCI */ |
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# define SCSPTR2 0xFFE80020 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) (((port)->type == PORT_SCI) ? \ |
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7760) |
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# define SCSPTR0 0xfe600024 /* 16 bit SCIF */ |
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# define SCSPTR1 0xfe610024 /* 16 bit SCIF */ |
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# define SCSPTR2 0xfe620024 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7710) || defined(CONFIG_CPU_SUBTYPE_SH7712) |
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# define SCSPTR0 0xA4400000 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define PACR 0xa4050100 |
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# define PBCR 0xa4050102 |
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# define SCSCR_INIT(port) 0x3B |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7343) |
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# define SCSPTR0 0xffe00010 /* 16 bit SCIF */ |
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# define SCSPTR1 0xffe10010 /* 16 bit SCIF */ |
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# define SCSPTR2 0xffe20010 /* 16 bit SCIF */ |
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# define SCSPTR3 0xffe30010 /* 16 bit SCIF */ |
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# define SCSCR_INIT(port) 0x32 /* TIE=0,RIE=0,TE=1,RE=1,REIE=0,CKE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7722) |
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# define PADR 0xA4050120 |
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# define PSDR 0xA405013e |
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# define PWDR 0xA4050166 |
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# define PSCR 0xA405011E |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7366) |
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# define SCPDR0 0xA405013E /* 16 bit SCIF0 PSDR */ |
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# define SCSPTR0 SCPDR0 |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) |
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# define SCSPTR0 0xa4050160 |
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# define SCSPTR1 0xa405013e |
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@ -94,62 +75,38 @@ |
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# define SCSPTR4 0xa4050128 |
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# define SCSPTR5 0xa4050128 |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x0038 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) ((port)->type == PORT_SCIFA ? \ |
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0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ : \
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0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ ) |
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#elif defined(CONFIG_CPU_SUBTYPE_SH4_202) |
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# define SCSPTR2 0xffe80020 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_CPU_SUBTYPE_SH5_101) || defined(CONFIG_CPU_SUBTYPE_SH5_103) |
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# define SCIF_BASE_ADDR 0x01030000 |
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# define SCIF_ADDR_SH5 PHYS_PERIPHERAL_BLOCK+SCIF_BASE_ADDR |
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# define SCIF_PTR2_OFFS 0x0000020 |
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# define SCIF_LSR2_OFFS 0x0000024 |
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# define SCSPTR2 ((port->mapbase)+SCIF_PTR2_OFFS) /* 16 bit SCIF */ |
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# define SCLSR2 ((port->mapbase)+SCIF_LSR2_OFFS) /* 16 bit SCIF */ |
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# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0, TE=1,RE=1,REIE=1 */ |
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#elif defined(CONFIG_H83007) || defined(CONFIG_H83068) |
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# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
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# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
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#elif defined(CONFIG_H8S2678) |
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|
|
# define SCSCR_INIT(port) 0x30 /* TIE=0,RIE=0,TE=1,RE=1 */ |
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|
# define H8300_SCI_DR(ch) *(volatile char *)(P1DR + h8300_sci_pins[ch].port) |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7757) |
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# define SCSPTR0 0xfe4b0020 |
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# define SCSPTR1 0xfe4b0020 |
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# define SCSPTR2 0xfe4b0020 |
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# define SCIF_ORER 0x0001 |
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# define SCSCR_INIT(port) 0x38 |
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# define SCIF_ONLY |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
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|
|
# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
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|
|
# define SCSPTR1 0xffe08024 /* 16 bit SCIF */ |
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|
# define SCSPTR2 0xffe10020 /* 16 bit SCIF/IRDA */ |
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|
# define SCIF_ORER 0x0001 /* overrun error bit */ |
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|
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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|
#elif defined(CONFIG_CPU_SUBTYPE_SH7770) |
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|
# define SCSPTR0 0xff923020 /* 16 bit SCIF */ |
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# define SCSPTR1 0xff924020 /* 16 bit SCIF */ |
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# define SCSPTR2 0xff925020 /* 16 bit SCIF */ |
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# define SCIF_ORER 0x0001 /* overrun error bit */ |
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|
# define SCSCR_INIT(port) 0x3c /* TIE=0,RIE=0,TE=1,RE=1,REIE=1,cke=2 */ |
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|
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#elif defined(CONFIG_CPU_SUBTYPE_SH7780) |
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# define SCSPTR0 0xffe00024 /* 16 bit SCIF */ |
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|
# define SCSPTR1 0xffe10024 /* 16 bit SCIF */ |
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|
# define SCIF_ORER 0x0001 /* Overrun error bit */ |
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|
#if defined(CONFIG_SH_SH2007) |
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|
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=0 */ |
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|
|
# define SCSCR_INIT(port) 0x38 |
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|
#else |
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|
/* TIE=0,RIE=0,TE=1,RE=1,REIE=1,CKE1=1 */ |
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|
# define SCSCR_INIT(port) 0x3a |
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|
#endif |
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|
#elif defined(CONFIG_CPU_SUBTYPE_SH7785) || \ |
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7786) |
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|
|
# define SCSPTR0 0xffea0024 /* 16 bit SCIF */ |
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|
@ -159,7 +116,6 @@ |
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|
# define SCSPTR4 0xffee0024 /* 16 bit SCIF */ |
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|
# define SCSPTR5 0xffef0024 /* 16 bit SCIF */ |
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|
|
# define SCIF_ORER 0x0001 /* Overrun error bit */ |
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|
|
# define SCSCR_INIT(port) 0x3a /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7201) || \ |
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7203) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7206) || \
|
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|
|
@ -174,52 +130,21 @@ |
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|
|
# define SCSPTR6 0xfffeB020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR7 0xfffeB820 /* 16 bit SCIF */ |
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|
|
# endif |
|
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|
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7619) |
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|
|
# define SCSPTR0 0xf8400020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR1 0xf8410020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR2 0xf8420020 /* 16 bit SCIF */ |
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|
|
# define SCIF_ORER 0x0001 /* overrun error bit */ |
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|
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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|
|
#elif defined(CONFIG_CPU_SUBTYPE_SHX3) |
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|
|
# define SCSPTR0 0xffc30020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR1 0xffc40020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR2 0xffc50020 /* 16 bit SCIF */ |
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|
|
# define SCSPTR3 0xffc60020 /* 16 bit SCIF */ |
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|
|
# define SCIF_ORER 0x0001 /* Overrun error bit */ |
|
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|
|
# define SCSCR_INIT(port) 0x38 /* TIE=0,RIE=0,TE=1,RE=1,REIE=1 */ |
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|
|
#else |
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|
|
# error CPU subtype not defined |
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|
#endif |
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|
|
/* SCSCR */ |
|
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|
|
#define SCI_CTRL_FLAGS_TIE 0x80 /* all */ |
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|
|
#define SCI_CTRL_FLAGS_RIE 0x40 /* all */ |
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|
|
#define SCI_CTRL_FLAGS_TE 0x20 /* all */ |
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|
|
#define SCI_CTRL_FLAGS_RE 0x10 /* all */ |
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|
#if defined(CONFIG_CPU_SUBTYPE_SH7750) || \ |
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7091) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7750R) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7722) || \
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7750S) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7751) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7751R) || \
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7763) || \
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7780) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7785) || \
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SH7786) || \
|
|
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|
|
defined(CONFIG_CPU_SUBTYPE_SHX3) |
|
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|
|
#define SCI_CTRL_FLAGS_REIE 0x08 /* 7750 SCIF */ |
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|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7724) |
|
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|
|
#define SCI_CTRL_FLAGS_REIE ((port)->type == PORT_SCIFA ? 0 : 8) |
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|
|
#else |
|
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|
|
#define SCI_CTRL_FLAGS_REIE 0 |
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|
|
#endif |
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|
|
/* SCI_CTRL_FLAGS_MPIE 0x08 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
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|
|
/* SCI_CTRL_FLAGS_TEIE 0x04 * 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
|
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|
|
/* SCI_CTRL_FLAGS_CKE1 0x02 * all */ |
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|
|
/* SCI_CTRL_FLAGS_CKE0 0x01 * 7707 SCI/SCIF, 7708 SCI, 7709 SCI/SCIF, 7750 SCI */ |
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|
|
/* SCxSR SCI */ |
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|
|
#define SCI_TDRE 0x80 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
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|
|
#define SCI_RDRF 0x40 /* 7707 SCI, 7708 SCI, 7709 SCI, 7750 SCI */ |
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|
|
@ -300,23 +225,11 @@ |
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|
|
/* SCFCR */ |
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|
|
#define SCFCR_RFRST 0x0002 |
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|
|
#define SCFCR_TFRST 0x0004 |
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|
|
#define SCFCR_TCRST 0x4000 |
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|
|
#define SCFCR_MCE 0x0008 |
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|
|
#define SCI_MAJOR 204 |
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|
|
#define SCI_MINOR_START 8 |
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|
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|
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|
|
/* Generic serial flags */ |
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|
|
#define SCI_RX_THROTTLE 0x0000001 |
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|
|
#define SCI_MAGIC 0xbabeface |
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|
|
|
|
|
/*
|
|
|
|
|
* Events are used to schedule things to happen at timer-interrupt |
|
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|
|
* time, instead of at rs interrupt time. |
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|
|
*/ |
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|
|
#define SCI_EVENT_WRITE_WAKEUP 0 |
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|
|
|
|
|
|
#define SCI_IN(size, offset) \ |
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|
|
if ((size) == 8) { \
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|
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|
|
return ioread8(port->membase + (offset)); \
|
|
|
|
|
@ -445,8 +358,6 @@ |
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|
|
SCIF_FNS(SCSMR, 0x00, 16) |
|
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|
|
SCIF_FNS(SCBRR, 0x04, 8) |
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|
|
SCIF_FNS(SCSCR, 0x08, 16) |
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|
|
SCIF_FNS(SCTDSR, 0x0c, 8) |
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|
|
SCIF_FNS(SCFER, 0x10, 16) |
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|
|
SCIF_FNS(SCxSR, 0x14, 16) |
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|
|
SCIF_FNS(SCFCR, 0x18, 16) |
|
|
|
|
SCIF_FNS(SCFDR, 0x1c, 16) |
|
|
|
|
@ -476,8 +387,6 @@ SCIx_FNS(SCxTDR, 0x20, 8, 0x0c, 8) |
|
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|
|
SCIx_FNS(SCxSR, 0x14, 16, 0x10, 16) |
|
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|
|
SCIx_FNS(SCxRDR, 0x24, 8, 0x14, 8) |
|
|
|
|
SCIx_FNS(SCSPTR, 0, 0, 0, 0) |
|
|
|
|
SCIF_FNS(SCTDSR, 0x0c, 8) |
|
|
|
|
SCIF_FNS(SCFER, 0x10, 16) |
|
|
|
|
SCIF_FNS(SCFCR, 0x18, 16) |
|
|
|
|
SCIF_FNS(SCFDR, 0x1c, 16) |
|
|
|
|
SCIF_FNS(SCLSR, 0x24, 16) |
|
|
|
|
@ -503,7 +412,6 @@ SCIF_FNS(SCLSR, 0, 0, 0x28, 16) |
|
|
|
|
#elif defined(CONFIG_CPU_SUBTYPE_SH7763) |
|
|
|
|
SCIF_FNS(SCFDR, 0, 0, 0x1C, 16) |
|
|
|
|
SCIF_FNS(SCSPTR2, 0, 0, 0x20, 16) |
|
|
|
|
SCIF_FNS(SCLSR2, 0, 0, 0x24, 16) |
|
|
|
|
SCIF_FNS(SCTFDR, 0x0e, 16, 0x1C, 16) |
|
|
|
|
SCIF_FNS(SCRFDR, 0x0e, 16, 0x20, 16) |
|
|
|
|
SCIF_FNS(SCSPTR, 0, 0, 0x24, 16) |
|
|
|
|
@ -597,64 +505,3 @@ static inline int sci_rxd_in(struct uart_port *port) |
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|
|
return 1; |
|
|
|
|
} |
|
|
|
|
#endif |
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* Values for the BitRate Register (SCBRR) |
|
|
|
|
* |
|
|
|
|
* The values are actually divisors for a frequency which can |
|
|
|
|
* be internal to the SH3 (14.7456MHz) or derived from an external |
|
|
|
|
* clock source. This driver assumes the internal clock is used; |
|
|
|
|
* to support using an external clock source, config options or |
|
|
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* possibly command-line options would need to be added. |
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* |
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* Also, to support speeds below 2400 (why?) the lower 2 bits of |
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* the SCSMR register would also need to be set to non-zero values. |
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* |
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* -- Greg Banks 27Feb2000 |
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* |
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* Answer: The SCBRR register is only eight bits, and the value in |
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* it gets larger with lower baud rates. At around 2400 (depending on |
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* the peripherial module clock) you run out of bits. However the |
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* lower two bits of SCSMR allow the module clock to be divided down, |
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* scaling the value which is needed in SCBRR. |
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* |
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* -- Stuart Menefy - 23 May 2000 |
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* |
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* I meant, why would anyone bother with bitrates below 2400. |
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* |
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* -- Greg Banks - 7Jul2000 |
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* |
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* You "speedist"! How will I use my 110bps ASR-33 teletype with paper |
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* tape reader as a console! |
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* |
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* -- Mitch Davis - 15 Jul 2000 |
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*/ |
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#if (defined(CONFIG_CPU_SUBTYPE_SH7780) || \ |
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defined(CONFIG_CPU_SUBTYPE_SH7785) || \
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defined(CONFIG_CPU_SUBTYPE_SH7786)) && \
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!defined(CONFIG_SH_SH2007) |
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(16*bps)-1) |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7705) || \ |
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defined(CONFIG_CPU_SUBTYPE_SH7720) || \
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defined(CONFIG_CPU_SUBTYPE_SH7721) || \
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defined(CONFIG_ARCH_SH73A0) || \
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defined(CONFIG_ARCH_SH7367) || \
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defined(CONFIG_ARCH_SH7377) || \
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defined(CONFIG_ARCH_SH7372) |
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#define SCBRR_VALUE(bps, clk) (((clk*2)+16*bps)/(32*bps)-1) |
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#elif defined(CONFIG_CPU_SUBTYPE_SH7723) ||\ |
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defined(CONFIG_CPU_SUBTYPE_SH7724) |
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static inline int scbrr_calc(struct uart_port *port, int bps, int clk) |
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{ |
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if (port->type == PORT_SCIF) |
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return (clk+16*bps)/(32*bps)-1; |
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else |
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return ((clk*2)+16*bps)/(16*bps)-1; |
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} |
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#define SCBRR_VALUE(bps, clk) scbrr_calc(port, bps, clk) |
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#elif defined(__H8300H__) || defined(__H8300S__) |
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#define SCBRR_VALUE(bps, clk) (((clk*1000/32)/bps)-1) |
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#else /* Generic SH */ |
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#define SCBRR_VALUE(bps, clk) ((clk+16*bps)/(32*bps)-1) |
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#endif |
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Linus Torvalds
14 years ago