Merge branch 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung into drm-core-next
these patch sets include the following features: - add Samsung SoC Exynos based HDMI support. - add pm feature for fimd driver. - add multi buffer plane pixel formats to drm/drm_fourcc.h. multi buffer plane pixel format has seperated memory spaces for each plane. for exampme, NV12M has Y plane and CbCr plane and these are in non-continuous memory region. compared with NV12, NV12M's memory shape is like following. NV12 : ______(Y)(CbCr)_______ NV12M : __(Y)_ ..... _(CbCr)__ - bug fix to vblank. - code clean to exynos gem framework. * 'exynos-drm-next' of git://git.infradead.org/users/kmpark/linux-samsung: drm/exynos: added hdmi display support drm/exynos: added mutex lock and code clean. drm/exynos: extend vblank off delay time. drm/exynos: change driver name. drm/exynos: Support multi buffers drm: Add multi buffer plane pixel formats drm/exynos: added pm support. drm/exynos: remove buffer creation of fbdev from drm framebuffer creation drm/exynos: Split creation of gem object and gem handle drm/exynos: Fix a fake mmap offset creation drm/exynos: gem code cleanuptirimbino
commit
863f78b5ff
@ -0,0 +1,58 @@ |
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/*
|
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* Copyright (C) 2011 Samsung Electronics Co.Ltd |
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* Authors: |
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* Seung-Woo Kim <sw0312.kim@samsung.com> |
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* Inki Dae <inki.dae@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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*/ |
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|
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#include "drmP.h" |
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|
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#include <linux/kernel.h> |
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#include <linux/i2c.h> |
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#include <linux/module.h> |
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#include "exynos_drm_drv.h" |
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#include "exynos_hdmi.h" |
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static int s5p_ddc_probe(struct i2c_client *client, |
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const struct i2c_device_id *dev_id) |
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{ |
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hdmi_attach_ddc_client(client); |
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dev_info(&client->adapter->dev, "attached s5p_ddc " |
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"into i2c adapter successfully\n"); |
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return 0; |
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} |
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|
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static int s5p_ddc_remove(struct i2c_client *client) |
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{ |
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dev_info(&client->adapter->dev, "detached s5p_ddc " |
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"from i2c adapter successfully\n"); |
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return 0; |
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} |
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static struct i2c_device_id ddc_idtable[] = { |
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{"s5p_ddc", 0}, |
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{ }, |
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}; |
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|
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struct i2c_driver ddc_driver = { |
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.driver = { |
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.name = "s5p_ddc", |
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.owner = THIS_MODULE, |
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}, |
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.id_table = ddc_idtable, |
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.probe = s5p_ddc_probe, |
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.remove = __devexit_p(s5p_ddc_remove), |
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.command = NULL, |
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}; |
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EXPORT_SYMBOL(ddc_driver); |
@ -0,0 +1,439 @@ |
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/*
|
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* Copyright (C) 2011 Samsung Electronics Co.Ltd |
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* Authors: |
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* Inki Dae <inki.dae@samsung.com> |
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* Seung-Woo Kim <sw0312.kim@samsung.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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*/ |
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|
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#include "drmP.h" |
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#include <linux/kernel.h> |
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#include <linux/wait.h> |
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#include <linux/module.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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#include <drm/exynos_drm.h> |
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#include "exynos_drm_drv.h" |
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#include "exynos_drm_hdmi.h" |
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#define to_context(dev) platform_get_drvdata(to_platform_device(dev)) |
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#define to_subdrv(dev) to_context(dev) |
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#define get_ctx_from_subdrv(subdrv) container_of(subdrv,\ |
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struct drm_hdmi_context, subdrv); |
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/* these callback points shoud be set by specific drivers. */ |
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static struct exynos_hdmi_display_ops *hdmi_display_ops; |
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static struct exynos_hdmi_manager_ops *hdmi_manager_ops; |
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static struct exynos_hdmi_overlay_ops *hdmi_overlay_ops; |
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|
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struct drm_hdmi_context { |
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struct exynos_drm_subdrv subdrv; |
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struct exynos_drm_hdmi_context *hdmi_ctx; |
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struct exynos_drm_hdmi_context *mixer_ctx; |
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struct work_struct work; |
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}; |
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|
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void exynos_drm_display_ops_register(struct exynos_hdmi_display_ops |
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*display_ops) |
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{ |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (display_ops) |
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hdmi_display_ops = display_ops; |
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} |
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EXPORT_SYMBOL(exynos_drm_display_ops_register); |
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void exynos_drm_manager_ops_register(struct exynos_hdmi_manager_ops |
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*manager_ops) |
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{ |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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|
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if (manager_ops) |
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hdmi_manager_ops = manager_ops; |
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} |
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EXPORT_SYMBOL(exynos_drm_manager_ops_register); |
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void exynos_drm_overlay_ops_register(struct exynos_hdmi_overlay_ops |
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*overlay_ops) |
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{ |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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|
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if (overlay_ops) |
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hdmi_overlay_ops = overlay_ops; |
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} |
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EXPORT_SYMBOL(exynos_drm_overlay_ops_register); |
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static bool drm_hdmi_is_connected(struct device *dev) |
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{ |
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struct drm_hdmi_context *ctx = to_context(dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_display_ops && hdmi_display_ops->is_connected) |
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return hdmi_display_ops->is_connected(ctx->hdmi_ctx->ctx); |
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return false; |
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} |
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static int drm_hdmi_get_edid(struct device *dev, |
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struct drm_connector *connector, u8 *edid, int len) |
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{ |
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struct drm_hdmi_context *ctx = to_context(dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_display_ops && hdmi_display_ops->get_edid) |
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return hdmi_display_ops->get_edid(ctx->hdmi_ctx->ctx, |
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connector, edid, len); |
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return 0; |
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} |
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static int drm_hdmi_check_timing(struct device *dev, void *timing) |
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{ |
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struct drm_hdmi_context *ctx = to_context(dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_display_ops && hdmi_display_ops->check_timing) |
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return hdmi_display_ops->check_timing(ctx->hdmi_ctx->ctx, |
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timing); |
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return 0; |
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} |
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static int drm_hdmi_power_on(struct device *dev, int mode) |
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{ |
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struct drm_hdmi_context *ctx = to_context(dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_display_ops && hdmi_display_ops->power_on) |
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return hdmi_display_ops->power_on(ctx->hdmi_ctx->ctx, mode); |
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return 0; |
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} |
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static struct exynos_drm_display_ops drm_hdmi_display_ops = { |
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.type = EXYNOS_DISPLAY_TYPE_HDMI, |
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.is_connected = drm_hdmi_is_connected, |
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.get_edid = drm_hdmi_get_edid, |
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.check_timing = drm_hdmi_check_timing, |
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.power_on = drm_hdmi_power_on, |
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}; |
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static int drm_hdmi_enable_vblank(struct device *subdrv_dev) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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struct exynos_drm_subdrv *subdrv = &ctx->subdrv; |
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struct exynos_drm_manager *manager = &subdrv->manager; |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_overlay_ops && hdmi_overlay_ops->enable_vblank) |
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return hdmi_overlay_ops->enable_vblank(ctx->mixer_ctx->ctx, |
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manager->pipe); |
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return 0; |
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} |
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static void drm_hdmi_disable_vblank(struct device *subdrv_dev) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_overlay_ops && hdmi_overlay_ops->disable_vblank) |
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return hdmi_overlay_ops->disable_vblank(ctx->mixer_ctx->ctx); |
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} |
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static void drm_hdmi_mode_set(struct device *subdrv_dev, void *mode) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_manager_ops && hdmi_manager_ops->mode_set) |
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hdmi_manager_ops->mode_set(ctx->hdmi_ctx->ctx, mode); |
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} |
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static void drm_hdmi_commit(struct device *subdrv_dev) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_manager_ops && hdmi_manager_ops->commit) |
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hdmi_manager_ops->commit(ctx->hdmi_ctx->ctx); |
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} |
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static void drm_hdmi_dpms(struct device *subdrv_dev, int mode) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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switch (mode) { |
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case DRM_MODE_DPMS_ON: |
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break; |
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case DRM_MODE_DPMS_STANDBY: |
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case DRM_MODE_DPMS_SUSPEND: |
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case DRM_MODE_DPMS_OFF: |
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if (hdmi_manager_ops && hdmi_manager_ops->disable) |
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hdmi_manager_ops->disable(ctx->hdmi_ctx->ctx); |
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break; |
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default: |
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DRM_DEBUG_KMS("unkown dps mode: %d\n", mode); |
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break; |
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} |
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} |
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static struct exynos_drm_manager_ops drm_hdmi_manager_ops = { |
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.dpms = drm_hdmi_dpms, |
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.enable_vblank = drm_hdmi_enable_vblank, |
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.disable_vblank = drm_hdmi_disable_vblank, |
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.mode_set = drm_hdmi_mode_set, |
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.commit = drm_hdmi_commit, |
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}; |
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static void drm_mixer_mode_set(struct device *subdrv_dev, |
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struct exynos_drm_overlay *overlay) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_overlay_ops && hdmi_overlay_ops->win_mode_set) |
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hdmi_overlay_ops->win_mode_set(ctx->mixer_ctx->ctx, overlay); |
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} |
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static void drm_mixer_commit(struct device *subdrv_dev, int zpos) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_overlay_ops && hdmi_overlay_ops->win_commit) |
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hdmi_overlay_ops->win_commit(ctx->mixer_ctx->ctx, zpos); |
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} |
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|
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static void drm_mixer_disable(struct device *subdrv_dev, int zpos) |
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{ |
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struct drm_hdmi_context *ctx = to_context(subdrv_dev); |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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if (hdmi_overlay_ops && hdmi_overlay_ops->win_disable) |
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hdmi_overlay_ops->win_disable(ctx->mixer_ctx->ctx, zpos); |
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} |
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|
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static struct exynos_drm_overlay_ops drm_hdmi_overlay_ops = { |
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.mode_set = drm_mixer_mode_set, |
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.commit = drm_mixer_commit, |
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.disable = drm_mixer_disable, |
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}; |
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|
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|
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static int hdmi_subdrv_probe(struct drm_device *drm_dev, |
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struct device *dev) |
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{ |
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struct exynos_drm_subdrv *subdrv = to_subdrv(dev); |
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struct drm_hdmi_context *ctx; |
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struct platform_device *pdev = to_platform_device(dev); |
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struct exynos_drm_common_hdmi_pd *pd; |
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int ret; |
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|
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DRM_DEBUG_KMS("%s\n", __FILE__); |
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|
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pd = pdev->dev.platform_data; |
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|
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if (!pd) { |
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DRM_DEBUG_KMS("platform data is null.\n"); |
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return -EFAULT; |
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} |
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|
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if (!pd->hdmi_dev) { |
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DRM_DEBUG_KMS("hdmi device is null.\n"); |
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return -EFAULT; |
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} |
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|
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if (!pd->mixer_dev) { |
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DRM_DEBUG_KMS("mixer device is null.\n"); |
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return -EFAULT; |
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} |
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|
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ret = platform_driver_register(&hdmi_driver); |
||||
if (ret) { |
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DRM_DEBUG_KMS("failed to register hdmi driver.\n"); |
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return ret; |
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} |
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|
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ret = platform_driver_register(&mixer_driver); |
||||
if (ret) { |
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DRM_DEBUG_KMS("failed to register mixer driver.\n"); |
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goto err_hdmidrv; |
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} |
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|
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ctx = get_ctx_from_subdrv(subdrv); |
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|
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ctx->hdmi_ctx = (struct exynos_drm_hdmi_context *) |
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to_context(pd->hdmi_dev); |
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if (!ctx->hdmi_ctx) { |
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DRM_DEBUG_KMS("hdmi context is null.\n"); |
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ret = -EFAULT; |
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goto err_mixerdrv; |
||||
} |
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|
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ctx->hdmi_ctx->drm_dev = drm_dev; |
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|
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ctx->mixer_ctx = (struct exynos_drm_hdmi_context *) |
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to_context(pd->mixer_dev); |
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if (!ctx->mixer_ctx) { |
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DRM_DEBUG_KMS("mixer context is null.\n"); |
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ret = -EFAULT; |
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goto err_mixerdrv; |
||||
} |
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|
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ctx->mixer_ctx->drm_dev = drm_dev; |
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|
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return 0; |
||||
|
||||
err_mixerdrv: |
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platform_driver_unregister(&mixer_driver); |
||||
err_hdmidrv: |
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platform_driver_unregister(&hdmi_driver); |
||||
return ret; |
||||
} |
||||
|
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static void hdmi_subdrv_remove(struct drm_device *drm_dev) |
||||
{ |
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DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
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platform_driver_unregister(&hdmi_driver); |
||||
platform_driver_unregister(&mixer_driver); |
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} |
||||
|
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static void exynos_drm_hdmi_late_probe(struct work_struct *work) |
||||
{ |
||||
struct drm_hdmi_context *ctx = container_of(work, |
||||
struct drm_hdmi_context, work); |
||||
|
||||
/*
|
||||
* this function calls subdrv->probe() so this must be called |
||||
* after probe context. |
||||
* |
||||
* PS. subdrv->probe() will call platform_driver_register() to probe |
||||
* hdmi and mixer driver. |
||||
*/ |
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exynos_drm_subdrv_register(&ctx->subdrv); |
||||
} |
||||
|
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static int __devinit exynos_drm_hdmi_probe(struct platform_device *pdev) |
||||
{ |
||||
struct device *dev = &pdev->dev; |
||||
struct exynos_drm_subdrv *subdrv; |
||||
struct drm_hdmi_context *ctx; |
||||
|
||||
DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
||||
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
||||
if (!ctx) { |
||||
DRM_LOG_KMS("failed to alloc common hdmi context.\n"); |
||||
return -ENOMEM; |
||||
} |
||||
|
||||
subdrv = &ctx->subdrv; |
||||
|
||||
subdrv->probe = hdmi_subdrv_probe; |
||||
subdrv->remove = hdmi_subdrv_remove; |
||||
subdrv->manager.pipe = -1; |
||||
subdrv->manager.ops = &drm_hdmi_manager_ops; |
||||
subdrv->manager.overlay_ops = &drm_hdmi_overlay_ops; |
||||
subdrv->manager.display_ops = &drm_hdmi_display_ops; |
||||
subdrv->manager.dev = dev; |
||||
|
||||
platform_set_drvdata(pdev, subdrv); |
||||
|
||||
INIT_WORK(&ctx->work, exynos_drm_hdmi_late_probe); |
||||
|
||||
schedule_work(&ctx->work); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int hdmi_runtime_suspend(struct device *dev) |
||||
{ |
||||
DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int hdmi_runtime_resume(struct device *dev) |
||||
{ |
||||
DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dev_pm_ops hdmi_pm_ops = { |
||||
.runtime_suspend = hdmi_runtime_suspend, |
||||
.runtime_resume = hdmi_runtime_resume, |
||||
}; |
||||
|
||||
static int __devexit exynos_drm_hdmi_remove(struct platform_device *pdev) |
||||
{ |
||||
struct drm_hdmi_context *ctx = platform_get_drvdata(pdev); |
||||
|
||||
DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
||||
exynos_drm_subdrv_unregister(&ctx->subdrv); |
||||
kfree(ctx); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct platform_driver exynos_drm_common_hdmi_driver = { |
||||
.probe = exynos_drm_hdmi_probe, |
||||
.remove = __devexit_p(exynos_drm_hdmi_remove), |
||||
.driver = { |
||||
.name = "exynos-drm-hdmi", |
||||
.owner = THIS_MODULE, |
||||
.pm = &hdmi_pm_ops, |
||||
}, |
||||
}; |
||||
|
||||
static int __init exynos_drm_hdmi_init(void) |
||||
{ |
||||
int ret; |
||||
|
||||
DRM_DEBUG_KMS("%s\n", __FILE__); |
||||
|
||||
ret = platform_driver_register(&exynos_drm_common_hdmi_driver); |
||||
if (ret) { |
||||
DRM_DEBUG_KMS("failed to register hdmi common driver.\n"); |
||||
return ret; |
||||
} |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static void __exit exynos_drm_hdmi_exit(void) |
||||
{ |
||||
platform_driver_unregister(&exynos_drm_common_hdmi_driver); |
||||
} |
||||
|
||||
module_init(exynos_drm_hdmi_init); |
||||
module_exit(exynos_drm_hdmi_exit); |
||||
|
||||
MODULE_AUTHOR("Inki Dae <inki.dae@samsung.com>"); |
||||
MODULE_AUTHOR("Seung-Woo Kim, <sw0312.kim@samsung.com>"); |
||||
MODULE_DESCRIPTION("Samsung SoC DRM HDMI Driver"); |
||||
MODULE_LICENSE("GPL"); |
@ -0,0 +1,73 @@ |
||||
/* exynos_drm_hdmi.h
|
||||
* |
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
||||
* Authoer: Inki Dae <inki.dae@samsung.com> |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice (including the next |
||||
* paragraph) shall be included in all copies or substantial portions of the |
||||
* Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _EXYNOS_DRM_HDMI_H_ |
||||
#define _EXYNOS_DRM_HDMI_H_ |
||||
|
||||
/*
|
||||
* exynos hdmi common context structure. |
||||
* |
||||
* @drm_dev: pointer to drm_device. |
||||
* @ctx: pointer to the context of specific device driver. |
||||
* this context should be hdmi_context or mixer_context. |
||||
*/ |
||||
struct exynos_drm_hdmi_context { |
||||
struct drm_device *drm_dev; |
||||
void *ctx; |
||||
}; |
||||
|
||||
struct exynos_hdmi_display_ops { |
||||
bool (*is_connected)(void *ctx); |
||||
int (*get_edid)(void *ctx, struct drm_connector *connector, |
||||
u8 *edid, int len); |
||||
int (*check_timing)(void *ctx, void *timing); |
||||
int (*power_on)(void *ctx, int mode); |
||||
}; |
||||
|
||||
struct exynos_hdmi_manager_ops { |
||||
void (*mode_set)(void *ctx, void *mode); |
||||
void (*commit)(void *ctx); |
||||
void (*disable)(void *ctx); |
||||
}; |
||||
|
||||
struct exynos_hdmi_overlay_ops { |
||||
int (*enable_vblank)(void *ctx, int pipe); |
||||
void (*disable_vblank)(void *ctx); |
||||
void (*win_mode_set)(void *ctx, struct exynos_drm_overlay *overlay); |
||||
void (*win_commit)(void *ctx, int zpos); |
||||
void (*win_disable)(void *ctx, int zpos); |
||||
}; |
||||
|
||||
extern struct platform_driver hdmi_driver; |
||||
extern struct platform_driver mixer_driver; |
||||
|
||||
void exynos_drm_display_ops_register(struct exynos_hdmi_display_ops |
||||
*display_ops); |
||||
void exynos_drm_manager_ops_register(struct exynos_hdmi_manager_ops |
||||
*manager_ops); |
||||
void exynos_drm_overlay_ops_register(struct exynos_hdmi_overlay_ops |
||||
*overlay_ops); |
||||
|
||||
#endif |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,87 @@ |
||||
/*
|
||||
* |
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
||||
* Authors: |
||||
* Inki Dae <inki.dae@samsung.com> |
||||
* Seung-Woo Kim <sw0312.kim@samsung.com> |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice (including the next |
||||
* paragraph) shall be included in all copies or substantial portions of the |
||||
* Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _EXYNOS_HDMI_H_ |
||||
#define _EXYNOS_HDMI_H_ |
||||
|
||||
struct hdmi_conf { |
||||
int width; |
||||
int height; |
||||
int vrefresh; |
||||
bool interlace; |
||||
const u8 *hdmiphy_data; |
||||
const struct hdmi_preset_conf *conf; |
||||
}; |
||||
|
||||
struct hdmi_resources { |
||||
struct clk *hdmi; |
||||
struct clk *sclk_hdmi; |
||||
struct clk *sclk_pixel; |
||||
struct clk *sclk_hdmiphy; |
||||
struct clk *hdmiphy; |
||||
struct regulator_bulk_data *regul_bulk; |
||||
int regul_count; |
||||
}; |
||||
|
||||
struct hdmi_context { |
||||
struct device *dev; |
||||
struct drm_device *drm_dev; |
||||
struct fb_videomode *default_timing; |
||||
unsigned int default_win; |
||||
unsigned int default_bpp; |
||||
bool hpd_handle; |
||||
bool enabled; |
||||
|
||||
struct resource *regs_res; |
||||
/** base address of HDMI registers */ |
||||
void __iomem *regs; |
||||
/** HDMI hotplug interrupt */ |
||||
unsigned int irq; |
||||
/** workqueue for delayed work */ |
||||
struct workqueue_struct *wq; |
||||
/** hotplug handling work */ |
||||
struct work_struct hotplug_work; |
||||
|
||||
struct i2c_client *ddc_port; |
||||
struct i2c_client *hdmiphy_port; |
||||
|
||||
/** current hdmiphy conf index */ |
||||
int cur_conf; |
||||
/** other resources */ |
||||
struct hdmi_resources res; |
||||
|
||||
void *parent_ctx; |
||||
}; |
||||
|
||||
|
||||
void hdmi_attach_ddc_client(struct i2c_client *ddc); |
||||
void hdmi_attach_hdmiphy_client(struct i2c_client *hdmiphy); |
||||
|
||||
extern struct i2c_driver hdmiphy_driver; |
||||
extern struct i2c_driver ddc_driver; |
||||
|
||||
#endif |
@ -0,0 +1,58 @@ |
||||
/*
|
||||
* Copyright (C) 2011 Samsung Electronics Co.Ltd |
||||
* Authors: |
||||
* Seung-Woo Kim <sw0312.kim@samsung.com> |
||||
* Inki Dae <inki.dae@samsung.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify it |
||||
* under the terms of the GNU General Public License as published by the |
||||
* Free Software Foundation; either version 2 of the License, or (at your |
||||
* option) any later version. |
||||
* |
||||
*/ |
||||
|
||||
#include "drmP.h" |
||||
|
||||
#include <linux/kernel.h> |
||||
#include <linux/i2c.h> |
||||
#include <linux/module.h> |
||||
|
||||
#include "exynos_drm_drv.h" |
||||
#include "exynos_hdmi.h" |
||||
|
||||
|
||||
static int hdmiphy_probe(struct i2c_client *client, |
||||
const struct i2c_device_id *id) |
||||
{ |
||||
hdmi_attach_hdmiphy_client(client); |
||||
|
||||
dev_info(&client->adapter->dev, "attached s5p_hdmiphy " |
||||
"into i2c adapter successfully\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int hdmiphy_remove(struct i2c_client *client) |
||||
{ |
||||
dev_info(&client->adapter->dev, "detached s5p_hdmiphy " |
||||
"from i2c adapter successfully\n"); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct i2c_device_id hdmiphy_id[] = { |
||||
{ "s5p_hdmiphy", 0 }, |
||||
{ }, |
||||
}; |
||||
|
||||
struct i2c_driver hdmiphy_driver = { |
||||
.driver = { |
||||
.name = "s5p-hdmiphy", |
||||
.owner = THIS_MODULE, |
||||
}, |
||||
.id_table = hdmiphy_id, |
||||
.probe = hdmiphy_probe, |
||||
.remove = __devexit_p(hdmiphy_remove), |
||||
.command = NULL, |
||||
}; |
||||
EXPORT_SYMBOL(hdmiphy_driver); |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,92 @@ |
||||
/*
|
||||
* |
||||
* Copyright (c) 2011 Samsung Electronics Co., Ltd. |
||||
* Authors: |
||||
* Seung-Woo Kim <sw0312.kim@samsung.com> |
||||
* Inki Dae <inki.dae@samsung.com> |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice (including the next |
||||
* paragraph) shall be included in all copies or substantial portions of the |
||||
* Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
*/ |
||||
|
||||
#ifndef _EXYNOS_MIXER_H_ |
||||
#define _EXYNOS_MIXER_H_ |
||||
|
||||
#define HDMI_OVERLAY_NUMBER 3 |
||||
|
||||
struct hdmi_win_data { |
||||
dma_addr_t dma_addr; |
||||
void __iomem *vaddr; |
||||
dma_addr_t chroma_dma_addr; |
||||
void __iomem *chroma_vaddr; |
||||
uint32_t pixel_format; |
||||
unsigned int bpp; |
||||
unsigned int crtc_x; |
||||
unsigned int crtc_y; |
||||
unsigned int crtc_width; |
||||
unsigned int crtc_height; |
||||
unsigned int fb_x; |
||||
unsigned int fb_y; |
||||
unsigned int fb_width; |
||||
unsigned int fb_height; |
||||
unsigned int mode_width; |
||||
unsigned int mode_height; |
||||
unsigned int scan_flags; |
||||
}; |
||||
|
||||
struct mixer_resources { |
||||
struct device *dev; |
||||
/** interrupt index */ |
||||
int irq; |
||||
/** pointer to Mixer registers */ |
||||
void __iomem *mixer_regs; |
||||
/** pointer to Video Processor registers */ |
||||
void __iomem *vp_regs; |
||||
/** spinlock for protection of registers */ |
||||
spinlock_t reg_slock; |
||||
/** other resources */ |
||||
struct clk *mixer; |
||||
struct clk *vp; |
||||
struct clk *sclk_mixer; |
||||
struct clk *sclk_hdmi; |
||||
struct clk *sclk_dac; |
||||
}; |
||||
|
||||
struct mixer_context { |
||||
unsigned int default_win; |
||||
struct fb_videomode *default_timing; |
||||
unsigned int default_bpp; |
||||
|
||||
/** mixer interrupt */ |
||||
unsigned int irq; |
||||
/** current crtc pipe for vblank */ |
||||
int pipe; |
||||
/** interlace scan mode */ |
||||
bool interlace; |
||||
/** vp enabled status */ |
||||
bool vp_enabled; |
||||
|
||||
/** mixer and vp resources */ |
||||
struct mixer_resources mixer_res; |
||||
|
||||
/** overlay window data */ |
||||
struct hdmi_win_data win_data[HDMI_OVERLAY_NUMBER]; |
||||
}; |
||||
|
||||
#endif |
@ -0,0 +1,147 @@ |
||||
/*
|
||||
* |
||||
* Cloned from drivers/media/video/s5p-tv/regs-hdmi.h |
||||
* |
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* HDMI register header file for Samsung TVOUT driver |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef SAMSUNG_REGS_HDMI_H |
||||
#define SAMSUNG_REGS_HDMI_H |
||||
|
||||
/*
|
||||
* Register part |
||||
*/ |
||||
|
||||
#define HDMI_CTRL_BASE(x) ((x) + 0x00000000) |
||||
#define HDMI_CORE_BASE(x) ((x) + 0x00010000) |
||||
#define HDMI_TG_BASE(x) ((x) + 0x00050000) |
||||
|
||||
/* Control registers */ |
||||
#define HDMI_INTC_CON HDMI_CTRL_BASE(0x0000) |
||||
#define HDMI_INTC_FLAG HDMI_CTRL_BASE(0x0004) |
||||
#define HDMI_HPD_STATUS HDMI_CTRL_BASE(0x000C) |
||||
#define HDMI_PHY_RSTOUT HDMI_CTRL_BASE(0x0014) |
||||
#define HDMI_PHY_VPLL HDMI_CTRL_BASE(0x0018) |
||||
#define HDMI_PHY_CMU HDMI_CTRL_BASE(0x001C) |
||||
#define HDMI_CORE_RSTOUT HDMI_CTRL_BASE(0x0020) |
||||
|
||||
/* Core registers */ |
||||
#define HDMI_CON_0 HDMI_CORE_BASE(0x0000) |
||||
#define HDMI_CON_1 HDMI_CORE_BASE(0x0004) |
||||
#define HDMI_CON_2 HDMI_CORE_BASE(0x0008) |
||||
#define HDMI_SYS_STATUS HDMI_CORE_BASE(0x0010) |
||||
#define HDMI_PHY_STATUS HDMI_CORE_BASE(0x0014) |
||||
#define HDMI_STATUS_EN HDMI_CORE_BASE(0x0020) |
||||
#define HDMI_HPD HDMI_CORE_BASE(0x0030) |
||||
#define HDMI_MODE_SEL HDMI_CORE_BASE(0x0040) |
||||
#define HDMI_BLUE_SCREEN_0 HDMI_CORE_BASE(0x0050) |
||||
#define HDMI_BLUE_SCREEN_1 HDMI_CORE_BASE(0x0054) |
||||
#define HDMI_BLUE_SCREEN_2 HDMI_CORE_BASE(0x0058) |
||||
#define HDMI_H_BLANK_0 HDMI_CORE_BASE(0x00A0) |
||||
#define HDMI_H_BLANK_1 HDMI_CORE_BASE(0x00A4) |
||||
#define HDMI_V_BLANK_0 HDMI_CORE_BASE(0x00B0) |
||||
#define HDMI_V_BLANK_1 HDMI_CORE_BASE(0x00B4) |
||||
#define HDMI_V_BLANK_2 HDMI_CORE_BASE(0x00B8) |
||||
#define HDMI_H_V_LINE_0 HDMI_CORE_BASE(0x00C0) |
||||
#define HDMI_H_V_LINE_1 HDMI_CORE_BASE(0x00C4) |
||||
#define HDMI_H_V_LINE_2 HDMI_CORE_BASE(0x00C8) |
||||
#define HDMI_VSYNC_POL HDMI_CORE_BASE(0x00E4) |
||||
#define HDMI_INT_PRO_MODE HDMI_CORE_BASE(0x00E8) |
||||
#define HDMI_V_BLANK_F_0 HDMI_CORE_BASE(0x0110) |
||||
#define HDMI_V_BLANK_F_1 HDMI_CORE_BASE(0x0114) |
||||
#define HDMI_V_BLANK_F_2 HDMI_CORE_BASE(0x0118) |
||||
#define HDMI_H_SYNC_GEN_0 HDMI_CORE_BASE(0x0120) |
||||
#define HDMI_H_SYNC_GEN_1 HDMI_CORE_BASE(0x0124) |
||||
#define HDMI_H_SYNC_GEN_2 HDMI_CORE_BASE(0x0128) |
||||
#define HDMI_V_SYNC_GEN_1_0 HDMI_CORE_BASE(0x0130) |
||||
#define HDMI_V_SYNC_GEN_1_1 HDMI_CORE_BASE(0x0134) |
||||
#define HDMI_V_SYNC_GEN_1_2 HDMI_CORE_BASE(0x0138) |
||||
#define HDMI_V_SYNC_GEN_2_0 HDMI_CORE_BASE(0x0140) |
||||
#define HDMI_V_SYNC_GEN_2_1 HDMI_CORE_BASE(0x0144) |
||||
#define HDMI_V_SYNC_GEN_2_2 HDMI_CORE_BASE(0x0148) |
||||
#define HDMI_V_SYNC_GEN_3_0 HDMI_CORE_BASE(0x0150) |
||||
#define HDMI_V_SYNC_GEN_3_1 HDMI_CORE_BASE(0x0154) |
||||
#define HDMI_V_SYNC_GEN_3_2 HDMI_CORE_BASE(0x0158) |
||||
#define HDMI_ACR_CON HDMI_CORE_BASE(0x0180) |
||||
#define HDMI_AVI_CON HDMI_CORE_BASE(0x0300) |
||||
#define HDMI_AVI_BYTE(n) HDMI_CORE_BASE(0x0320 + 4 * (n)) |
||||
#define HDMI_DC_CONTROL HDMI_CORE_BASE(0x05C0) |
||||
#define HDMI_VIDEO_PATTERN_GEN HDMI_CORE_BASE(0x05C4) |
||||
#define HDMI_HPD_GEN HDMI_CORE_BASE(0x05C8) |
||||
#define HDMI_AUI_CON HDMI_CORE_BASE(0x0360) |
||||
#define HDMI_SPD_CON HDMI_CORE_BASE(0x0400) |
||||
|
||||
/* Timing generator registers */ |
||||
#define HDMI_TG_CMD HDMI_TG_BASE(0x0000) |
||||
#define HDMI_TG_H_FSZ_L HDMI_TG_BASE(0x0018) |
||||
#define HDMI_TG_H_FSZ_H HDMI_TG_BASE(0x001C) |
||||
#define HDMI_TG_HACT_ST_L HDMI_TG_BASE(0x0020) |
||||
#define HDMI_TG_HACT_ST_H HDMI_TG_BASE(0x0024) |
||||
#define HDMI_TG_HACT_SZ_L HDMI_TG_BASE(0x0028) |
||||
#define HDMI_TG_HACT_SZ_H HDMI_TG_BASE(0x002C) |
||||
#define HDMI_TG_V_FSZ_L HDMI_TG_BASE(0x0030) |
||||
#define HDMI_TG_V_FSZ_H HDMI_TG_BASE(0x0034) |
||||
#define HDMI_TG_VSYNC_L HDMI_TG_BASE(0x0038) |
||||
#define HDMI_TG_VSYNC_H HDMI_TG_BASE(0x003C) |
||||
#define HDMI_TG_VSYNC2_L HDMI_TG_BASE(0x0040) |
||||
#define HDMI_TG_VSYNC2_H HDMI_TG_BASE(0x0044) |
||||
#define HDMI_TG_VACT_ST_L HDMI_TG_BASE(0x0048) |
||||
#define HDMI_TG_VACT_ST_H HDMI_TG_BASE(0x004C) |
||||
#define HDMI_TG_VACT_SZ_L HDMI_TG_BASE(0x0050) |
||||
#define HDMI_TG_VACT_SZ_H HDMI_TG_BASE(0x0054) |
||||
#define HDMI_TG_FIELD_CHG_L HDMI_TG_BASE(0x0058) |
||||
#define HDMI_TG_FIELD_CHG_H HDMI_TG_BASE(0x005C) |
||||
#define HDMI_TG_VACT_ST2_L HDMI_TG_BASE(0x0060) |
||||
#define HDMI_TG_VACT_ST2_H HDMI_TG_BASE(0x0064) |
||||
#define HDMI_TG_VSYNC_TOP_HDMI_L HDMI_TG_BASE(0x0078) |
||||
#define HDMI_TG_VSYNC_TOP_HDMI_H HDMI_TG_BASE(0x007C) |
||||
#define HDMI_TG_VSYNC_BOT_HDMI_L HDMI_TG_BASE(0x0080) |
||||
#define HDMI_TG_VSYNC_BOT_HDMI_H HDMI_TG_BASE(0x0084) |
||||
#define HDMI_TG_FIELD_TOP_HDMI_L HDMI_TG_BASE(0x0088) |
||||
#define HDMI_TG_FIELD_TOP_HDMI_H HDMI_TG_BASE(0x008C) |
||||
#define HDMI_TG_FIELD_BOT_HDMI_L HDMI_TG_BASE(0x0090) |
||||
#define HDMI_TG_FIELD_BOT_HDMI_H HDMI_TG_BASE(0x0094) |
||||
|
||||
/*
|
||||
* Bit definition part |
||||
*/ |
||||
|
||||
/* HDMI_INTC_CON */ |
||||
#define HDMI_INTC_EN_GLOBAL (1 << 6) |
||||
#define HDMI_INTC_EN_HPD_PLUG (1 << 3) |
||||
#define HDMI_INTC_EN_HPD_UNPLUG (1 << 2) |
||||
|
||||
/* HDMI_INTC_FLAG */ |
||||
#define HDMI_INTC_FLAG_HPD_PLUG (1 << 3) |
||||
#define HDMI_INTC_FLAG_HPD_UNPLUG (1 << 2) |
||||
|
||||
/* HDMI_PHY_RSTOUT */ |
||||
#define HDMI_PHY_SW_RSTOUT (1 << 0) |
||||
|
||||
/* HDMI_CORE_RSTOUT */ |
||||
#define HDMI_CORE_SW_RSTOUT (1 << 0) |
||||
|
||||
/* HDMI_CON_0 */ |
||||
#define HDMI_BLUE_SCR_EN (1 << 5) |
||||
#define HDMI_EN (1 << 0) |
||||
|
||||
/* HDMI_PHY_STATUS */ |
||||
#define HDMI_PHY_STATUS_READY (1 << 0) |
||||
|
||||
/* HDMI_MODE_SEL */ |
||||
#define HDMI_MODE_HDMI_EN (1 << 1) |
||||
#define HDMI_MODE_DVI_EN (1 << 0) |
||||
#define HDMI_MODE_MASK (3 << 0) |
||||
|
||||
/* HDMI_TG_CMD */ |
||||
#define HDMI_TG_EN (1 << 0) |
||||
#define HDMI_FIELD_EN (1 << 1) |
||||
|
||||
#endif /* SAMSUNG_REGS_HDMI_H */ |
@ -0,0 +1,141 @@ |
||||
/*
|
||||
* |
||||
* Cloned from drivers/media/video/s5p-tv/regs-mixer.h |
||||
* |
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* Mixer register header file for Samsung Mixer driver |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
#ifndef SAMSUNG_REGS_MIXER_H |
||||
#define SAMSUNG_REGS_MIXER_H |
||||
|
||||
/*
|
||||
* Register part |
||||
*/ |
||||
#define MXR_STATUS 0x0000 |
||||
#define MXR_CFG 0x0004 |
||||
#define MXR_INT_EN 0x0008 |
||||
#define MXR_INT_STATUS 0x000C |
||||
#define MXR_LAYER_CFG 0x0010 |
||||
#define MXR_VIDEO_CFG 0x0014 |
||||
#define MXR_GRAPHIC0_CFG 0x0020 |
||||
#define MXR_GRAPHIC0_BASE 0x0024 |
||||
#define MXR_GRAPHIC0_SPAN 0x0028 |
||||
#define MXR_GRAPHIC0_SXY 0x002C |
||||
#define MXR_GRAPHIC0_WH 0x0030 |
||||
#define MXR_GRAPHIC0_DXY 0x0034 |
||||
#define MXR_GRAPHIC0_BLANK 0x0038 |
||||
#define MXR_GRAPHIC1_CFG 0x0040 |
||||
#define MXR_GRAPHIC1_BASE 0x0044 |
||||
#define MXR_GRAPHIC1_SPAN 0x0048 |
||||
#define MXR_GRAPHIC1_SXY 0x004C |
||||
#define MXR_GRAPHIC1_WH 0x0050 |
||||
#define MXR_GRAPHIC1_DXY 0x0054 |
||||
#define MXR_GRAPHIC1_BLANK 0x0058 |
||||
#define MXR_BG_CFG 0x0060 |
||||
#define MXR_BG_COLOR0 0x0064 |
||||
#define MXR_BG_COLOR1 0x0068 |
||||
#define MXR_BG_COLOR2 0x006C |
||||
#define MXR_CM_COEFF_Y 0x0080 |
||||
#define MXR_CM_COEFF_CB 0x0084 |
||||
#define MXR_CM_COEFF_CR 0x0088 |
||||
#define MXR_GRAPHIC0_BASE_S 0x2024 |
||||
#define MXR_GRAPHIC1_BASE_S 0x2044 |
||||
|
||||
/* for parametrized access to layer registers */ |
||||
#define MXR_GRAPHIC_CFG(i) (0x0020 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_BASE(i) (0x0024 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_SPAN(i) (0x0028 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_SXY(i) (0x002C + (i) * 0x20) |
||||
#define MXR_GRAPHIC_WH(i) (0x0030 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_DXY(i) (0x0034 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_BLANK(i) (0x0038 + (i) * 0x20) |
||||
#define MXR_GRAPHIC_BASE_S(i) (0x2024 + (i) * 0x20) |
||||
|
||||
/*
|
||||
* Bit definition part |
||||
*/ |
||||
|
||||
/* generates mask for range of bits */ |
||||
#define MXR_MASK(high_bit, low_bit) \ |
||||
(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) |
||||
|
||||
#define MXR_MASK_VAL(val, high_bit, low_bit) \ |
||||
(((val) << (low_bit)) & MXR_MASK(high_bit, low_bit)) |
||||
|
||||
/* bits for MXR_STATUS */ |
||||
#define MXR_STATUS_16_BURST (1 << 7) |
||||
#define MXR_STATUS_BURST_MASK (1 << 7) |
||||
#define MXR_STATUS_BIG_ENDIAN (1 << 3) |
||||
#define MXR_STATUS_ENDIAN_MASK (1 << 3) |
||||
#define MXR_STATUS_SYNC_ENABLE (1 << 2) |
||||
#define MXR_STATUS_REG_RUN (1 << 0) |
||||
|
||||
/* bits for MXR_CFG */ |
||||
#define MXR_CFG_RGB601_0_255 (0 << 9) |
||||
#define MXR_CFG_RGB601_16_235 (1 << 9) |
||||
#define MXR_CFG_RGB709_0_255 (2 << 9) |
||||
#define MXR_CFG_RGB709_16_235 (3 << 9) |
||||
#define MXR_CFG_RGB_FMT_MASK 0x600 |
||||
#define MXR_CFG_OUT_YUV444 (0 << 8) |
||||
#define MXR_CFG_OUT_RGB888 (1 << 8) |
||||
#define MXR_CFG_OUT_MASK (1 << 8) |
||||
#define MXR_CFG_DST_SDO (0 << 7) |
||||
#define MXR_CFG_DST_HDMI (1 << 7) |
||||
#define MXR_CFG_DST_MASK (1 << 7) |
||||
#define MXR_CFG_SCAN_HD_720 (0 << 6) |
||||
#define MXR_CFG_SCAN_HD_1080 (1 << 6) |
||||
#define MXR_CFG_GRP1_ENABLE (1 << 5) |
||||
#define MXR_CFG_GRP0_ENABLE (1 << 4) |
||||
#define MXR_CFG_VP_ENABLE (1 << 3) |
||||
#define MXR_CFG_SCAN_INTERLACE (0 << 2) |
||||
#define MXR_CFG_SCAN_PROGRASSIVE (1 << 2) |
||||
#define MXR_CFG_SCAN_NTSC (0 << 1) |
||||
#define MXR_CFG_SCAN_PAL (1 << 1) |
||||
#define MXR_CFG_SCAN_SD (0 << 0) |
||||
#define MXR_CFG_SCAN_HD (1 << 0) |
||||
#define MXR_CFG_SCAN_MASK 0x47 |
||||
|
||||
/* bits for MXR_GRAPHICn_CFG */ |
||||
#define MXR_GRP_CFG_COLOR_KEY_DISABLE (1 << 21) |
||||
#define MXR_GRP_CFG_BLEND_PRE_MUL (1 << 20) |
||||
#define MXR_GRP_CFG_WIN_BLEND_EN (1 << 17) |
||||
#define MXR_GRP_CFG_PIXEL_BLEND_EN (1 << 16) |
||||
#define MXR_GRP_CFG_FORMAT_VAL(x) MXR_MASK_VAL(x, 11, 8) |
||||
#define MXR_GRP_CFG_FORMAT_MASK MXR_GRP_CFG_FORMAT_VAL(~0) |
||||
#define MXR_GRP_CFG_ALPHA_VAL(x) MXR_MASK_VAL(x, 7, 0) |
||||
|
||||
/* bits for MXR_GRAPHICn_WH */ |
||||
#define MXR_GRP_WH_H_SCALE(x) MXR_MASK_VAL(x, 28, 28) |
||||
#define MXR_GRP_WH_V_SCALE(x) MXR_MASK_VAL(x, 12, 12) |
||||
#define MXR_GRP_WH_WIDTH(x) MXR_MASK_VAL(x, 26, 16) |
||||
#define MXR_GRP_WH_HEIGHT(x) MXR_MASK_VAL(x, 10, 0) |
||||
|
||||
/* bits for MXR_GRAPHICn_SXY */ |
||||
#define MXR_GRP_SXY_SX(x) MXR_MASK_VAL(x, 26, 16) |
||||
#define MXR_GRP_SXY_SY(x) MXR_MASK_VAL(x, 10, 0) |
||||
|
||||
/* bits for MXR_GRAPHICn_DXY */ |
||||
#define MXR_GRP_DXY_DX(x) MXR_MASK_VAL(x, 26, 16) |
||||
#define MXR_GRP_DXY_DY(x) MXR_MASK_VAL(x, 10, 0) |
||||
|
||||
/* bits for MXR_INT_EN */ |
||||
#define MXR_INT_EN_VSYNC (1 << 11) |
||||
#define MXR_INT_EN_ALL (0x0f << 8) |
||||
|
||||
/* bit for MXR_INT_STATUS */ |
||||
#define MXR_INT_CLEAR_VSYNC (1 << 11) |
||||
#define MXR_INT_STATUS_VSYNC (1 << 0) |
||||
|
||||
/* bit for MXR_LAYER_CFG */ |
||||
#define MXR_LAYER_CFG_GRP1_VAL(x) MXR_MASK_VAL(x, 11, 8) |
||||
#define MXR_LAYER_CFG_GRP0_VAL(x) MXR_MASK_VAL(x, 7, 4) |
||||
#define MXR_LAYER_CFG_VP_VAL(x) MXR_MASK_VAL(x, 3, 0) |
||||
|
||||
#endif /* SAMSUNG_REGS_MIXER_H */ |
||||
|
@ -0,0 +1,91 @@ |
||||
/*
|
||||
* |
||||
* Cloned from drivers/media/video/s5p-tv/regs-vp.h |
||||
* |
||||
* Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. |
||||
* http://www.samsung.com/
|
||||
* |
||||
* Video processor register header file for Samsung Mixer driver |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
*/ |
||||
|
||||
#ifndef SAMSUNG_REGS_VP_H |
||||
#define SAMSUNG_REGS_VP_H |
||||
|
||||
/*
|
||||
* Register part |
||||
*/ |
||||
|
||||
#define VP_ENABLE 0x0000 |
||||
#define VP_SRESET 0x0004 |
||||
#define VP_SHADOW_UPDATE 0x0008 |
||||
#define VP_FIELD_ID 0x000C |
||||
#define VP_MODE 0x0010 |
||||
#define VP_IMG_SIZE_Y 0x0014 |
||||
#define VP_IMG_SIZE_C 0x0018 |
||||
#define VP_PER_RATE_CTRL 0x001C |
||||
#define VP_TOP_Y_PTR 0x0028 |
||||
#define VP_BOT_Y_PTR 0x002C |
||||
#define VP_TOP_C_PTR 0x0030 |
||||
#define VP_BOT_C_PTR 0x0034 |
||||
#define VP_ENDIAN_MODE 0x03CC |
||||
#define VP_SRC_H_POSITION 0x0044 |
||||
#define VP_SRC_V_POSITION 0x0048 |
||||
#define VP_SRC_WIDTH 0x004C |
||||
#define VP_SRC_HEIGHT 0x0050 |
||||
#define VP_DST_H_POSITION 0x0054 |
||||
#define VP_DST_V_POSITION 0x0058 |
||||
#define VP_DST_WIDTH 0x005C |
||||
#define VP_DST_HEIGHT 0x0060 |
||||
#define VP_H_RATIO 0x0064 |
||||
#define VP_V_RATIO 0x0068 |
||||
#define VP_POLY8_Y0_LL 0x006C |
||||
#define VP_POLY4_Y0_LL 0x00EC |
||||
#define VP_POLY4_C0_LL 0x012C |
||||
|
||||
/*
|
||||
* Bit definition part |
||||
*/ |
||||
|
||||
/* generates mask for range of bits */ |
||||
|
||||
#define VP_MASK(high_bit, low_bit) \ |
||||
(((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) |
||||
|
||||
#define VP_MASK_VAL(val, high_bit, low_bit) \ |
||||
(((val) << (low_bit)) & VP_MASK(high_bit, low_bit)) |
||||
|
||||
/* VP_ENABLE */ |
||||
#define VP_ENABLE_ON (1 << 0) |
||||
|
||||
/* VP_SRESET */ |
||||
#define VP_SRESET_PROCESSING (1 << 0) |
||||
|
||||
/* VP_SHADOW_UPDATE */ |
||||
#define VP_SHADOW_UPDATE_ENABLE (1 << 0) |
||||
|
||||
/* VP_MODE */ |
||||
#define VP_MODE_NV12 (0 << 6) |
||||
#define VP_MODE_NV21 (1 << 6) |
||||
#define VP_MODE_LINE_SKIP (1 << 5) |
||||
#define VP_MODE_MEM_LINEAR (0 << 4) |
||||
#define VP_MODE_MEM_TILED (1 << 4) |
||||
#define VP_MODE_FMT_MASK (5 << 4) |
||||
#define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2) |
||||
#define VP_MODE_2D_IPC (1 << 1) |
||||
|
||||
/* VP_IMG_SIZE_Y */ |
||||
/* VP_IMG_SIZE_C */ |
||||
#define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16) |
||||
#define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0) |
||||
|
||||
/* VP_SRC_H_POSITION */ |
||||
#define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4) |
||||
|
||||
/* VP_ENDIAN_MODE */ |
||||
#define VP_ENDIAN_MODE_LITTLE (1 << 0) |
||||
|
||||
#endif /* SAMSUNG_REGS_VP_H */ |
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Reference in new issue