This commit migrates the mach-dove platforms to use the mvebu-mbus driver and therefore removes the Dove-specific addr-map code. The dove_init_early() function now initializes the mvebu-mbus driver by calling mvebu_mbus_init(). The address decoding windows are now registered in the dove_setup_cpu_wins() function. It is worth noting that the four PCIe address decoding windows will ultimately no longer have to be registered here: it will be done automatically by the PCIe driver once Dove has been migrated to use the upcoming mvebu PCIe driver. Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com> Acked-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Jason Cooper <jason@lakedaemon.net>tirimbino
Thomas Petazzoni
12 years ago
committed by
Jason Cooper
parent
5cc0673a67
commit
7d55490277
@ -1,125 +0,0 @@ |
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/*
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* arch/arm/mach-dove/addr-map.c |
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* |
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* Address map functions for Marvell Dove 88AP510 SoC |
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* |
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* This file is licensed under the terms of the GNU General Public |
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* License version 2. This program is licensed "as is" without any |
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* warranty of any kind, whether express or implied. |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/mbus.h> |
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#include <linux/io.h> |
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#include <asm/mach/arch.h> |
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#include <asm/setup.h> |
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#include <mach/dove.h> |
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#include <plat/addr-map.h> |
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#include "common.h" |
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/*
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* Generic Address Decode Windows bit settings |
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*/ |
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#define TARGET_DDR 0x0 |
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#define TARGET_BOOTROM 0x1 |
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#define TARGET_CESA 0x3 |
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#define TARGET_PCIE0 0x4 |
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#define TARGET_PCIE1 0x8 |
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#define TARGET_SCRATCHPAD 0xd |
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#define ATTR_CESA 0x01 |
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#define ATTR_BOOTROM 0xfd |
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#define ATTR_DEV_SPI0_ROM 0xfe |
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#define ATTR_DEV_SPI1_ROM 0xfb |
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#define ATTR_PCIE_IO 0xe0 |
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#define ATTR_PCIE_MEM 0xe8 |
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#define ATTR_SCRATCHPAD 0x0 |
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static inline void __iomem *ddr_map_sc(int i) |
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{ |
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return (void __iomem *)(DOVE_MC_VIRT_BASE + 0x100 + ((i) << 4)); |
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} |
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/*
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* Description of the windows needed by the platform code |
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*/ |
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static struct __initdata orion_addr_map_cfg addr_map_cfg = { |
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.num_wins = 8, |
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.remappable_wins = 4, |
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.bridge_virt_base = BRIDGE_VIRT_BASE, |
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}; |
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static const struct __initdata orion_addr_map_info addr_map_info[] = { |
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/*
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* Windows for PCIe IO+MEM space. |
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*/ |
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{ 0, DOVE_PCIE0_IO_PHYS_BASE, DOVE_PCIE0_IO_SIZE, |
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TARGET_PCIE0, ATTR_PCIE_IO, DOVE_PCIE0_IO_BUS_BASE |
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}, |
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{ 1, DOVE_PCIE1_IO_PHYS_BASE, DOVE_PCIE1_IO_SIZE, |
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TARGET_PCIE1, ATTR_PCIE_IO, DOVE_PCIE1_IO_BUS_BASE |
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}, |
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{ 2, DOVE_PCIE0_MEM_PHYS_BASE, DOVE_PCIE0_MEM_SIZE, |
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TARGET_PCIE0, ATTR_PCIE_MEM, -1 |
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}, |
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{ 3, DOVE_PCIE1_MEM_PHYS_BASE, DOVE_PCIE1_MEM_SIZE, |
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TARGET_PCIE1, ATTR_PCIE_MEM, -1 |
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}, |
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/*
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* Window for CESA engine. |
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*/ |
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{ 4, DOVE_CESA_PHYS_BASE, DOVE_CESA_SIZE, |
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TARGET_CESA, ATTR_CESA, -1 |
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}, |
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/*
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* Window to the BootROM for Standby and Sleep Resume |
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*/ |
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{ 5, DOVE_BOOTROM_PHYS_BASE, DOVE_BOOTROM_SIZE, |
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TARGET_BOOTROM, ATTR_BOOTROM, -1 |
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}, |
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/*
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* Window to the PMU Scratch Pad space |
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*/ |
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{ 6, DOVE_SCRATCHPAD_PHYS_BASE, DOVE_SCRATCHPAD_SIZE, |
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TARGET_SCRATCHPAD, ATTR_SCRATCHPAD, -1 |
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}, |
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/* End marker */ |
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{ -1, 0, 0, 0, 0, 0 } |
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}; |
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void __init dove_setup_cpu_mbus(void) |
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{ |
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int i; |
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int cs; |
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/*
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* Disable, clear and configure windows. |
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*/ |
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orion_config_wins(&addr_map_cfg, addr_map_info); |
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/*
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* Setup MBUS dram target info. |
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*/ |
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orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR; |
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for (i = 0, cs = 0; i < 2; i++) { |
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u32 map = readl(ddr_map_sc(i)); |
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/*
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* Chip select enabled? |
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*/ |
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if (map & 1) { |
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struct mbus_dram_window *w; |
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w = &orion_mbus_dram_info.cs[cs++]; |
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w->cs_index = i; |
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w->mbus_attr = 0; /* CS address decoding done inside */ |
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/* the DDR controller, no need to */ |
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/* provide attributes */ |
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w->base = map & 0xff800000; |
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w->size = 0x100000 << (((map & 0x000f0000) >> 16) - 4); |
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} |
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} |
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orion_mbus_dram_info.num_cs = cs; |
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} |
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