Add the GPIO driver for the Broadcom bcm281xx family of mobile SoCs. These GPIO controllers may contain up to 8 banks where each bank includes 32 pins that can be driven high or low and act as an edge sensitive interrupt. Signed-off-by: Markus Mayer <markus.mayer@linaro.org> Reviewed-by: Christian Daudt <csd@broadcom.com> Reviewed-by: Tim Kryger <tim.kryger@linaro.org> Reviewed-by: Matt Porter <matt.porter@linaro.org> Reviewed-by: Stephen Warren <swarren@nvidia.com> [Added depends on OF_GPIO] Signed-off-by: Linus Walleij <linus.walleij@linaro.org>tirimbino
Markus Mayer
12 years ago
committed by
Linus Walleij
parent
d8e0ac0824
commit
757651e3d6
@ -0,0 +1,52 @@ |
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Broadcom Kona Family GPIO |
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========================= |
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|
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This GPIO driver is used in the following Broadcom SoCs: |
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BCM11130, BCM11140, BCM11351, BCM28145, BCM28155 |
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|
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The Broadcom GPIO Controller IP can be configured prior to synthesis to |
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support up to 8 banks of 32 GPIOs where each bank has its own IRQ. The |
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GPIO controller only supports edge, not level, triggering of interrupts. |
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|
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Required properties |
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------------------- |
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|
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- compatible: "brcm,bcm11351-gpio", "brcm,kona-gpio" |
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- reg: Physical base address and length of the controller's registers. |
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- interrupts: The interrupt outputs from the controller. There is one GPIO |
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interrupt per GPIO bank. The number of interrupts listed depends on the |
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number of GPIO banks on the SoC. The interrupts must be ordered by bank, |
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starting with bank 0. There is always a 1:1 mapping between banks and |
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IRQs. |
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- #gpio-cells: Should be <2>. The first cell is the pin number, the second |
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cell is used to specify optional parameters: |
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- bit 0 specifies polarity (0 for normal, 1 for inverted) |
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See also "gpio-specifier" in .../devicetree/bindings/gpio/gpio.txt. |
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- #interrupt-cells: Should be <2>. The first cell is the GPIO number. The |
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second cell is used to specify flags. The following subset of flags is |
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supported: |
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- trigger type (bits[1:0]): |
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1 = low-to-high edge triggered. |
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2 = high-to-low edge triggered. |
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3 = low-to-high or high-to-low edge triggered |
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Valid values are 1, 2, 3 |
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See also .../devicetree/bindings/interrupt-controller/interrupts.txt. |
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- gpio-controller: Marks the device node as a GPIO controller. |
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- interrupt-controller: Marks the device node as an interrupt controller. |
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|
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Example: |
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gpio: gpio@35003000 { |
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compatible = "brcm,bcm11351-gpio", "brcm,kona-gpio"; |
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reg = <0x35003000 0x800>; |
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interrupts = |
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<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH |
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GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH |
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GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH |
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GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH |
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GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH |
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GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; |
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#gpio-cells = <2>; |
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#interrupt-cells = <2>; |
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gpio-controller; |
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interrupt-controller; |
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}; |
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@ -0,0 +1,632 @@ |
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/*
|
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* Copyright (C) 2012-2013 Broadcom Corporation |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <linux/bitops.h> |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/gpio.h> |
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#include <linux/of_device.h> |
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#include <linux/of_irq.h> |
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#include <linux/module.h> |
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#include <linux/irqdomain.h> |
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#include <linux/irqchip/chained_irq.h> |
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|
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#define BCM_GPIO_PASSWD 0x00a5a501 |
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#define GPIO_PER_BANK 32 |
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#define GPIO_MAX_BANK_NUM 8 |
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|
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#define GPIO_BANK(gpio) ((gpio) >> 5) |
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#define GPIO_BIT(gpio) ((gpio) & (GPIO_PER_BANK - 1)) |
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|
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#define GPIO_OUT_STATUS(bank) (0x00000000 + ((bank) << 2)) |
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#define GPIO_IN_STATUS(bank) (0x00000020 + ((bank) << 2)) |
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#define GPIO_OUT_SET(bank) (0x00000040 + ((bank) << 2)) |
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#define GPIO_OUT_CLEAR(bank) (0x00000060 + ((bank) << 2)) |
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#define GPIO_INT_STATUS(bank) (0x00000080 + ((bank) << 2)) |
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#define GPIO_INT_MASK(bank) (0x000000a0 + ((bank) << 2)) |
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#define GPIO_INT_MSKCLR(bank) (0x000000c0 + ((bank) << 2)) |
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#define GPIO_CONTROL(bank) (0x00000100 + ((bank) << 2)) |
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#define GPIO_PWD_STATUS(bank) (0x00000500 + ((bank) << 2)) |
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|
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#define GPIO_GPPWR_OFFSET 0x00000520 |
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|
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#define GPIO_GPCTR0_DBR_SHIFT 5 |
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#define GPIO_GPCTR0_DBR_MASK 0x000001e0 |
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|
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#define GPIO_GPCTR0_ITR_SHIFT 3 |
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#define GPIO_GPCTR0_ITR_MASK 0x00000018 |
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#define GPIO_GPCTR0_ITR_CMD_RISING_EDGE 0x00000001 |
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#define GPIO_GPCTR0_ITR_CMD_FALLING_EDGE 0x00000002 |
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#define GPIO_GPCTR0_ITR_CMD_BOTH_EDGE 0x00000003 |
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|
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#define GPIO_GPCTR0_IOTR_MASK 0x00000001 |
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#define GPIO_GPCTR0_IOTR_CMD_0UTPUT 0x00000000 |
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#define GPIO_GPCTR0_IOTR_CMD_INPUT 0x00000001 |
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|
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#define GPIO_GPCTR0_DB_ENABLE_MASK 0x00000100 |
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|
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#define LOCK_CODE 0xffffffff |
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#define UNLOCK_CODE 0x00000000 |
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|
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struct bcm_kona_gpio { |
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void __iomem *reg_base; |
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int num_bank; |
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spinlock_t lock; |
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struct gpio_chip gpio_chip; |
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struct irq_domain *irq_domain; |
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struct bcm_kona_gpio_bank *banks; |
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struct platform_device *pdev; |
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}; |
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|
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struct bcm_kona_gpio_bank { |
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int id; |
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int irq; |
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/* Used in the interrupt handler */ |
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struct bcm_kona_gpio *kona_gpio; |
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}; |
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|
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static inline struct bcm_kona_gpio *to_kona_gpio(struct gpio_chip *chip) |
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{ |
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return container_of(chip, struct bcm_kona_gpio, gpio_chip); |
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} |
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|
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static void bcm_kona_gpio_set_lockcode_bank(void __iomem *reg_base, |
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int bank_id, int lockcode) |
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{ |
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writel(BCM_GPIO_PASSWD, reg_base + GPIO_GPPWR_OFFSET); |
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writel(lockcode, reg_base + GPIO_PWD_STATUS(bank_id)); |
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} |
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|
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static inline void bcm_kona_gpio_lock_bank(void __iomem *reg_base, int bank_id) |
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{ |
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bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, LOCK_CODE); |
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} |
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|
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static inline void bcm_kona_gpio_unlock_bank(void __iomem *reg_base, |
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int bank_id) |
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{ |
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bcm_kona_gpio_set_lockcode_bank(reg_base, bank_id, UNLOCK_CODE); |
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} |
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|
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static void bcm_kona_gpio_set(struct gpio_chip *chip, unsigned gpio, int value) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val, reg_offset; |
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unsigned long flags; |
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kona_gpio = to_kona_gpio(chip); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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/* determine the GPIO pin direction */ |
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= GPIO_GPCTR0_IOTR_MASK; |
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|
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/* this function only applies to output pin */ |
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if (GPIO_GPCTR0_IOTR_CMD_INPUT == val) |
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goto out; |
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); |
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val = readl(reg_base + reg_offset); |
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val |= BIT(bit); |
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writel(val, reg_base + reg_offset); |
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out: |
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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} |
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|
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static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val, reg_offset; |
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unsigned long flags; |
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kona_gpio = to_kona_gpio(chip); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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/* determine the GPIO pin direction */ |
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= GPIO_GPCTR0_IOTR_MASK; |
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|
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/* read the GPIO bank status */ |
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reg_offset = (GPIO_GPCTR0_IOTR_CMD_INPUT == val) ? |
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GPIO_IN_STATUS(bank_id) : GPIO_OUT_STATUS(bank_id); |
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val = readl(reg_base + reg_offset); |
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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/* return the specified bit status */ |
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return !!(val & bit); |
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} |
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static int bcm_kona_gpio_direction_input(struct gpio_chip *chip, unsigned gpio) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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u32 val; |
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unsigned long flags; |
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int bank_id = GPIO_BANK(gpio); |
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kona_gpio = to_kona_gpio(chip); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= ~GPIO_GPCTR0_IOTR_MASK; |
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val |= GPIO_GPCTR0_IOTR_CMD_INPUT; |
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writel(val, reg_base + GPIO_CONTROL(gpio)); |
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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return 0; |
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} |
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static int bcm_kona_gpio_direction_output(struct gpio_chip *chip, |
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unsigned gpio, int value) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val, reg_offset; |
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unsigned long flags; |
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kona_gpio = to_kona_gpio(chip); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= ~GPIO_GPCTR0_IOTR_MASK; |
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val |= GPIO_GPCTR0_IOTR_CMD_0UTPUT; |
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writel(val, reg_base + GPIO_CONTROL(gpio)); |
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reg_offset = value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); |
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val = readl(reg_base + reg_offset); |
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val |= BIT(bit); |
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writel(val, reg_base + reg_offset); |
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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return 0; |
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} |
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static int bcm_kona_gpio_to_irq(struct gpio_chip *chip, unsigned gpio) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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kona_gpio = to_kona_gpio(chip); |
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if (gpio >= kona_gpio->gpio_chip.ngpio) |
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return -ENXIO; |
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return irq_create_mapping(kona_gpio->irq_domain, gpio); |
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} |
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static int bcm_kona_gpio_set_debounce(struct gpio_chip *chip, unsigned gpio, |
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unsigned debounce) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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u32 val, res; |
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unsigned long flags; |
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int bank_id = GPIO_BANK(gpio); |
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kona_gpio = to_kona_gpio(chip); |
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reg_base = kona_gpio->reg_base; |
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/* debounce must be 1-128ms (or 0) */ |
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if ((debounce > 0 && debounce < 1000) || debounce > 128000) { |
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dev_err(chip->dev, "Debounce value %u not in range\n", |
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debounce); |
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return -EINVAL; |
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} |
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|
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/* calculate debounce bit value */ |
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if (debounce != 0) { |
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/* Convert to ms */ |
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debounce /= 1000; |
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/* find the MSB */ |
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res = fls(debounce) - 1; |
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/* Check if MSB-1 is set (round up or down) */ |
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if (res > 0 && (debounce & BIT(res - 1))) |
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res++; |
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} |
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|
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/* spin lock for read-modify-write of the GPIO register */ |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= ~GPIO_GPCTR0_DBR_MASK; |
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|
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if (debounce == 0) { |
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/* disable debounce */ |
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val &= ~GPIO_GPCTR0_DB_ENABLE_MASK; |
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} else { |
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val |= GPIO_GPCTR0_DB_ENABLE_MASK | |
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(res << GPIO_GPCTR0_DBR_SHIFT); |
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} |
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|
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writel(val, reg_base + GPIO_CONTROL(gpio)); |
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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return 0; |
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} |
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|
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static struct gpio_chip template_chip = { |
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.label = "bcm-kona-gpio", |
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.direction_input = bcm_kona_gpio_direction_input, |
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.get = bcm_kona_gpio_get, |
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.direction_output = bcm_kona_gpio_direction_output, |
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.set = bcm_kona_gpio_set, |
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.set_debounce = bcm_kona_gpio_set_debounce, |
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.to_irq = bcm_kona_gpio_to_irq, |
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.base = 0, |
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}; |
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|
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static void bcm_kona_gpio_irq_ack(struct irq_data *d) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int gpio = d->hwirq; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val; |
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unsigned long flags; |
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|
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kona_gpio = irq_data_get_irq_chip_data(d); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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val = readl(reg_base + GPIO_INT_STATUS(bank_id)); |
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val |= BIT(bit); |
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writel(val, reg_base + GPIO_INT_STATUS(bank_id)); |
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|
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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} |
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|
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static void bcm_kona_gpio_irq_mask(struct irq_data *d) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int gpio = d->hwirq; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val; |
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unsigned long flags; |
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|
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kona_gpio = irq_data_get_irq_chip_data(d); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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val = readl(reg_base + GPIO_INT_MASK(bank_id)); |
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val |= BIT(bit); |
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writel(val, reg_base + GPIO_INT_MASK(bank_id)); |
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|
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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} |
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|
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static void bcm_kona_gpio_irq_unmask(struct irq_data *d) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int gpio = d->hwirq; |
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int bank_id = GPIO_BANK(gpio); |
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int bit = GPIO_BIT(gpio); |
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u32 val; |
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unsigned long flags; |
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|
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kona_gpio = irq_data_get_irq_chip_data(d); |
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reg_base = kona_gpio->reg_base; |
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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val = readl(reg_base + GPIO_INT_MSKCLR(bank_id)); |
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val |= BIT(bit); |
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writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); |
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|
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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} |
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|
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static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int type) |
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{ |
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struct bcm_kona_gpio *kona_gpio; |
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void __iomem *reg_base; |
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int gpio = d->hwirq; |
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u32 lvl_type; |
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u32 val; |
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unsigned long flags; |
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int bank_id = GPIO_BANK(gpio); |
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|
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kona_gpio = irq_data_get_irq_chip_data(d); |
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reg_base = kona_gpio->reg_base; |
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switch (type & IRQ_TYPE_SENSE_MASK) { |
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case IRQ_TYPE_EDGE_RISING: |
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lvl_type = GPIO_GPCTR0_ITR_CMD_RISING_EDGE; |
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break; |
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|
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case IRQ_TYPE_EDGE_FALLING: |
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lvl_type = GPIO_GPCTR0_ITR_CMD_FALLING_EDGE; |
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break; |
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|
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case IRQ_TYPE_EDGE_BOTH: |
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lvl_type = GPIO_GPCTR0_ITR_CMD_BOTH_EDGE; |
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break; |
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|
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case IRQ_TYPE_LEVEL_HIGH: |
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case IRQ_TYPE_LEVEL_LOW: |
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/* BCM GPIO doesn't support level triggering */ |
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default: |
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dev_err(kona_gpio->gpio_chip.dev, |
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"Invalid BCM GPIO irq type 0x%x\n", type); |
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return -EINVAL; |
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} |
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|
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spin_lock_irqsave(&kona_gpio->lock, flags); |
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bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
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|
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val = readl(reg_base + GPIO_CONTROL(gpio)); |
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val &= ~GPIO_GPCTR0_ITR_MASK; |
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val |= lvl_type << GPIO_GPCTR0_ITR_SHIFT; |
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writel(val, reg_base + GPIO_CONTROL(gpio)); |
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|
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bcm_kona_gpio_lock_bank(reg_base, bank_id); |
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spin_unlock_irqrestore(&kona_gpio->lock, flags); |
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|
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return 0; |
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} |
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|
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static void bcm_kona_gpio_irq_handler(unsigned int irq, struct irq_desc *desc) |
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{ |
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void __iomem *reg_base; |
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int bit, bank_id; |
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unsigned long sta; |
||||
struct bcm_kona_gpio_bank *bank = irq_get_handler_data(irq); |
||||
struct irq_chip *chip = irq_desc_get_chip(desc); |
||||
|
||||
chained_irq_enter(chip, desc); |
||||
|
||||
/*
|
||||
* For bank interrupts, we can't use chip_data to store the kona_gpio |
||||
* pointer, since GIC needs it for its own purposes. Therefore, we get |
||||
* our pointer from the bank structure. |
||||
*/ |
||||
reg_base = bank->kona_gpio->reg_base; |
||||
bank_id = bank->id; |
||||
bcm_kona_gpio_unlock_bank(reg_base, bank_id); |
||||
|
||||
while ((sta = readl(reg_base + GPIO_INT_STATUS(bank_id)) & |
||||
(~(readl(reg_base + GPIO_INT_MASK(bank_id)))))) { |
||||
for_each_set_bit(bit, &sta, 32) { |
||||
int gpio = GPIO_PER_BANK * bank_id + bit; |
||||
int virq = irq_find_mapping(bank->kona_gpio->irq_domain, |
||||
gpio); |
||||
/*
|
||||
* Clear interrupt before handler is called so we don't |
||||
* miss any interrupt occurred during executing them. |
||||
*/ |
||||
writel(readl(reg_base + GPIO_INT_STATUS(bank_id)) | |
||||
BIT(bit), reg_base + GPIO_INT_STATUS(bank_id)); |
||||
/* Invoke interrupt handler */ |
||||
generic_handle_irq(virq); |
||||
} |
||||
} |
||||
|
||||
bcm_kona_gpio_lock_bank(reg_base, bank_id); |
||||
|
||||
chained_irq_exit(chip, desc); |
||||
} |
||||
|
||||
static struct irq_chip bcm_gpio_irq_chip = { |
||||
.name = "bcm-kona-gpio", |
||||
.irq_ack = bcm_kona_gpio_irq_ack, |
||||
.irq_mask = bcm_kona_gpio_irq_mask, |
||||
.irq_unmask = bcm_kona_gpio_irq_unmask, |
||||
.irq_set_type = bcm_kona_gpio_irq_set_type, |
||||
}; |
||||
|
||||
static struct __initconst of_device_id bcm_kona_gpio_of_match[] = { |
||||
{ .compatible = "brcm,kona-gpio" }, |
||||
{} |
||||
}; |
||||
|
||||
MODULE_DEVICE_TABLE(of, bcm_kona_gpio_of_match); |
||||
|
||||
/*
|
||||
* This lock class tells lockdep that GPIO irqs are in a different |
||||
* category than their parents, so it won't report false recursion. |
||||
*/ |
||||
static struct lock_class_key gpio_lock_class; |
||||
|
||||
static int bcm_kona_gpio_irq_map(struct irq_domain *d, unsigned int virq, |
||||
irq_hw_number_t hwirq) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = irq_set_chip_data(virq, d->host_data); |
||||
if (ret < 0) |
||||
return ret; |
||||
irq_set_lockdep_class(virq, &gpio_lock_class); |
||||
irq_set_chip_and_handler(virq, &bcm_gpio_irq_chip, handle_simple_irq); |
||||
irq_set_nested_thread(virq, 1); |
||||
set_irq_flags(virq, IRQF_VALID); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void bcm_kona_gpio_irq_unmap(struct irq_domain *d, unsigned int virq) |
||||
{ |
||||
irq_set_chip_and_handler(virq, NULL, NULL); |
||||
irq_set_chip_data(virq, NULL); |
||||
} |
||||
|
||||
static struct irq_domain_ops bcm_kona_irq_ops = { |
||||
.map = bcm_kona_gpio_irq_map, |
||||
.unmap = bcm_kona_gpio_irq_unmap, |
||||
.xlate = irq_domain_xlate_twocell, |
||||
}; |
||||
|
||||
static void bcm_kona_gpio_reset(struct bcm_kona_gpio *kona_gpio) |
||||
{ |
||||
void __iomem *reg_base; |
||||
int i; |
||||
|
||||
reg_base = kona_gpio->reg_base; |
||||
/* disable interrupts and clear status */ |
||||
for (i = 0; i < kona_gpio->num_bank; i++) { |
||||
bcm_kona_gpio_unlock_bank(reg_base, i); |
||||
writel(0xffffffff, reg_base + GPIO_INT_MASK(i)); |
||||
writel(0xffffffff, reg_base + GPIO_INT_STATUS(i)); |
||||
bcm_kona_gpio_lock_bank(reg_base, i); |
||||
} |
||||
} |
||||
|
||||
static int bcm_kona_gpio_probe(struct platform_device *pdev) |
||||
{ |
||||
struct device *dev = &pdev->dev; |
||||
const struct of_device_id *match; |
||||
struct resource *res; |
||||
struct bcm_kona_gpio_bank *bank; |
||||
struct bcm_kona_gpio *kona_gpio; |
||||
struct gpio_chip *chip; |
||||
int ret; |
||||
int i; |
||||
|
||||
match = of_match_device(bcm_kona_gpio_of_match, dev); |
||||
if (!match) { |
||||
dev_err(dev, "Failed to find gpio controller\n"); |
||||
return -ENODEV; |
||||
} |
||||
|
||||
kona_gpio = devm_kzalloc(dev, sizeof(*kona_gpio), GFP_KERNEL); |
||||
if (!kona_gpio) |
||||
return -ENOMEM; |
||||
|
||||
kona_gpio->gpio_chip = template_chip; |
||||
chip = &kona_gpio->gpio_chip; |
||||
kona_gpio->num_bank = of_irq_count(dev->of_node); |
||||
if (kona_gpio->num_bank == 0) { |
||||
dev_err(dev, "Couldn't determine # GPIO banks\n"); |
||||
return -ENOENT; |
||||
} |
||||
if (kona_gpio->num_bank > GPIO_MAX_BANK_NUM) { |
||||
dev_err(dev, "Too many GPIO banks configured (max=%d)\n", |
||||
GPIO_MAX_BANK_NUM); |
||||
return -ENXIO; |
||||
} |
||||
kona_gpio->banks = devm_kzalloc(dev, |
||||
kona_gpio->num_bank * |
||||
sizeof(*kona_gpio->banks), GFP_KERNEL); |
||||
if (!kona_gpio->banks) |
||||
return -ENOMEM; |
||||
|
||||
kona_gpio->pdev = pdev; |
||||
platform_set_drvdata(pdev, kona_gpio); |
||||
chip->of_node = dev->of_node; |
||||
chip->ngpio = kona_gpio->num_bank * GPIO_PER_BANK; |
||||
|
||||
kona_gpio->irq_domain = irq_domain_add_linear(dev->of_node, |
||||
chip->ngpio, |
||||
&bcm_kona_irq_ops, |
||||
kona_gpio); |
||||
if (!kona_gpio->irq_domain) { |
||||
dev_err(dev, "Couldn't allocate IRQ domain\n"); |
||||
return -ENXIO; |
||||
} |
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
kona_gpio->reg_base = devm_ioremap_resource(dev, res); |
||||
if (IS_ERR(kona_gpio->reg_base)) { |
||||
ret = -ENXIO; |
||||
goto err_irq_domain; |
||||
} |
||||
|
||||
for (i = 0; i < kona_gpio->num_bank; i++) { |
||||
bank = &kona_gpio->banks[i]; |
||||
bank->id = i; |
||||
bank->irq = platform_get_irq(pdev, i); |
||||
bank->kona_gpio = kona_gpio; |
||||
if (bank->irq < 0) { |
||||
dev_err(dev, "Couldn't get IRQ for bank %d", i); |
||||
ret = -ENOENT; |
||||
goto err_irq_domain; |
||||
} |
||||
} |
||||
|
||||
dev_info(&pdev->dev, "Setting up Kona GPIO at 0x%p (phys %#x)\n", |
||||
kona_gpio->reg_base, res->start); |
||||
|
||||
bcm_kona_gpio_reset(kona_gpio); |
||||
|
||||
ret = gpiochip_add(chip); |
||||
if (ret < 0) { |
||||
dev_err(dev, "Couldn't add GPIO chip -- %d\n", ret); |
||||
goto err_irq_domain; |
||||
} |
||||
for (i = 0; i < chip->ngpio; i++) { |
||||
int irq = bcm_kona_gpio_to_irq(chip, i); |
||||
irq_set_lockdep_class(irq, &gpio_lock_class); |
||||
irq_set_chip_and_handler(irq, &bcm_gpio_irq_chip, |
||||
handle_simple_irq); |
||||
set_irq_flags(irq, IRQF_VALID); |
||||
} |
||||
for (i = 0; i < kona_gpio->num_bank; i++) { |
||||
bank = &kona_gpio->banks[i]; |
||||
irq_set_chained_handler(bank->irq, bcm_kona_gpio_irq_handler); |
||||
irq_set_handler_data(bank->irq, bank); |
||||
} |
||||
|
||||
spin_lock_init(&kona_gpio->lock); |
||||
|
||||
return 0; |
||||
|
||||
err_irq_domain: |
||||
irq_domain_remove(kona_gpio->irq_domain); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static struct platform_driver bcm_kona_gpio_driver = { |
||||
.driver = { |
||||
.name = "bcm-kona-gpio", |
||||
.owner = THIS_MODULE, |
||||
.of_match_table = bcm_kona_gpio_of_match, |
||||
}, |
||||
.probe = bcm_kona_gpio_probe, |
||||
}; |
||||
|
||||
module_platform_driver(bcm_kona_gpio_driver); |
||||
|
||||
MODULE_AUTHOR("Broadcom"); |
||||
MODULE_DESCRIPTION("Broadcom Kona GPIO Driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
Loading…
Reference in new issue