- Rewrite Alchemy PCI support as a platform driver. - Fixup boards which have PCI. Run-tested on DB1500 and DB1550. Signed-off-by: Manuel Lauss <manuel.lauss@googlemail.com> To: Linux-MIPS <linux-mips@linux-mips.org> Patchwork: https://patchwork.linux-mips.org/patch/2706/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org> delete mode 100644 arch/mips/alchemy/common/pci.c delete mode 100644 arch/mips/pci/fixup-au1000.c delete mode 100644 arch/mips/pci/ops-au1000.c create mode 100644 arch/mips/pci/pci-alchemy.ctirimbino
Manuel Lauss
14 years ago
committed by
Ralf Baechle
parent
7cc2e272da
commit
7517de3486
@ -1,104 +0,0 @@ |
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/*
|
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* BRIEF MODULE DESCRIPTION |
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* Alchemy/AMD Au1x00 PCI support. |
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* |
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* Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. <source@mvista.com> |
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* |
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* Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org) |
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* |
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* Support for all devices (greater than 16) added by David Gathright. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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|
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <asm/mach-au1x00/au1000.h> |
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|
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/* TBD */ |
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static struct resource pci_io_resource = { |
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.start = PCI_IO_START, |
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.end = PCI_IO_END, |
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.name = "PCI IO space", |
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.flags = IORESOURCE_IO |
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}; |
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static struct resource pci_mem_resource = { |
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.start = PCI_MEM_START, |
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.end = PCI_MEM_END, |
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.name = "PCI memory space", |
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.flags = IORESOURCE_MEM |
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}; |
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|
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extern struct pci_ops au1x_pci_ops; |
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static struct pci_controller au1x_controller = { |
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.pci_ops = &au1x_pci_ops, |
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.io_resource = &pci_io_resource, |
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.mem_resource = &pci_mem_resource, |
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}; |
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|
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
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static unsigned long virt_io_addr; |
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#endif |
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static int __init au1x_pci_setup(void) |
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{ |
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extern void au1x_pci_cfg_init(void); |
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
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virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START, |
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Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1); |
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if (!virt_io_addr) { |
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printk(KERN_ERR "Unable to ioremap pci space\n"); |
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return 1; |
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} |
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au1x_controller.io_map_base = virt_io_addr; |
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#ifdef CONFIG_DMA_NONCOHERENT |
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{ |
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/*
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* Set the NC bit in controller for Au1500 pre-AC silicon |
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*/ |
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u32 prid = read_c0_prid(); |
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if ((prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) { |
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au_writel((1 << 16) | au_readl(Au1500_PCI_CFG), |
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Au1500_PCI_CFG); |
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printk(KERN_INFO "Non-coherent PCI accesses enabled\n"); |
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} |
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} |
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#endif |
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set_io_port_base(virt_io_addr); |
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#endif |
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au1x_pci_cfg_init(); |
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register_pci_controller(&au1x_controller); |
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return 0; |
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} |
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|
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arch_initcall(au1x_pci_setup); |
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@ -1,43 +0,0 @@ |
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/*
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* BRIEF MODULE DESCRIPTION |
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* Board specific PCI fixups. |
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* |
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* Copyright 2001-2003, 2008 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. <source@mvista.com> |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/pci.h> |
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#include <linux/init.h> |
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extern char irq_tab_alchemy[][5]; |
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int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
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{ |
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return irq_tab_alchemy[slot][pin]; |
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} |
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|
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/* Do platform specific device initialization at pci_enable_device() time */ |
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int pcibios_plat_dev_init(struct pci_dev *dev) |
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{ |
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return 0; |
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} |
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@ -1,308 +0,0 @@ |
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/*
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* BRIEF MODULE DESCRIPTION |
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* Alchemy/AMD Au1xx0 PCI support. |
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* |
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* Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. <source@mvista.com> |
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* |
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* Support for all devices (greater than 16) added by David Gathright. |
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* |
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* This program is free software; you can redistribute it and/or modify it |
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* under the terms of the GNU General Public License as published by the |
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* Free Software Foundation; either version 2 of the License, or (at your |
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* option) any later version. |
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* |
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* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN |
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* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, |
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT |
||||
* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF |
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* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON |
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* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF |
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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* You should have received a copy of the GNU General Public License along |
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* with this program; if not, write to the Free Software Foundation, Inc., |
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* 675 Mass Ave, Cambridge, MA 02139, USA. |
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*/ |
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/vmalloc.h> |
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#include <asm/mach-au1x00/au1000.h> |
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#undef DEBUG |
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#ifdef DEBUG |
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#define DBG(x...) printk(KERN_DEBUG x) |
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#else |
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#define DBG(x...) |
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#endif |
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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int (*board_pci_idsel)(unsigned int devsel, int assert); |
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void mod_wired_entry(int entry, unsigned long entrylo0, |
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unsigned long entrylo1, unsigned long entryhi, |
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unsigned long pagemask) |
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{ |
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unsigned long old_pagemask; |
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unsigned long old_ctx; |
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/* Save old context and create impossible VPN2 value */ |
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old_ctx = read_c0_entryhi() & 0xff; |
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old_pagemask = read_c0_pagemask(); |
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write_c0_index(entry); |
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write_c0_pagemask(pagemask); |
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write_c0_entryhi(entryhi); |
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write_c0_entrylo0(entrylo0); |
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write_c0_entrylo1(entrylo1); |
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tlb_write_indexed(); |
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write_c0_entryhi(old_ctx); |
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write_c0_pagemask(old_pagemask); |
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} |
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static struct vm_struct *pci_cfg_vm; |
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static int pci_cfg_wired_entry; |
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static unsigned long last_entryLo0, last_entryLo1; |
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/*
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* We can't ioremap the entire pci config space because it's too large. |
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* Nor can we call ioremap dynamically because some device drivers use |
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* the PCI config routines from within interrupt handlers and that |
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* becomes a problem in get_vm_area(). We use one wired TLB to handle |
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* all config accesses for all busses. |
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*/ |
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void __init au1x_pci_cfg_init(void) |
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{ |
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/* Reserve a wired entry for PCI config accesses */ |
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pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); |
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if (!pci_cfg_vm) |
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panic(KERN_ERR "PCI unable to get vm area\n"); |
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pci_cfg_wired_entry = read_c0_wired(); |
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add_wired_entry(0, 0, (unsigned long)pci_cfg_vm->addr, PM_4K); |
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last_entryLo0 = last_entryLo1 = 0xffffffff; |
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} |
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static int config_access(unsigned char access_type, struct pci_bus *bus, |
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unsigned int dev_fn, unsigned char where, u32 *data) |
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{ |
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#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) |
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unsigned int device = PCI_SLOT(dev_fn); |
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unsigned int function = PCI_FUNC(dev_fn); |
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unsigned long offset, status; |
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unsigned long cfg_base; |
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unsigned long flags; |
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int error = PCIBIOS_SUCCESSFUL; |
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unsigned long entryLo0, entryLo1; |
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if (device > 19) { |
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*data = 0xffffffff; |
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return -1; |
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} |
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local_irq_save(flags); |
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au_writel(((0x2000 << 16) | (au_readl(Au1500_PCI_STATCMD) & 0xffff)), |
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Au1500_PCI_STATCMD); |
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au_sync_udelay(1); |
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|
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/*
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* Allow board vendors to implement their own off-chip IDSEL. |
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* If it doesn't succeed, may as well bail out at this point. |
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*/ |
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if (board_pci_idsel && board_pci_idsel(device, 1) == 0) { |
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*data = 0xffffffff; |
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local_irq_restore(flags); |
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return -1; |
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} |
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|
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/* Setup the config window */ |
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if (bus->number == 0) |
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cfg_base = (1 << device) << 11; |
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else |
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cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); |
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|
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/* Setup the lower bits of the 36-bit address */ |
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offset = (function << 8) | (where & ~0x3); |
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/* Pick up any address that falls below the page mask */ |
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offset |= cfg_base & ~PAGE_MASK; |
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/* Page boundary */ |
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cfg_base = cfg_base & PAGE_MASK; |
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/*
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* To improve performance, if the current device is the same as |
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* the last device accessed, we don't touch the TLB. |
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*/ |
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entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; |
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entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; |
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if ((entryLo0 != last_entryLo0) || (entryLo1 != last_entryLo1)) { |
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mod_wired_entry(pci_cfg_wired_entry, entryLo0, entryLo1, |
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(unsigned long)pci_cfg_vm->addr, PM_4K); |
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last_entryLo0 = entryLo0; |
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last_entryLo1 = entryLo1; |
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} |
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if (access_type == PCI_ACCESS_WRITE) |
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au_writel(*data, (int)(pci_cfg_vm->addr + offset)); |
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else |
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*data = au_readl((int)(pci_cfg_vm->addr + offset)); |
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au_sync_udelay(2); |
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DBG("cfg_access %d bus->number %u dev %u at %x *data %x conf %lx\n", |
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access_type, bus->number, device, where, *data, offset); |
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/* Check master abort */ |
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status = au_readl(Au1500_PCI_STATCMD); |
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if (status & (1 << 29)) { |
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*data = 0xffffffff; |
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error = -1; |
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DBG("Au1x Master Abort\n"); |
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} else if ((status >> 28) & 0xf) { |
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DBG("PCI ERR detected: device %u, status %lx\n", |
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device, (status >> 28) & 0xf); |
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/* Clear errors */ |
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au_writel(status & 0xf000ffff, Au1500_PCI_STATCMD); |
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*data = 0xffffffff; |
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error = -1; |
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} |
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|
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/* Take away the IDSEL. */ |
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if (board_pci_idsel) |
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(void)board_pci_idsel(device, 0); |
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local_irq_restore(flags); |
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return error; |
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#endif |
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} |
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static int read_config_byte(struct pci_bus *bus, unsigned int devfn, |
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int where, u8 *val) |
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{ |
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u32 data; |
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int ret; |
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
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if (where & 1) |
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data >>= 8; |
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if (where & 2) |
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data >>= 16; |
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*val = data & 0xff; |
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return ret; |
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} |
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|
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static int read_config_word(struct pci_bus *bus, unsigned int devfn, |
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int where, u16 *val) |
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{ |
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u32 data; |
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int ret; |
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|
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
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if (where & 2) |
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data >>= 16; |
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*val = data & 0xffff; |
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return ret; |
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} |
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|
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static int read_config_dword(struct pci_bus *bus, unsigned int devfn, |
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int where, u32 *val) |
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{ |
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int ret; |
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|
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ret = config_access(PCI_ACCESS_READ, bus, devfn, where, val); |
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return ret; |
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} |
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|
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static int write_config_byte(struct pci_bus *bus, unsigned int devfn, |
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int where, u8 val) |
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{ |
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u32 data = 0; |
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|
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
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return -1; |
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|
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data = (data & ~(0xff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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|
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
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return -1; |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int write_config_word(struct pci_bus *bus, unsigned int devfn, |
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int where, u16 val) |
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{ |
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u32 data = 0; |
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|
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if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
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return -1; |
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|
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data = (data & ~(0xffff << ((where & 3) << 3))) | |
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(val << ((where & 3) << 3)); |
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|
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
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return -1; |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int write_config_dword(struct pci_bus *bus, unsigned int devfn, |
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int where, u32 val) |
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{ |
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if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val)) |
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return -1; |
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|
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return PCIBIOS_SUCCESSFUL; |
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} |
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|
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static int config_read(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 *val) |
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{ |
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switch (size) { |
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case 1: { |
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u8 _val; |
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int rc = read_config_byte(bus, devfn, where, &_val); |
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|
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*val = _val; |
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return rc; |
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} |
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case 2: { |
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u16 _val; |
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int rc = read_config_word(bus, devfn, where, &_val); |
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|
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*val = _val; |
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return rc; |
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} |
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default: |
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return read_config_dword(bus, devfn, where, val); |
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} |
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} |
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|
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static int config_write(struct pci_bus *bus, unsigned int devfn, |
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int where, int size, u32 val) |
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{ |
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switch (size) { |
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case 1: |
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return write_config_byte(bus, devfn, where, (u8) val); |
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case 2: |
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return write_config_word(bus, devfn, where, (u16) val); |
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default: |
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return write_config_dword(bus, devfn, where, val); |
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} |
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} |
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|
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struct pci_ops au1x_pci_ops = { |
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config_read, |
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config_write |
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}; |
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@ -0,0 +1,516 @@ |
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/*
|
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* Alchemy PCI host mode support. |
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* |
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* Copyright 2001-2003, 2007-2008 MontaVista Software Inc. |
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* Author: MontaVista Software, Inc. <source@mvista.com> |
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* |
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* Support for all devices (greater than 16) added by David Gathright. |
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*/ |
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|
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#include <linux/types.h> |
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#include <linux/pci.h> |
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#include <linux/platform_device.h> |
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#include <linux/kernel.h> |
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#include <linux/init.h> |
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#include <linux/vmalloc.h> |
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|
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#include <asm/mach-au1x00/au1000.h> |
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|
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#ifdef CONFIG_DEBUG_PCI |
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#define DBG(x...) printk(KERN_DEBUG x) |
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#else |
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#define DBG(x...) do {} while (0) |
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#endif |
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|
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#define PCI_ACCESS_READ 0 |
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#define PCI_ACCESS_WRITE 1 |
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|
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struct alchemy_pci_context { |
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struct pci_controller alchemy_pci_ctrl; /* leave as first member! */ |
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void __iomem *regs; /* ctrl base */ |
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/* tools for wired entry for config space access */ |
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unsigned long last_elo0; |
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unsigned long last_elo1; |
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int wired_entry; |
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struct vm_struct *pci_cfg_vm; |
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|
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unsigned long pm[12]; |
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|
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int (*board_map_irq)(const struct pci_dev *d, u8 slot, u8 pin); |
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int (*board_pci_idsel)(unsigned int devsel, int assert); |
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}; |
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|
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/* IO/MEM resources for PCI. Keep the memres in sync with __fixup_bigphys_addr
|
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* in arch/mips/alchemy/common/setup.c |
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*/ |
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static struct resource alchemy_pci_def_memres = { |
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.start = ALCHEMY_PCI_MEMWIN_START, |
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.end = ALCHEMY_PCI_MEMWIN_END, |
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.name = "PCI memory space", |
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.flags = IORESOURCE_MEM |
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}; |
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|
||||
static struct resource alchemy_pci_def_iores = { |
||||
.start = ALCHEMY_PCI_IOWIN_START, |
||||
.end = ALCHEMY_PCI_IOWIN_END, |
||||
.name = "PCI IO space", |
||||
.flags = IORESOURCE_IO |
||||
}; |
||||
|
||||
static void mod_wired_entry(int entry, unsigned long entrylo0, |
||||
unsigned long entrylo1, unsigned long entryhi, |
||||
unsigned long pagemask) |
||||
{ |
||||
unsigned long old_pagemask; |
||||
unsigned long old_ctx; |
||||
|
||||
/* Save old context and create impossible VPN2 value */ |
||||
old_ctx = read_c0_entryhi() & 0xff; |
||||
old_pagemask = read_c0_pagemask(); |
||||
write_c0_index(entry); |
||||
write_c0_pagemask(pagemask); |
||||
write_c0_entryhi(entryhi); |
||||
write_c0_entrylo0(entrylo0); |
||||
write_c0_entrylo1(entrylo1); |
||||
tlb_write_indexed(); |
||||
write_c0_entryhi(old_ctx); |
||||
write_c0_pagemask(old_pagemask); |
||||
} |
||||
|
||||
static void alchemy_pci_wired_entry(struct alchemy_pci_context *ctx) |
||||
{ |
||||
ctx->wired_entry = read_c0_wired(); |
||||
add_wired_entry(0, 0, (unsigned long)ctx->pci_cfg_vm->addr, PM_4K); |
||||
ctx->last_elo0 = ctx->last_elo1 = ~0; |
||||
} |
||||
|
||||
static int config_access(unsigned char access_type, struct pci_bus *bus, |
||||
unsigned int dev_fn, unsigned char where, u32 *data) |
||||
{ |
||||
struct alchemy_pci_context *ctx = bus->sysdata; |
||||
unsigned int device = PCI_SLOT(dev_fn); |
||||
unsigned int function = PCI_FUNC(dev_fn); |
||||
unsigned long offset, status, cfg_base, flags, entryLo0, entryLo1, r; |
||||
int error = PCIBIOS_SUCCESSFUL; |
||||
|
||||
if (device > 19) { |
||||
*data = 0xffffffff; |
||||
return -1; |
||||
} |
||||
|
||||
/* YAMON on all db1xxx boards wipes the TLB and writes zero to C0_wired
|
||||
* on resume, clearing our wired entry. Unfortunately the ->resume() |
||||
* callback is called way way way too late (and ->suspend() too early) |
||||
* to have them destroy and recreate it. Instead just test if c0_wired |
||||
* is now lower than the index we retrieved before suspending and then |
||||
* recreate the entry if necessary. Of course this is totally bonkers |
||||
* and breaks as soon as someone else adds another wired entry somewhere |
||||
* else. Anyone have any ideas how to handle this better? |
||||
*/ |
||||
if (unlikely(read_c0_wired() < ctx->wired_entry)) |
||||
alchemy_pci_wired_entry(ctx); |
||||
|
||||
local_irq_save(flags); |
||||
r = __raw_readl(ctx->regs + PCI_REG_STATCMD) & 0x0000ffff; |
||||
r |= PCI_STATCMD_STATUS(0x2000); |
||||
__raw_writel(r, ctx->regs + PCI_REG_STATCMD); |
||||
wmb(); |
||||
|
||||
/* Allow board vendors to implement their own off-chip IDSEL.
|
||||
* If it doesn't succeed, may as well bail out at this point. |
||||
*/ |
||||
if (ctx->board_pci_idsel(device, 1) == 0) { |
||||
*data = 0xffffffff; |
||||
local_irq_restore(flags); |
||||
return -1; |
||||
} |
||||
|
||||
/* Setup the config window */ |
||||
if (bus->number == 0) |
||||
cfg_base = (1 << device) << 11; |
||||
else |
||||
cfg_base = 0x80000000 | (bus->number << 16) | (device << 11); |
||||
|
||||
/* Setup the lower bits of the 36-bit address */ |
||||
offset = (function << 8) | (where & ~0x3); |
||||
/* Pick up any address that falls below the page mask */ |
||||
offset |= cfg_base & ~PAGE_MASK; |
||||
|
||||
/* Page boundary */ |
||||
cfg_base = cfg_base & PAGE_MASK; |
||||
|
||||
/* To improve performance, if the current device is the same as
|
||||
* the last device accessed, we don't touch the TLB. |
||||
*/ |
||||
entryLo0 = (6 << 26) | (cfg_base >> 6) | (2 << 3) | 7; |
||||
entryLo1 = (6 << 26) | (cfg_base >> 6) | (0x1000 >> 6) | (2 << 3) | 7; |
||||
if ((entryLo0 != ctx->last_elo0) || (entryLo1 != ctx->last_elo1)) { |
||||
mod_wired_entry(ctx->wired_entry, entryLo0, entryLo1, |
||||
(unsigned long)ctx->pci_cfg_vm->addr, PM_4K); |
||||
ctx->last_elo0 = entryLo0; |
||||
ctx->last_elo1 = entryLo1; |
||||
} |
||||
|
||||
if (access_type == PCI_ACCESS_WRITE) |
||||
__raw_writel(*data, ctx->pci_cfg_vm->addr + offset); |
||||
else |
||||
*data = __raw_readl(ctx->pci_cfg_vm->addr + offset); |
||||
wmb(); |
||||
|
||||
DBG("alchemy-pci: cfg access %d bus %u dev %u at %x dat %x conf %lx\n", |
||||
access_type, bus->number, device, where, *data, offset); |
||||
|
||||
/* check for errors, master abort */ |
||||
status = __raw_readl(ctx->regs + PCI_REG_STATCMD); |
||||
if (status & (1 << 29)) { |
||||
*data = 0xffffffff; |
||||
error = -1; |
||||
DBG("alchemy-pci: master abort on cfg access %d bus %d dev %d", |
||||
access_type, bus->number, device); |
||||
} else if ((status >> 28) & 0xf) { |
||||
DBG("alchemy-pci: PCI ERR detected: dev %d, status %lx\n", |
||||
device, (status >> 28) & 0xf); |
||||
|
||||
/* clear errors */ |
||||
__raw_writel(status & 0xf000ffff, ctx->regs + PCI_REG_STATCMD); |
||||
|
||||
*data = 0xffffffff; |
||||
error = -1; |
||||
} |
||||
|
||||
/* Take away the IDSEL. */ |
||||
(void)ctx->board_pci_idsel(device, 0); |
||||
|
||||
local_irq_restore(flags); |
||||
return error; |
||||
} |
||||
|
||||
static int read_config_byte(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u8 *val) |
||||
{ |
||||
u32 data; |
||||
int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
||||
|
||||
if (where & 1) |
||||
data >>= 8; |
||||
if (where & 2) |
||||
data >>= 16; |
||||
*val = data & 0xff; |
||||
return ret; |
||||
} |
||||
|
||||
static int read_config_word(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u16 *val) |
||||
{ |
||||
u32 data; |
||||
int ret = config_access(PCI_ACCESS_READ, bus, devfn, where, &data); |
||||
|
||||
if (where & 2) |
||||
data >>= 16; |
||||
*val = data & 0xffff; |
||||
return ret; |
||||
} |
||||
|
||||
static int read_config_dword(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u32 *val) |
||||
{ |
||||
return config_access(PCI_ACCESS_READ, bus, devfn, where, val); |
||||
} |
||||
|
||||
static int write_config_byte(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u8 val) |
||||
{ |
||||
u32 data = 0; |
||||
|
||||
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
||||
return -1; |
||||
|
||||
data = (data & ~(0xff << ((where & 3) << 3))) | |
||||
(val << ((where & 3) << 3)); |
||||
|
||||
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
||||
return -1; |
||||
|
||||
return PCIBIOS_SUCCESSFUL; |
||||
} |
||||
|
||||
static int write_config_word(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u16 val) |
||||
{ |
||||
u32 data = 0; |
||||
|
||||
if (config_access(PCI_ACCESS_READ, bus, devfn, where, &data)) |
||||
return -1; |
||||
|
||||
data = (data & ~(0xffff << ((where & 3) << 3))) | |
||||
(val << ((where & 3) << 3)); |
||||
|
||||
if (config_access(PCI_ACCESS_WRITE, bus, devfn, where, &data)) |
||||
return -1; |
||||
|
||||
return PCIBIOS_SUCCESSFUL; |
||||
} |
||||
|
||||
static int write_config_dword(struct pci_bus *bus, unsigned int devfn, |
||||
int where, u32 val) |
||||
{ |
||||
return config_access(PCI_ACCESS_WRITE, bus, devfn, where, &val); |
||||
} |
||||
|
||||
static int alchemy_pci_read(struct pci_bus *bus, unsigned int devfn, |
||||
int where, int size, u32 *val) |
||||
{ |
||||
switch (size) { |
||||
case 1: { |
||||
u8 _val; |
||||
int rc = read_config_byte(bus, devfn, where, &_val); |
||||
|
||||
*val = _val; |
||||
return rc; |
||||
} |
||||
case 2: { |
||||
u16 _val; |
||||
int rc = read_config_word(bus, devfn, where, &_val); |
||||
|
||||
*val = _val; |
||||
return rc; |
||||
} |
||||
default: |
||||
return read_config_dword(bus, devfn, where, val); |
||||
} |
||||
} |
||||
|
||||
static int alchemy_pci_write(struct pci_bus *bus, unsigned int devfn, |
||||
int where, int size, u32 val) |
||||
{ |
||||
switch (size) { |
||||
case 1: |
||||
return write_config_byte(bus, devfn, where, (u8) val); |
||||
case 2: |
||||
return write_config_word(bus, devfn, where, (u16) val); |
||||
default: |
||||
return write_config_dword(bus, devfn, where, val); |
||||
} |
||||
} |
||||
|
||||
static struct pci_ops alchemy_pci_ops = { |
||||
.read = alchemy_pci_read, |
||||
.write = alchemy_pci_write, |
||||
}; |
||||
|
||||
static int alchemy_pci_def_idsel(unsigned int devsel, int assert) |
||||
{ |
||||
return 1; /* success */ |
||||
} |
||||
|
||||
static int __devinit alchemy_pci_probe(struct platform_device *pdev) |
||||
{ |
||||
struct alchemy_pci_platdata *pd = pdev->dev.platform_data; |
||||
struct alchemy_pci_context *ctx; |
||||
void __iomem *virt_io; |
||||
unsigned long val; |
||||
struct resource *r; |
||||
int ret; |
||||
|
||||
/* need at least PCI IRQ mapping table */ |
||||
if (!pd) { |
||||
dev_err(&pdev->dev, "need platform data for PCI setup\n"); |
||||
ret = -ENODEV; |
||||
goto out; |
||||
} |
||||
|
||||
ctx = kzalloc(sizeof(*ctx), GFP_KERNEL); |
||||
if (!ctx) { |
||||
dev_err(&pdev->dev, "no memory for pcictl context\n"); |
||||
ret = -ENOMEM; |
||||
goto out; |
||||
} |
||||
|
||||
r = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
if (!r) { |
||||
dev_err(&pdev->dev, "no pcictl ctrl regs resource\n"); |
||||
ret = -ENODEV; |
||||
goto out1; |
||||
} |
||||
|
||||
if (!request_mem_region(r->start, resource_size(r), pdev->name)) { |
||||
dev_err(&pdev->dev, "cannot claim pci regs\n"); |
||||
ret = -ENODEV; |
||||
goto out1; |
||||
} |
||||
|
||||
ctx->regs = ioremap_nocache(r->start, resource_size(r)); |
||||
if (!ctx->regs) { |
||||
dev_err(&pdev->dev, "cannot map pci regs\n"); |
||||
ret = -ENODEV; |
||||
goto out2; |
||||
} |
||||
|
||||
/* map parts of the PCI IO area */ |
||||
/* REVISIT: if this changes with a newer variant (doubt it) make this
|
||||
* a platform resource. |
||||
*/ |
||||
virt_io = ioremap(AU1500_PCI_IO_PHYS_ADDR, 0x00100000); |
||||
if (!virt_io) { |
||||
dev_err(&pdev->dev, "cannot remap pci io space\n"); |
||||
ret = -ENODEV; |
||||
goto out3; |
||||
} |
||||
ctx->alchemy_pci_ctrl.io_map_base = (unsigned long)virt_io; |
||||
|
||||
#ifdef CONFIG_DMA_NONCOHERENT |
||||
/* Au1500 revisions older than AD have borked coherent PCI */ |
||||
if ((alchemy_get_cputype() == ALCHEMY_CPU_AU1500) && |
||||
(read_c0_prid() < 0x01030202)) { |
||||
val = __raw_readl(ctx->regs + PCI_REG_CONFIG); |
||||
val |= PCI_CONFIG_NC; |
||||
__raw_writel(val, ctx->regs + PCI_REG_CONFIG); |
||||
wmb(); |
||||
dev_info(&pdev->dev, "non-coherent PCI on Au1500 AA/AB/AC\n"); |
||||
} |
||||
#endif |
||||
|
||||
if (pd->board_map_irq) |
||||
ctx->board_map_irq = pd->board_map_irq; |
||||
|
||||
if (pd->board_pci_idsel) |
||||
ctx->board_pci_idsel = pd->board_pci_idsel; |
||||
else |
||||
ctx->board_pci_idsel = alchemy_pci_def_idsel; |
||||
|
||||
/* fill in relevant pci_controller members */ |
||||
ctx->alchemy_pci_ctrl.pci_ops = &alchemy_pci_ops; |
||||
ctx->alchemy_pci_ctrl.mem_resource = &alchemy_pci_def_memres; |
||||
ctx->alchemy_pci_ctrl.io_resource = &alchemy_pci_def_iores; |
||||
|
||||
/* we can't ioremap the entire pci config space because it's too large,
|
||||
* nor can we dynamically ioremap it because some drivers use the |
||||
* PCI config routines from within atomic contex and that becomes a |
||||
* problem in get_vm_area(). Instead we use one wired TLB entry to |
||||
* handle all config accesses for all busses. |
||||
*/ |
||||
ctx->pci_cfg_vm = get_vm_area(0x2000, VM_IOREMAP); |
||||
if (!ctx->pci_cfg_vm) { |
||||
dev_err(&pdev->dev, "unable to get vm area\n"); |
||||
ret = -ENOMEM; |
||||
goto out4; |
||||
} |
||||
ctx->wired_entry = 8192; /* impossibly high value */ |
||||
|
||||
set_io_port_base((unsigned long)ctx->alchemy_pci_ctrl.io_map_base); |
||||
|
||||
/* board may want to modify bits in the config register, do it now */ |
||||
val = __raw_readl(ctx->regs + PCI_REG_CONFIG); |
||||
val &= ~pd->pci_cfg_clr; |
||||
val |= pd->pci_cfg_set; |
||||
val &= ~PCI_CONFIG_PD; /* clear disable bit */ |
||||
__raw_writel(val, ctx->regs + PCI_REG_CONFIG); |
||||
wmb(); |
||||
|
||||
platform_set_drvdata(pdev, ctx); |
||||
register_pci_controller(&ctx->alchemy_pci_ctrl); |
||||
|
||||
return 0; |
||||
|
||||
out4: |
||||
iounmap(virt_io); |
||||
out3: |
||||
iounmap(ctx->regs); |
||||
out2: |
||||
release_mem_region(r->start, resource_size(r)); |
||||
out1: |
||||
kfree(ctx); |
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
|
||||
#ifdef CONFIG_PM |
||||
/* save PCI controller register contents. */ |
||||
static int alchemy_pci_suspend(struct device *dev) |
||||
{ |
||||
struct alchemy_pci_context *ctx = dev_get_drvdata(dev); |
||||
|
||||
ctx->pm[0] = __raw_readl(ctx->regs + PCI_REG_CMEM); |
||||
ctx->pm[1] = __raw_readl(ctx->regs + PCI_REG_CONFIG) & 0x0009ffff; |
||||
ctx->pm[2] = __raw_readl(ctx->regs + PCI_REG_B2BMASK_CCH); |
||||
ctx->pm[3] = __raw_readl(ctx->regs + PCI_REG_B2BBASE0_VID); |
||||
ctx->pm[4] = __raw_readl(ctx->regs + PCI_REG_B2BBASE1_SID); |
||||
ctx->pm[5] = __raw_readl(ctx->regs + PCI_REG_MWMASK_DEV); |
||||
ctx->pm[6] = __raw_readl(ctx->regs + PCI_REG_MWBASE_REV_CCL); |
||||
ctx->pm[7] = __raw_readl(ctx->regs + PCI_REG_ID); |
||||
ctx->pm[8] = __raw_readl(ctx->regs + PCI_REG_CLASSREV); |
||||
ctx->pm[9] = __raw_readl(ctx->regs + PCI_REG_PARAM); |
||||
ctx->pm[10] = __raw_readl(ctx->regs + PCI_REG_MBAR); |
||||
ctx->pm[11] = __raw_readl(ctx->regs + PCI_REG_TIMEOUT); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int alchemy_pci_resume(struct device *dev) |
||||
{ |
||||
struct alchemy_pci_context *ctx = dev_get_drvdata(dev); |
||||
|
||||
__raw_writel(ctx->pm[0], ctx->regs + PCI_REG_CMEM); |
||||
__raw_writel(ctx->pm[2], ctx->regs + PCI_REG_B2BMASK_CCH); |
||||
__raw_writel(ctx->pm[3], ctx->regs + PCI_REG_B2BBASE0_VID); |
||||
__raw_writel(ctx->pm[4], ctx->regs + PCI_REG_B2BBASE1_SID); |
||||
__raw_writel(ctx->pm[5], ctx->regs + PCI_REG_MWMASK_DEV); |
||||
__raw_writel(ctx->pm[6], ctx->regs + PCI_REG_MWBASE_REV_CCL); |
||||
__raw_writel(ctx->pm[7], ctx->regs + PCI_REG_ID); |
||||
__raw_writel(ctx->pm[8], ctx->regs + PCI_REG_CLASSREV); |
||||
__raw_writel(ctx->pm[9], ctx->regs + PCI_REG_PARAM); |
||||
__raw_writel(ctx->pm[10], ctx->regs + PCI_REG_MBAR); |
||||
__raw_writel(ctx->pm[11], ctx->regs + PCI_REG_TIMEOUT); |
||||
wmb(); |
||||
__raw_writel(ctx->pm[1], ctx->regs + PCI_REG_CONFIG); |
||||
wmb(); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct dev_pm_ops alchemy_pci_pmops = { |
||||
.suspend = alchemy_pci_suspend, |
||||
.resume = alchemy_pci_resume, |
||||
}; |
||||
|
||||
#define ALCHEMY_PCICTL_PM (&alchemy_pci_pmops) |
||||
|
||||
#else |
||||
#define ALCHEMY_PCICTL_PM NULL |
||||
#endif |
||||
|
||||
static struct platform_driver alchemy_pcictl_driver = { |
||||
.probe = alchemy_pci_probe, |
||||
.driver = { |
||||
.name = "alchemy-pci", |
||||
.owner = THIS_MODULE, |
||||
.pm = ALCHEMY_PCICTL_PM, |
||||
}, |
||||
}; |
||||
|
||||
static int __init alchemy_pci_init(void) |
||||
{ |
||||
/* Au1500/Au1550 have PCI */ |
||||
switch (alchemy_get_cputype()) { |
||||
case ALCHEMY_CPU_AU1500: |
||||
case ALCHEMY_CPU_AU1550: |
||||
return platform_driver_register(&alchemy_pcictl_driver); |
||||
} |
||||
return 0; |
||||
} |
||||
arch_initcall(alchemy_pci_init); |
||||
|
||||
|
||||
int __init pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) |
||||
{ |
||||
struct alchemy_pci_context *ctx = dev->sysdata; |
||||
if (ctx && ctx->board_map_irq) |
||||
return ctx->board_map_irq(dev, slot, pin); |
||||
return -1; |
||||
} |
||||
|
||||
int pcibios_plat_dev_init(struct pci_dev *dev) |
||||
{ |
||||
return 0; |
||||
} |
||||
Loading…
Reference in new issue