From 69dd9c2b616f828cfaac34657b4a2c2ff4c4b969 Mon Sep 17 00:00:00 2001 From: Raghavendra Ambadas Date: Fri, 17 Jul 2020 21:30:00 +0800 Subject: [PATCH] clk: qcom: mdss: Add check to read the gdsc status Add check for SDM660 target and 12NM pll interface to read the gdsc status bit. Change-Id: I8bdee9deb9b68844769c2ab66a87d79e8659b6fd Signed-off-by: Marco Zhang Signed-off-by: Nirmal Abraham --- drivers/clk/qcom/mdss/mdss-pll.h | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/drivers/clk/qcom/mdss/mdss-pll.h b/drivers/clk/qcom/mdss/mdss-pll.h index 4e3af2f03b8b..070c62ea69d7 100644 --- a/drivers/clk/qcom/mdss/mdss-pll.h +++ b/drivers/clk/qcom/mdss/mdss-pll.h @@ -219,8 +219,14 @@ static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) WARN(1, "gdsc_base register is not defined\n"); return true; } - ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && - (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; + if ((pll_res->target_id == MDSS_PLL_TARGET_SDM660) || + (pll_res->pll_interface_type == MDSS_DSI_PLL_12NM)) + ret = ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && + (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? + false : true; + else + ret = readl_relaxed(pll_res->gdsc_base) & BIT(31) ? + false : true; return ret; }