This adds dpm support for rv7xx asics. This includes: - clockgating - dynamic engine clock scaling - dynamic memory clock scaling - dynamic voltage scaling - dynamic pcie gen1/gen2 switching Set radeon.dpm=1 to enable. v2: reduce stack usage v3: fix 64 bit div v4: fix state enable Signed-off-by: Alex Deucher <alexander.deucher@amd.com>tirimbino
parent
4a6369e993
commit
66229b2005
@ -0,0 +1,78 @@ |
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/*
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* Copyright 2011 Advanced Micro Devices, Inc. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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* |
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*/ |
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#ifndef PP_SMC_H |
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#define PP_SMC_H |
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#pragma pack(push, 1) |
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#define PPSMC_SWSTATE_FLAG_DC 0x01 |
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#define PPSMC_THERMAL_PROTECT_TYPE_INTERNAL 0x00 |
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#define PPSMC_THERMAL_PROTECT_TYPE_EXTERNAL 0x01 |
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#define PPSMC_THERMAL_PROTECT_TYPE_NONE 0xff |
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|
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#define PPSMC_SYSTEMFLAG_GPIO_DC 0x01 |
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#define PPSMC_SYSTEMFLAG_STEPVDDC 0x02 |
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#define PPSMC_SYSTEMFLAG_GDDR5 0x04 |
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#define PPSMC_SYSTEMFLAG_DISABLE_BABYSTEP 0x08 |
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#define PPSMC_SYSTEMFLAG_REGULATOR_HOT 0x10 |
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_MASK 0x07 |
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#define PPSMC_EXTRAFLAGS_AC2DC_DONT_WAIT_FOR_VBLANK 0x08 |
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTODPMLOWSTATE 0x00 |
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#define PPSMC_EXTRAFLAGS_AC2DC_ACTION_GOTOINITIALSTATE 0x01 |
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#define PPSMC_DISPLAY_WATERMARK_LOW 0 |
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#define PPSMC_DISPLAY_WATERMARK_HIGH 1 |
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#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 |
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#define PPSMC_Result_OK ((uint8_t)0x01) |
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#define PPSMC_Result_Failed ((uint8_t)0xFF) |
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typedef uint8_t PPSMC_Result; |
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#define PPSMC_MSG_Halt ((uint8_t)0x10) |
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#define PPSMC_MSG_Resume ((uint8_t)0x11) |
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#define PPSMC_MSG_ZeroLevelsDisabled ((uint8_t)0x13) |
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#define PPSMC_MSG_OneLevelsDisabled ((uint8_t)0x14) |
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#define PPSMC_MSG_TwoLevelsDisabled ((uint8_t)0x15) |
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#define PPSMC_MSG_EnableThermalInterrupt ((uint8_t)0x16) |
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#define PPSMC_MSG_SwitchToSwState ((uint8_t)0x20) |
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#define PPSMC_MSG_SwitchToInitialState ((uint8_t)0x40) |
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#define PPSMC_MSG_NoForcedLevel ((uint8_t)0x41) |
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#define PPSMC_MSG_SwitchToMinimumPower ((uint8_t)0x51) |
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#define PPSMC_MSG_ResumeFromMinimumPower ((uint8_t)0x52) |
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#define PPSMC_MSG_NoDisplay ((uint8_t)0x5D) |
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#define PPSMC_MSG_HasDisplay ((uint8_t)0x5E) |
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#define PPSMC_MSG_EnableULV ((uint8_t)0x62) |
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#define PPSMC_MSG_DisableULV ((uint8_t)0x63) |
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#define PPSMC_MSG_EnterULV ((uint8_t)0x64) |
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#define PPSMC_MSG_ExitULV ((uint8_t)0x65) |
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#define PPSMC_MSG_ResetToDefaults ((uint8_t)0x84) |
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typedef uint8_t PPSMC_Msg; |
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#pragma pack(pop) |
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#endif |
@ -0,0 +1,508 @@ |
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/*
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* Copyright 2011 Advanced Micro Devices, Inc. |
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* |
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* Permission is hereby granted, free of charge, to any person obtaining a |
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* copy of this software and associated documentation files (the "Software"), |
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* to deal in the Software without restriction, including without limitation |
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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* and/or sell copies of the Software, and to permit persons to whom the |
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* Software is furnished to do so, subject to the following conditions: |
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* |
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* The above copyright notice and this permission notice shall be included in |
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* all copies or substantial portions of the Software. |
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* |
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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* OTHER DEALINGS IN THE SOFTWARE. |
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* |
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* Authors: Alex Deucher |
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*/ |
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#include "drmP.h" |
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#include "radeon.h" |
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#include "rv730d.h" |
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#include "r600_dpm.h" |
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#include "rv770_dpm.h" |
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#include "atom.h" |
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#define MC_CG_ARB_FREQ_F0 0x0a |
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#define MC_CG_ARB_FREQ_F1 0x0b |
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#define MC_CG_ARB_FREQ_F2 0x0c |
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#define MC_CG_ARB_FREQ_F3 0x0d |
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struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); |
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struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); |
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int rv730_populate_sclk_value(struct radeon_device *rdev, |
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u32 engine_clock, |
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RV770_SMC_SCLK_VALUE *sclk) |
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{ |
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struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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struct atom_clock_dividers dividers; |
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u32 spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; |
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u32 spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; |
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u32 spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; |
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u32 cg_spll_spread_spectrum = pi->clk_regs.rv730.cg_spll_spread_spectrum; |
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u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv730.cg_spll_spread_spectrum_2; |
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u64 tmp; |
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u32 reference_clock = rdev->clock.spll.reference_freq; |
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u32 reference_divider, post_divider; |
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u32 fbdiv; |
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int ret; |
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
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engine_clock, false, ÷rs); |
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if (ret) |
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return ret; |
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reference_divider = 1 + dividers.ref_div; |
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if (dividers.enable_post_div) |
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post_divider = ((dividers.post_div >> 4) & 0xf) + |
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(dividers.post_div & 0xf) + 2; |
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else |
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post_divider = 1; |
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tmp = (u64) engine_clock * reference_divider * post_divider * 16384; |
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do_div(tmp, reference_clock); |
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fbdiv = (u32) tmp; |
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/* set up registers */ |
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if (dividers.enable_post_div) |
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spll_func_cntl |= SPLL_DIVEN; |
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else |
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spll_func_cntl &= ~SPLL_DIVEN; |
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spll_func_cntl &= ~(SPLL_HILEN_MASK | SPLL_LOLEN_MASK | SPLL_REF_DIV_MASK); |
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spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); |
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spll_func_cntl |= SPLL_HILEN((dividers.post_div >> 4) & 0xf); |
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spll_func_cntl |= SPLL_LOLEN(dividers.post_div & 0xf); |
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spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
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spll_func_cntl_2 |= SCLK_MUX_SEL(2); |
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spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
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spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); |
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spll_func_cntl_3 |= SPLL_DITHEN; |
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if (pi->sclk_ss) { |
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struct radeon_atom_ss ss; |
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u32 vco_freq = engine_clock * post_divider; |
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if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
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ASIC_INTERNAL_ENGINE_SS, vco_freq)) { |
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u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
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u32 clk_v = ss.percentage * fbdiv / (clk_s * 10000); |
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cg_spll_spread_spectrum &= ~CLK_S_MASK; |
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cg_spll_spread_spectrum |= CLK_S(clk_s); |
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cg_spll_spread_spectrum |= SSEN; |
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cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; |
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cg_spll_spread_spectrum_2 |= CLK_V(clk_v); |
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} |
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} |
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sclk->sclk_value = cpu_to_be32(engine_clock); |
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sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
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sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
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sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
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sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); |
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sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); |
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return 0; |
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} |
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int rv730_populate_mclk_value(struct radeon_device *rdev, |
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u32 engine_clock, u32 memory_clock, |
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LPRV7XX_SMC_MCLK_VALUE mclk) |
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{ |
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struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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u32 mclk_pwrmgt_cntl = pi->clk_regs.rv730.mclk_pwrmgt_cntl; |
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u32 dll_cntl = pi->clk_regs.rv730.dll_cntl; |
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u32 mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; |
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u32 mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; |
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u32 mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; |
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u32 mpll_ss = pi->clk_regs.rv730.mpll_ss; |
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u32 mpll_ss2 = pi->clk_regs.rv730.mpll_ss2; |
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struct atom_clock_dividers dividers; |
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u32 post_divider, reference_divider; |
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int ret; |
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ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, |
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memory_clock, false, ÷rs); |
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if (ret) |
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return ret; |
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reference_divider = dividers.ref_div + 1; |
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if (dividers.enable_post_div) |
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post_divider = ((dividers.post_div >> 4) & 0xf) + |
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(dividers.post_div & 0xf) + 2; |
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else |
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post_divider = 1; |
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/* setup the registers */ |
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if (dividers.enable_post_div) |
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mpll_func_cntl |= MPLL_DIVEN; |
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else |
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mpll_func_cntl &= ~MPLL_DIVEN; |
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mpll_func_cntl &= ~(MPLL_REF_DIV_MASK | MPLL_HILEN_MASK | MPLL_LOLEN_MASK); |
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mpll_func_cntl |= MPLL_REF_DIV(dividers.ref_div); |
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mpll_func_cntl |= MPLL_HILEN((dividers.post_div >> 4) & 0xf); |
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mpll_func_cntl |= MPLL_LOLEN(dividers.post_div & 0xf); |
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mpll_func_cntl_3 &= ~MPLL_FB_DIV_MASK; |
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mpll_func_cntl_3 |= MPLL_FB_DIV(dividers.fb_div); |
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if (dividers.enable_dithen) |
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mpll_func_cntl_3 |= MPLL_DITHEN; |
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else |
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mpll_func_cntl_3 &= ~MPLL_DITHEN; |
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if (pi->mclk_ss) { |
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struct radeon_atom_ss ss; |
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u32 vco_freq = memory_clock * post_divider; |
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if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
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ASIC_INTERNAL_MEMORY_SS, vco_freq)) { |
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u32 reference_clock = rdev->clock.mpll.reference_freq; |
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u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
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u32 clk_v = ss.percentage * dividers.fb_div / (clk_s * 10000); |
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mpll_ss &= ~CLK_S_MASK; |
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mpll_ss |= CLK_S(clk_s); |
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mpll_ss |= SSEN; |
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mpll_ss2 &= ~CLK_V_MASK; |
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mpll_ss |= CLK_V(clk_v); |
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} |
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} |
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mclk->mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
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mclk->mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); |
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mclk->mclk730.mclk_value = cpu_to_be32(memory_clock); |
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mclk->mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); |
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mclk->mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); |
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mclk->mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); |
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mclk->mclk730.vMPLL_SS = cpu_to_be32(mpll_ss); |
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mclk->mclk730.vMPLL_SS2 = cpu_to_be32(mpll_ss2); |
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return 0; |
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} |
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void rv730_read_clock_registers(struct radeon_device *rdev) |
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{ |
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struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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pi->clk_regs.rv730.cg_spll_func_cntl = |
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RREG32(CG_SPLL_FUNC_CNTL); |
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pi->clk_regs.rv730.cg_spll_func_cntl_2 = |
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RREG32(CG_SPLL_FUNC_CNTL_2); |
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pi->clk_regs.rv730.cg_spll_func_cntl_3 = |
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RREG32(CG_SPLL_FUNC_CNTL_3); |
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pi->clk_regs.rv730.cg_spll_spread_spectrum = |
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RREG32(CG_SPLL_SPREAD_SPECTRUM); |
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pi->clk_regs.rv730.cg_spll_spread_spectrum_2 = |
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RREG32(CG_SPLL_SPREAD_SPECTRUM_2); |
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pi->clk_regs.rv730.mclk_pwrmgt_cntl = |
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RREG32(TCI_MCLK_PWRMGT_CNTL); |
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pi->clk_regs.rv730.dll_cntl = |
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RREG32(TCI_DLL_CNTL); |
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pi->clk_regs.rv730.mpll_func_cntl = |
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RREG32(CG_MPLL_FUNC_CNTL); |
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pi->clk_regs.rv730.mpll_func_cntl2 = |
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RREG32(CG_MPLL_FUNC_CNTL_2); |
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pi->clk_regs.rv730.mpll_func_cntl3 = |
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RREG32(CG_MPLL_FUNC_CNTL_3); |
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pi->clk_regs.rv730.mpll_ss = |
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RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM); |
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pi->clk_regs.rv730.mpll_ss2 = |
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RREG32(CG_TCI_MPLL_SPREAD_SPECTRUM_2); |
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} |
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int rv730_populate_smc_acpi_state(struct radeon_device *rdev, |
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RV770_SMC_STATETABLE *table) |
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{ |
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struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
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u32 mpll_func_cntl = 0; |
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u32 mpll_func_cntl_2 = 0 ; |
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u32 mpll_func_cntl_3 = 0; |
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u32 mclk_pwrmgt_cntl; |
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u32 dll_cntl; |
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u32 spll_func_cntl; |
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u32 spll_func_cntl_2; |
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u32 spll_func_cntl_3; |
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table->ACPIState = table->initialState; |
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table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; |
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if (pi->acpi_vddc) { |
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rv770_populate_vddc_value(rdev, pi->acpi_vddc, |
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&table->ACPIState.levels[0].vddc); |
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table->ACPIState.levels[0].gen2PCIE = pi->pcie_gen2 ? |
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pi->acpi_pcie_gen2 : 0; |
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table->ACPIState.levels[0].gen2XSP = |
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pi->acpi_pcie_gen2; |
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} else { |
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rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, |
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&table->ACPIState.levels[0].vddc); |
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table->ACPIState.levels[0].gen2PCIE = 0; |
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} |
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mpll_func_cntl = pi->clk_regs.rv730.mpll_func_cntl; |
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mpll_func_cntl_2 = pi->clk_regs.rv730.mpll_func_cntl2; |
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mpll_func_cntl_3 = pi->clk_regs.rv730.mpll_func_cntl3; |
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mpll_func_cntl |= MPLL_RESET | MPLL_BYPASS_EN; |
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mpll_func_cntl &= ~MPLL_SLEEP; |
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mpll_func_cntl_2 &= ~MCLK_MUX_SEL_MASK; |
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mpll_func_cntl_2 |= MCLK_MUX_SEL(1); |
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mclk_pwrmgt_cntl = (MRDCKA_RESET | |
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MRDCKB_RESET | |
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MRDCKC_RESET | |
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MRDCKD_RESET | |
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MRDCKE_RESET | |
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MRDCKF_RESET | |
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MRDCKG_RESET | |
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MRDCKH_RESET | |
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MRDCKA_SLEEP | |
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MRDCKB_SLEEP | |
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MRDCKC_SLEEP | |
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MRDCKD_SLEEP | |
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MRDCKE_SLEEP | |
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MRDCKF_SLEEP | |
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MRDCKG_SLEEP | |
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MRDCKH_SLEEP); |
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dll_cntl = 0xff000000; |
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spll_func_cntl = pi->clk_regs.rv730.cg_spll_func_cntl; |
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spll_func_cntl_2 = pi->clk_regs.rv730.cg_spll_func_cntl_2; |
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spll_func_cntl_3 = pi->clk_regs.rv730.cg_spll_func_cntl_3; |
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spll_func_cntl |= SPLL_RESET | SPLL_BYPASS_EN; |
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spll_func_cntl &= ~SPLL_SLEEP; |
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spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
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spll_func_cntl_2 |= SCLK_MUX_SEL(4); |
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = cpu_to_be32(mpll_func_cntl); |
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = cpu_to_be32(mpll_func_cntl_2); |
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table->ACPIState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = cpu_to_be32(mpll_func_cntl_3); |
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table->ACPIState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
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table->ACPIState.levels[0].mclk.mclk730.vDLL_CNTL = cpu_to_be32(dll_cntl); |
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table->ACPIState.levels[0].mclk.mclk730.mclk_value = 0; |
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
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table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
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table->ACPIState.levels[0].sclk.sclk_value = 0; |
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|
||||
rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); |
||||
|
||||
table->ACPIState.levels[1] = table->ACPIState.levels[0]; |
||||
table->ACPIState.levels[2] = table->ACPIState.levels[0]; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rv730_populate_smc_initial_state(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_state, |
||||
RV770_SMC_STATETABLE *table) |
||||
{ |
||||
struct rv7xx_ps *initial_state = rv770_get_ps(radeon_state); |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
u32 a_t; |
||||
|
||||
table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL = |
||||
cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl); |
||||
table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL2 = |
||||
cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl2); |
||||
table->initialState.levels[0].mclk.mclk730.vMPLL_FUNC_CNTL3 = |
||||
cpu_to_be32(pi->clk_regs.rv730.mpll_func_cntl3); |
||||
table->initialState.levels[0].mclk.mclk730.vMCLK_PWRMGT_CNTL = |
||||
cpu_to_be32(pi->clk_regs.rv730.mclk_pwrmgt_cntl); |
||||
table->initialState.levels[0].mclk.mclk730.vDLL_CNTL = |
||||
cpu_to_be32(pi->clk_regs.rv730.dll_cntl); |
||||
table->initialState.levels[0].mclk.mclk730.vMPLL_SS = |
||||
cpu_to_be32(pi->clk_regs.rv730.mpll_ss); |
||||
table->initialState.levels[0].mclk.mclk730.vMPLL_SS2 = |
||||
cpu_to_be32(pi->clk_regs.rv730.mpll_ss2); |
||||
|
||||
table->initialState.levels[0].mclk.mclk730.mclk_value = |
||||
cpu_to_be32(initial_state->low.mclk); |
||||
|
||||
table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = |
||||
cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl); |
||||
table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = |
||||
cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_2); |
||||
table->initialState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = |
||||
cpu_to_be32(pi->clk_regs.rv730.cg_spll_func_cntl_3); |
||||
table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM = |
||||
cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum); |
||||
table->initialState.levels[0].sclk.vCG_SPLL_SPREAD_SPECTRUM_2 = |
||||
cpu_to_be32(pi->clk_regs.rv730.cg_spll_spread_spectrum_2); |
||||
|
||||
table->initialState.levels[0].sclk.sclk_value = |
||||
cpu_to_be32(initial_state->low.sclk); |
||||
|
||||
table->initialState.levels[0].arbValue = MC_CG_ARB_FREQ_F0; |
||||
|
||||
table->initialState.levels[0].seqValue = |
||||
rv770_get_seq_value(rdev, &initial_state->low); |
||||
|
||||
rv770_populate_vddc_value(rdev, |
||||
initial_state->low.vddc, |
||||
&table->initialState.levels[0].vddc); |
||||
rv770_populate_initial_mvdd_value(rdev, |
||||
&table->initialState.levels[0].mvdd); |
||||
|
||||
a_t = CG_R(0xffff) | CG_L(0); |
||||
|
||||
table->initialState.levels[0].aT = cpu_to_be32(a_t); |
||||
|
||||
table->initialState.levels[0].bSP = cpu_to_be32(pi->dsp); |
||||
|
||||
if (pi->boot_in_gen2) |
||||
table->initialState.levels[0].gen2PCIE = 1; |
||||
else |
||||
table->initialState.levels[0].gen2PCIE = 0; |
||||
if (initial_state->low.flags & ATOM_PPLIB_R600_FLAGS_PCIEGEN2) |
||||
table->initialState.levels[0].gen2XSP = 1; |
||||
else |
||||
table->initialState.levels[0].gen2XSP = 0; |
||||
|
||||
table->initialState.levels[1] = table->initialState.levels[0]; |
||||
table->initialState.levels[2] = table->initialState.levels[0]; |
||||
|
||||
table->initialState.flags |= PPSMC_SWSTATE_FLAG_DC; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rv730_program_memory_timing_parameters(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_state) |
||||
{ |
||||
struct rv7xx_ps *state = rv770_get_ps(radeon_state); |
||||
u32 arb_refresh_rate = 0; |
||||
u32 dram_timing = 0; |
||||
u32 dram_timing2 = 0; |
||||
u32 old_dram_timing = 0; |
||||
u32 old_dram_timing2 = 0; |
||||
|
||||
arb_refresh_rate = RREG32(MC_ARB_RFSH_RATE) & |
||||
~(POWERMODE1_MASK | POWERMODE2_MASK | POWERMODE3_MASK); |
||||
arb_refresh_rate |= |
||||
(POWERMODE1(rv770_calculate_memory_refresh_rate(rdev, state->low.sclk)) | |
||||
POWERMODE2(rv770_calculate_memory_refresh_rate(rdev, state->medium.sclk)) | |
||||
POWERMODE3(rv770_calculate_memory_refresh_rate(rdev, state->high.sclk))); |
||||
WREG32(MC_ARB_RFSH_RATE, arb_refresh_rate); |
||||
|
||||
/* save the boot dram timings */ |
||||
old_dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||||
old_dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||||
|
||||
radeon_atom_set_engine_dram_timings(rdev, |
||||
state->high.sclk, |
||||
state->high.mclk); |
||||
|
||||
dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||||
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||||
|
||||
WREG32(MC_ARB_DRAM_TIMING_3, dram_timing); |
||||
WREG32(MC_ARB_DRAM_TIMING2_3, dram_timing2); |
||||
|
||||
radeon_atom_set_engine_dram_timings(rdev, |
||||
state->medium.sclk, |
||||
state->medium.mclk); |
||||
|
||||
dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||||
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||||
|
||||
WREG32(MC_ARB_DRAM_TIMING_2, dram_timing); |
||||
WREG32(MC_ARB_DRAM_TIMING2_2, dram_timing2); |
||||
|
||||
radeon_atom_set_engine_dram_timings(rdev, |
||||
state->low.sclk, |
||||
state->low.mclk); |
||||
|
||||
dram_timing = RREG32(MC_ARB_DRAM_TIMING); |
||||
dram_timing2 = RREG32(MC_ARB_DRAM_TIMING2); |
||||
|
||||
WREG32(MC_ARB_DRAM_TIMING_1, dram_timing); |
||||
WREG32(MC_ARB_DRAM_TIMING2_1, dram_timing2); |
||||
|
||||
/* restore the boot dram timings */ |
||||
WREG32(MC_ARB_DRAM_TIMING, old_dram_timing); |
||||
WREG32(MC_ARB_DRAM_TIMING2, old_dram_timing2); |
||||
|
||||
} |
||||
|
||||
void rv730_start_dpm(struct radeon_device *rdev) |
||||
{ |
||||
WREG32_P(SCLK_PWRMGT_CNTL, 0, ~SCLK_PWRMGT_OFF); |
||||
|
||||
WREG32_P(TCI_MCLK_PWRMGT_CNTL, 0, ~MPLL_PWRMGT_OFF); |
||||
|
||||
WREG32_P(GENERAL_PWRMGT, GLOBAL_PWRMGT_EN, ~GLOBAL_PWRMGT_EN); |
||||
} |
||||
|
||||
void rv730_stop_dpm(struct radeon_device *rdev) |
||||
{ |
||||
PPSMC_Result result; |
||||
|
||||
result = rv770_send_msg_to_smc(rdev, PPSMC_MSG_TwoLevelsDisabled); |
||||
|
||||
if (result != PPSMC_Result_OK) |
||||
DRM_ERROR("Could not force DPM to low\n"); |
||||
|
||||
WREG32_P(GENERAL_PWRMGT, 0, ~GLOBAL_PWRMGT_EN); |
||||
|
||||
WREG32_P(SCLK_PWRMGT_CNTL, SCLK_PWRMGT_OFF, ~SCLK_PWRMGT_OFF); |
||||
|
||||
WREG32_P(TCI_MCLK_PWRMGT_CNTL, MPLL_PWRMGT_OFF, ~MPLL_PWRMGT_OFF); |
||||
} |
||||
|
||||
void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
u32 i = use_dcodt ? 0 : 1; |
||||
u32 mc4_io_pad_cntl; |
||||
|
||||
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); |
||||
mc4_io_pad_cntl &= 0xFFFFFF00; |
||||
mc4_io_pad_cntl |= pi->odt_value_0[i]; |
||||
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I0, mc4_io_pad_cntl); |
||||
WREG32(MC4_IO_DQ_PAD_CNTL_D0_I1, mc4_io_pad_cntl); |
||||
|
||||
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); |
||||
mc4_io_pad_cntl &= 0xFFFFFF00; |
||||
mc4_io_pad_cntl |= pi->odt_value_1[i]; |
||||
WREG32(MC4_IO_QS_PAD_CNTL_D0_I0, mc4_io_pad_cntl); |
||||
WREG32(MC4_IO_QS_PAD_CNTL_D0_I1, mc4_io_pad_cntl); |
||||
} |
||||
|
||||
void rv730_get_odt_values(struct radeon_device *rdev) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
u32 mc4_io_pad_cntl; |
||||
|
||||
pi->odt_value_0[0] = (u8)0; |
||||
pi->odt_value_1[0] = (u8)0x80; |
||||
|
||||
mc4_io_pad_cntl = RREG32(MC4_IO_DQ_PAD_CNTL_D0_I0); |
||||
pi->odt_value_0[1] = (u8)(mc4_io_pad_cntl & 0xff); |
||||
|
||||
mc4_io_pad_cntl = RREG32(MC4_IO_QS_PAD_CNTL_D0_I0); |
||||
pi->odt_value_1[1] = (u8)(mc4_io_pad_cntl & 0xff); |
||||
} |
@ -0,0 +1,165 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
*/ |
||||
#ifndef RV730_H |
||||
#define RV730_H |
||||
|
||||
#define CG_SPLL_FUNC_CNTL 0x600 |
||||
#define SPLL_RESET (1 << 0) |
||||
#define SPLL_SLEEP (1 << 1) |
||||
#define SPLL_DIVEN (1 << 2) |
||||
#define SPLL_BYPASS_EN (1 << 3) |
||||
#define SPLL_REF_DIV(x) ((x) << 4) |
||||
#define SPLL_REF_DIV_MASK (0x3f << 4) |
||||
#define SPLL_HILEN(x) ((x) << 12) |
||||
#define SPLL_HILEN_MASK (0xf << 12) |
||||
#define SPLL_LOLEN(x) ((x) << 16) |
||||
#define SPLL_LOLEN_MASK (0xf << 16) |
||||
#define CG_SPLL_FUNC_CNTL_2 0x604 |
||||
#define SCLK_MUX_SEL(x) ((x) << 0) |
||||
#define SCLK_MUX_SEL_MASK (0x1ff << 0) |
||||
#define CG_SPLL_FUNC_CNTL_3 0x608 |
||||
#define SPLL_FB_DIV(x) ((x) << 0) |
||||
#define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
||||
#define SPLL_DITHEN (1 << 28) |
||||
|
||||
#define CG_MPLL_FUNC_CNTL 0x624 |
||||
#define MPLL_RESET (1 << 0) |
||||
#define MPLL_SLEEP (1 << 1) |
||||
#define MPLL_DIVEN (1 << 2) |
||||
#define MPLL_BYPASS_EN (1 << 3) |
||||
#define MPLL_REF_DIV(x) ((x) << 4) |
||||
#define MPLL_REF_DIV_MASK (0x3f << 4) |
||||
#define MPLL_HILEN(x) ((x) << 12) |
||||
#define MPLL_HILEN_MASK (0xf << 12) |
||||
#define MPLL_LOLEN(x) ((x) << 16) |
||||
#define MPLL_LOLEN_MASK (0xf << 16) |
||||
#define CG_MPLL_FUNC_CNTL_2 0x628 |
||||
#define MCLK_MUX_SEL(x) ((x) << 0) |
||||
#define MCLK_MUX_SEL_MASK (0x1ff << 0) |
||||
#define CG_MPLL_FUNC_CNTL_3 0x62c |
||||
#define MPLL_FB_DIV(x) ((x) << 0) |
||||
#define MPLL_FB_DIV_MASK (0x3ffffff << 0) |
||||
#define MPLL_DITHEN (1 << 28) |
||||
|
||||
#define CG_TCI_MPLL_SPREAD_SPECTRUM 0x634 |
||||
#define CG_TCI_MPLL_SPREAD_SPECTRUM_2 0x638 |
||||
#define GENERAL_PWRMGT 0x63c |
||||
# define GLOBAL_PWRMGT_EN (1 << 0) |
||||
# define STATIC_PM_EN (1 << 1) |
||||
# define THERMAL_PROTECTION_DIS (1 << 2) |
||||
# define THERMAL_PROTECTION_TYPE (1 << 3) |
||||
# define ENABLE_GEN2PCIE (1 << 4) |
||||
# define ENABLE_GEN2XSP (1 << 5) |
||||
# define SW_SMIO_INDEX(x) ((x) << 6) |
||||
# define SW_SMIO_INDEX_MASK (3 << 6) |
||||
# define LOW_VOLT_D2_ACPI (1 << 8) |
||||
# define LOW_VOLT_D3_ACPI (1 << 9) |
||||
# define VOLT_PWRMGT_EN (1 << 10) |
||||
# define BACKBIAS_PAD_EN (1 << 18) |
||||
# define BACKBIAS_VALUE (1 << 19) |
||||
# define DYN_SPREAD_SPECTRUM_EN (1 << 23) |
||||
# define AC_DC_SW (1 << 24) |
||||
|
||||
#define SCLK_PWRMGT_CNTL 0x644 |
||||
# define SCLK_PWRMGT_OFF (1 << 0) |
||||
# define SCLK_LOW_D1 (1 << 1) |
||||
# define FIR_RESET (1 << 4) |
||||
# define FIR_FORCE_TREND_SEL (1 << 5) |
||||
# define FIR_TREND_MODE (1 << 6) |
||||
# define DYN_GFX_CLK_OFF_EN (1 << 7) |
||||
# define GFX_CLK_FORCE_ON (1 << 8) |
||||
# define GFX_CLK_REQUEST_OFF (1 << 9) |
||||
# define GFX_CLK_FORCE_OFF (1 << 10) |
||||
# define GFX_CLK_OFF_ACPI_D1 (1 << 11) |
||||
# define GFX_CLK_OFF_ACPI_D2 (1 << 12) |
||||
# define GFX_CLK_OFF_ACPI_D3 (1 << 13) |
||||
|
||||
#define TCI_MCLK_PWRMGT_CNTL 0x648 |
||||
# define MPLL_PWRMGT_OFF (1 << 5) |
||||
# define DLL_READY (1 << 6) |
||||
# define MC_INT_CNTL (1 << 7) |
||||
# define MRDCKA_SLEEP (1 << 8) |
||||
# define MRDCKB_SLEEP (1 << 9) |
||||
# define MRDCKC_SLEEP (1 << 10) |
||||
# define MRDCKD_SLEEP (1 << 11) |
||||
# define MRDCKE_SLEEP (1 << 12) |
||||
# define MRDCKF_SLEEP (1 << 13) |
||||
# define MRDCKG_SLEEP (1 << 14) |
||||
# define MRDCKH_SLEEP (1 << 15) |
||||
# define MRDCKA_RESET (1 << 16) |
||||
# define MRDCKB_RESET (1 << 17) |
||||
# define MRDCKC_RESET (1 << 18) |
||||
# define MRDCKD_RESET (1 << 19) |
||||
# define MRDCKE_RESET (1 << 20) |
||||
# define MRDCKF_RESET (1 << 21) |
||||
# define MRDCKG_RESET (1 << 22) |
||||
# define MRDCKH_RESET (1 << 23) |
||||
# define DLL_READY_READ (1 << 24) |
||||
# define USE_DISPLAY_GAP (1 << 25) |
||||
# define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
||||
# define MPLL_TURNOFF_D2 (1 << 28) |
||||
#define TCI_DLL_CNTL 0x64c |
||||
|
||||
#define CG_PG_CNTL 0x858 |
||||
# define PWRGATE_ENABLE (1 << 0) |
||||
|
||||
#define CG_AT 0x6d4 |
||||
#define CG_R(x) ((x) << 0) |
||||
#define CG_R_MASK (0xffff << 0) |
||||
#define CG_L(x) ((x) << 16) |
||||
#define CG_L_MASK (0xffff << 16) |
||||
|
||||
#define CG_SPLL_SPREAD_SPECTRUM 0x790 |
||||
#define SSEN (1 << 0) |
||||
#define CLK_S(x) ((x) << 4) |
||||
#define CLK_S_MASK (0xfff << 4) |
||||
#define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
||||
#define CLK_V(x) ((x) << 0) |
||||
#define CLK_V_MASK (0x3ffffff << 0) |
||||
|
||||
#define MC_ARB_DRAM_TIMING 0x2774 |
||||
#define MC_ARB_DRAM_TIMING2 0x2778 |
||||
|
||||
#define MC_ARB_RFSH_RATE 0x27b0 |
||||
#define POWERMODE0(x) ((x) << 0) |
||||
#define POWERMODE0_MASK (0xff << 0) |
||||
#define POWERMODE1(x) ((x) << 8) |
||||
#define POWERMODE1_MASK (0xff << 8) |
||||
#define POWERMODE2(x) ((x) << 16) |
||||
#define POWERMODE2_MASK (0xff << 16) |
||||
#define POWERMODE3(x) ((x) << 24) |
||||
#define POWERMODE3_MASK (0xff << 24) |
||||
|
||||
#define MC_ARB_DRAM_TIMING_1 0x27f0 |
||||
#define MC_ARB_DRAM_TIMING_2 0x27f4 |
||||
#define MC_ARB_DRAM_TIMING_3 0x27f8 |
||||
#define MC_ARB_DRAM_TIMING2_1 0x27fc |
||||
#define MC_ARB_DRAM_TIMING2_2 0x2800 |
||||
#define MC_ARB_DRAM_TIMING2_3 0x2804 |
||||
|
||||
#define MC4_IO_DQ_PAD_CNTL_D0_I0 0x2978 |
||||
#define MC4_IO_DQ_PAD_CNTL_D0_I1 0x297c |
||||
#define MC4_IO_QS_PAD_CNTL_D0_I0 0x2980 |
||||
#define MC4_IO_QS_PAD_CNTL_D0_I1 0x2984 |
||||
|
||||
#endif |
@ -0,0 +1,417 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
* Authors: Alex Deucher |
||||
*/ |
||||
|
||||
#include "drmP.h" |
||||
#include "radeon.h" |
||||
#include "rv740d.h" |
||||
#include "r600_dpm.h" |
||||
#include "rv770_dpm.h" |
||||
#include "atom.h" |
||||
|
||||
struct rv7xx_ps *rv770_get_ps(struct radeon_ps *rps); |
||||
struct rv7xx_power_info *rv770_get_pi(struct radeon_device *rdev); |
||||
|
||||
u32 rv740_get_decoded_reference_divider(u32 encoded_ref) |
||||
{ |
||||
u32 ref = 0; |
||||
|
||||
switch (encoded_ref) { |
||||
case 0: |
||||
ref = 1; |
||||
break; |
||||
case 16: |
||||
ref = 2; |
||||
break; |
||||
case 17: |
||||
ref = 3; |
||||
break; |
||||
case 18: |
||||
ref = 2; |
||||
break; |
||||
case 19: |
||||
ref = 3; |
||||
break; |
||||
case 20: |
||||
ref = 4; |
||||
break; |
||||
case 21: |
||||
ref = 5; |
||||
break; |
||||
default: |
||||
DRM_ERROR("Invalid encoded Reference Divider\n"); |
||||
ref = 0; |
||||
break; |
||||
} |
||||
|
||||
return ref; |
||||
} |
||||
|
||||
struct dll_speed_setting { |
||||
u16 min; |
||||
u16 max; |
||||
u32 dll_speed; |
||||
}; |
||||
|
||||
static struct dll_speed_setting dll_speed_table[16] = |
||||
{ |
||||
{ 270, 320, 0x0f }, |
||||
{ 240, 270, 0x0e }, |
||||
{ 200, 240, 0x0d }, |
||||
{ 180, 200, 0x0c }, |
||||
{ 160, 180, 0x0b }, |
||||
{ 140, 160, 0x0a }, |
||||
{ 120, 140, 0x09 }, |
||||
{ 110, 120, 0x08 }, |
||||
{ 95, 110, 0x07 }, |
||||
{ 85, 95, 0x06 }, |
||||
{ 78, 85, 0x05 }, |
||||
{ 70, 78, 0x04 }, |
||||
{ 65, 70, 0x03 }, |
||||
{ 60, 65, 0x02 }, |
||||
{ 42, 60, 0x01 }, |
||||
{ 00, 42, 0x00 } |
||||
}; |
||||
|
||||
u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock) |
||||
{ |
||||
int i; |
||||
u32 factor; |
||||
u16 data_rate; |
||||
|
||||
if (is_gddr5) |
||||
factor = 4; |
||||
else |
||||
factor = 2; |
||||
|
||||
data_rate = (u16)(memory_clock * factor / 1000); |
||||
|
||||
if (data_rate < dll_speed_table[0].max) { |
||||
for (i = 0; i < 16; i++) { |
||||
if (data_rate > dll_speed_table[i].min && |
||||
data_rate <= dll_speed_table[i].max) |
||||
return dll_speed_table[i].dll_speed; |
||||
} |
||||
} |
||||
|
||||
DRM_DEBUG_KMS("Target MCLK greater than largest MCLK in DLL speed table\n"); |
||||
|
||||
return 0x0f; |
||||
} |
||||
|
||||
int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, |
||||
RV770_SMC_SCLK_VALUE *sclk) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
struct atom_clock_dividers dividers; |
||||
u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; |
||||
u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; |
||||
u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; |
||||
u32 cg_spll_spread_spectrum = pi->clk_regs.rv770.cg_spll_spread_spectrum; |
||||
u32 cg_spll_spread_spectrum_2 = pi->clk_regs.rv770.cg_spll_spread_spectrum_2; |
||||
u64 tmp; |
||||
u32 reference_clock = rdev->clock.spll.reference_freq; |
||||
u32 reference_divider; |
||||
u32 fbdiv; |
||||
int ret; |
||||
|
||||
ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_ENGINE_PLL_PARAM, |
||||
engine_clock, false, ÷rs); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
reference_divider = 1 + dividers.ref_div; |
||||
|
||||
tmp = (u64) engine_clock * reference_divider * dividers.post_div * 16384; |
||||
do_div(tmp, reference_clock); |
||||
fbdiv = (u32) tmp; |
||||
|
||||
spll_func_cntl &= ~(SPLL_PDIV_A_MASK | SPLL_REF_DIV_MASK); |
||||
spll_func_cntl |= SPLL_REF_DIV(dividers.ref_div); |
||||
spll_func_cntl |= SPLL_PDIV_A(dividers.post_div); |
||||
|
||||
spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
||||
spll_func_cntl_2 |= SCLK_MUX_SEL(2); |
||||
|
||||
spll_func_cntl_3 &= ~SPLL_FB_DIV_MASK; |
||||
spll_func_cntl_3 |= SPLL_FB_DIV(fbdiv); |
||||
spll_func_cntl_3 |= SPLL_DITHEN; |
||||
|
||||
if (pi->sclk_ss) { |
||||
struct radeon_atom_ss ss; |
||||
u32 vco_freq = engine_clock * dividers.post_div; |
||||
|
||||
if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
||||
ASIC_INTERNAL_ENGINE_SS, vco_freq)) { |
||||
u32 clk_s = reference_clock * 5 / (reference_divider * ss.rate); |
||||
u32 clk_v = 4 * ss.percentage * fbdiv / (clk_s * 10000); |
||||
|
||||
cg_spll_spread_spectrum &= ~CLK_S_MASK; |
||||
cg_spll_spread_spectrum |= CLK_S(clk_s); |
||||
cg_spll_spread_spectrum |= SSEN; |
||||
|
||||
cg_spll_spread_spectrum_2 &= ~CLK_V_MASK; |
||||
cg_spll_spread_spectrum_2 |= CLK_V(clk_v); |
||||
} |
||||
} |
||||
|
||||
sclk->sclk_value = cpu_to_be32(engine_clock); |
||||
sclk->vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
||||
sclk->vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
||||
sclk->vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
||||
sclk->vCG_SPLL_SPREAD_SPECTRUM = cpu_to_be32(cg_spll_spread_spectrum); |
||||
sclk->vCG_SPLL_SPREAD_SPECTRUM_2 = cpu_to_be32(cg_spll_spread_spectrum_2); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rv740_populate_mclk_value(struct radeon_device *rdev, |
||||
u32 engine_clock, u32 memory_clock, |
||||
RV7XX_SMC_MCLK_VALUE *mclk) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; |
||||
u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; |
||||
u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; |
||||
u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; |
||||
u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; |
||||
u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; |
||||
u32 mpll_ss1 = pi->clk_regs.rv770.mpll_ss1; |
||||
u32 mpll_ss2 = pi->clk_regs.rv770.mpll_ss2; |
||||
struct atom_clock_dividers dividers; |
||||
u32 ibias; |
||||
u32 dll_speed; |
||||
int ret; |
||||
|
||||
ret = radeon_atom_get_clock_dividers(rdev, COMPUTE_MEMORY_PLL_PARAM, |
||||
memory_clock, false, ÷rs); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
ibias = rv770_map_clkf_to_ibias(rdev, dividers.whole_fb_div); |
||||
|
||||
mpll_ad_func_cntl &= ~(CLKR_MASK | |
||||
YCLK_POST_DIV_MASK | |
||||
CLKF_MASK | |
||||
CLKFRAC_MASK | |
||||
IBIAS_MASK); |
||||
mpll_ad_func_cntl |= CLKR(dividers.ref_div); |
||||
mpll_ad_func_cntl |= YCLK_POST_DIV(dividers.post_div); |
||||
mpll_ad_func_cntl |= CLKF(dividers.whole_fb_div); |
||||
mpll_ad_func_cntl |= CLKFRAC(dividers.frac_fb_div); |
||||
mpll_ad_func_cntl |= IBIAS(ibias); |
||||
|
||||
if (dividers.vco_mode) |
||||
mpll_ad_func_cntl_2 |= VCO_MODE; |
||||
else |
||||
mpll_ad_func_cntl_2 &= ~VCO_MODE; |
||||
|
||||
if (pi->mem_gddr5) { |
||||
mpll_dq_func_cntl &= ~(CLKR_MASK | |
||||
YCLK_POST_DIV_MASK | |
||||
CLKF_MASK | |
||||
CLKFRAC_MASK | |
||||
IBIAS_MASK); |
||||
mpll_dq_func_cntl |= CLKR(dividers.ref_div); |
||||
mpll_dq_func_cntl |= YCLK_POST_DIV(dividers.post_div); |
||||
mpll_dq_func_cntl |= CLKF(dividers.whole_fb_div); |
||||
mpll_dq_func_cntl |= CLKFRAC(dividers.frac_fb_div); |
||||
mpll_dq_func_cntl |= IBIAS(ibias); |
||||
|
||||
if (dividers.vco_mode) |
||||
mpll_dq_func_cntl_2 |= VCO_MODE; |
||||
else |
||||
mpll_dq_func_cntl_2 &= ~VCO_MODE; |
||||
} |
||||
|
||||
if (pi->mclk_ss) { |
||||
struct radeon_atom_ss ss; |
||||
u32 vco_freq = memory_clock * dividers.post_div; |
||||
|
||||
if (radeon_atombios_get_asic_ss_info(rdev, &ss, |
||||
ASIC_INTERNAL_MEMORY_SS, vco_freq)) { |
||||
u32 reference_clock = rdev->clock.mpll.reference_freq; |
||||
u32 decoded_ref = rv740_get_decoded_reference_divider(dividers.ref_div); |
||||
u32 clk_s = reference_clock * 5 / (decoded_ref * ss.rate); |
||||
u32 clk_v = 0x40000 * ss.percentage * |
||||
(dividers.whole_fb_div + (dividers.frac_fb_div / 8)) / (clk_s * 10000); |
||||
|
||||
mpll_ss1 &= ~CLKV_MASK; |
||||
mpll_ss1 |= CLKV(clk_v); |
||||
|
||||
mpll_ss2 &= ~CLKS_MASK; |
||||
mpll_ss2 |= CLKS(clk_s); |
||||
} |
||||
} |
||||
|
||||
dll_speed = rv740_get_dll_speed(pi->mem_gddr5, |
||||
memory_clock); |
||||
|
||||
mclk_pwrmgt_cntl &= ~DLL_SPEED_MASK; |
||||
mclk_pwrmgt_cntl |= DLL_SPEED(dll_speed); |
||||
|
||||
mclk->mclk770.mclk_value = cpu_to_be32(memory_clock); |
||||
mclk->mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); |
||||
mclk->mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); |
||||
mclk->mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); |
||||
mclk->mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); |
||||
mclk->mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
||||
mclk->mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); |
||||
mclk->mclk770.vMPLL_SS = cpu_to_be32(mpll_ss1); |
||||
mclk->mclk770.vMPLL_SS2 = cpu_to_be32(mpll_ss2); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rv740_read_clock_registers(struct radeon_device *rdev) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
|
||||
pi->clk_regs.rv770.cg_spll_func_cntl = |
||||
RREG32(CG_SPLL_FUNC_CNTL); |
||||
pi->clk_regs.rv770.cg_spll_func_cntl_2 = |
||||
RREG32(CG_SPLL_FUNC_CNTL_2); |
||||
pi->clk_regs.rv770.cg_spll_func_cntl_3 = |
||||
RREG32(CG_SPLL_FUNC_CNTL_3); |
||||
pi->clk_regs.rv770.cg_spll_spread_spectrum = |
||||
RREG32(CG_SPLL_SPREAD_SPECTRUM); |
||||
pi->clk_regs.rv770.cg_spll_spread_spectrum_2 = |
||||
RREG32(CG_SPLL_SPREAD_SPECTRUM_2); |
||||
|
||||
pi->clk_regs.rv770.mpll_ad_func_cntl = |
||||
RREG32(MPLL_AD_FUNC_CNTL); |
||||
pi->clk_regs.rv770.mpll_ad_func_cntl_2 = |
||||
RREG32(MPLL_AD_FUNC_CNTL_2); |
||||
pi->clk_regs.rv770.mpll_dq_func_cntl = |
||||
RREG32(MPLL_DQ_FUNC_CNTL); |
||||
pi->clk_regs.rv770.mpll_dq_func_cntl_2 = |
||||
RREG32(MPLL_DQ_FUNC_CNTL_2); |
||||
pi->clk_regs.rv770.mclk_pwrmgt_cntl = |
||||
RREG32(MCLK_PWRMGT_CNTL); |
||||
pi->clk_regs.rv770.dll_cntl = RREG32(DLL_CNTL); |
||||
pi->clk_regs.rv770.mpll_ss1 = RREG32(MPLL_SS1); |
||||
pi->clk_regs.rv770.mpll_ss2 = RREG32(MPLL_SS2); |
||||
} |
||||
|
||||
int rv740_populate_smc_acpi_state(struct radeon_device *rdev, |
||||
RV770_SMC_STATETABLE *table) |
||||
{ |
||||
struct rv7xx_power_info *pi = rv770_get_pi(rdev); |
||||
u32 mpll_ad_func_cntl = pi->clk_regs.rv770.mpll_ad_func_cntl; |
||||
u32 mpll_ad_func_cntl_2 = pi->clk_regs.rv770.mpll_ad_func_cntl_2; |
||||
u32 mpll_dq_func_cntl = pi->clk_regs.rv770.mpll_dq_func_cntl; |
||||
u32 mpll_dq_func_cntl_2 = pi->clk_regs.rv770.mpll_dq_func_cntl_2; |
||||
u32 spll_func_cntl = pi->clk_regs.rv770.cg_spll_func_cntl; |
||||
u32 spll_func_cntl_2 = pi->clk_regs.rv770.cg_spll_func_cntl_2; |
||||
u32 spll_func_cntl_3 = pi->clk_regs.rv770.cg_spll_func_cntl_3; |
||||
u32 mclk_pwrmgt_cntl = pi->clk_regs.rv770.mclk_pwrmgt_cntl; |
||||
u32 dll_cntl = pi->clk_regs.rv770.dll_cntl; |
||||
|
||||
table->ACPIState = table->initialState; |
||||
|
||||
table->ACPIState.flags &= ~PPSMC_SWSTATE_FLAG_DC; |
||||
|
||||
if (pi->acpi_vddc) { |
||||
rv770_populate_vddc_value(rdev, pi->acpi_vddc, |
||||
&table->ACPIState.levels[0].vddc); |
||||
table->ACPIState.levels[0].gen2PCIE = |
||||
pi->pcie_gen2 ? |
||||
pi->acpi_pcie_gen2 : 0; |
||||
table->ACPIState.levels[0].gen2XSP = |
||||
pi->acpi_pcie_gen2; |
||||
} else { |
||||
rv770_populate_vddc_value(rdev, pi->min_vddc_in_table, |
||||
&table->ACPIState.levels[0].vddc); |
||||
table->ACPIState.levels[0].gen2PCIE = 0; |
||||
} |
||||
|
||||
mpll_ad_func_cntl_2 |= BIAS_GEN_PDNB | RESET_EN; |
||||
|
||||
mpll_dq_func_cntl_2 |= BYPASS | BIAS_GEN_PDNB | RESET_EN; |
||||
|
||||
mclk_pwrmgt_cntl |= (MRDCKA0_RESET | |
||||
MRDCKA1_RESET | |
||||
MRDCKB0_RESET | |
||||
MRDCKB1_RESET | |
||||
MRDCKC0_RESET | |
||||
MRDCKC1_RESET | |
||||
MRDCKD0_RESET | |
||||
MRDCKD1_RESET); |
||||
|
||||
dll_cntl |= (MRDCKA0_BYPASS | |
||||
MRDCKA1_BYPASS | |
||||
MRDCKB0_BYPASS | |
||||
MRDCKB1_BYPASS | |
||||
MRDCKC0_BYPASS | |
||||
MRDCKC1_BYPASS | |
||||
MRDCKD0_BYPASS | |
||||
MRDCKD1_BYPASS); |
||||
|
||||
spll_func_cntl |= SPLL_RESET | SPLL_SLEEP | SPLL_BYPASS_EN; |
||||
|
||||
spll_func_cntl_2 &= ~SCLK_MUX_SEL_MASK; |
||||
spll_func_cntl_2 |= SCLK_MUX_SEL(4); |
||||
|
||||
table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL = cpu_to_be32(mpll_ad_func_cntl); |
||||
table->ACPIState.levels[0].mclk.mclk770.vMPLL_AD_FUNC_CNTL_2 = cpu_to_be32(mpll_ad_func_cntl_2); |
||||
table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL = cpu_to_be32(mpll_dq_func_cntl); |
||||
table->ACPIState.levels[0].mclk.mclk770.vMPLL_DQ_FUNC_CNTL_2 = cpu_to_be32(mpll_dq_func_cntl_2); |
||||
table->ACPIState.levels[0].mclk.mclk770.vMCLK_PWRMGT_CNTL = cpu_to_be32(mclk_pwrmgt_cntl); |
||||
table->ACPIState.levels[0].mclk.mclk770.vDLL_CNTL = cpu_to_be32(dll_cntl); |
||||
|
||||
table->ACPIState.levels[0].mclk.mclk770.mclk_value = 0; |
||||
|
||||
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL = cpu_to_be32(spll_func_cntl); |
||||
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_2 = cpu_to_be32(spll_func_cntl_2); |
||||
table->ACPIState.levels[0].sclk.vCG_SPLL_FUNC_CNTL_3 = cpu_to_be32(spll_func_cntl_3); |
||||
|
||||
table->ACPIState.levels[0].sclk.sclk_value = 0; |
||||
|
||||
table->ACPIState.levels[1] = table->ACPIState.levels[0]; |
||||
table->ACPIState.levels[2] = table->ACPIState.levels[0]; |
||||
|
||||
rv770_populate_mvdd_value(rdev, 0, &table->ACPIState.levels[0].mvdd); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, |
||||
bool enable) |
||||
{ |
||||
if (enable) |
||||
WREG32_P(MPLL_CNTL_MODE, SS_SSEN, ~SS_SSEN); |
||||
else |
||||
WREG32_P(MPLL_CNTL_MODE, 0, ~SS_SSEN); |
||||
} |
||||
|
||||
u8 rv740_get_mclk_frequency_ratio(u32 memory_clock) |
||||
{ |
||||
u8 mc_para_index; |
||||
|
||||
if ((memory_clock < 10000) || (memory_clock > 47500)) |
||||
mc_para_index = 0x00; |
||||
else |
||||
mc_para_index = (u8)((memory_clock - 10000) / 2500); |
||||
|
||||
return mc_para_index; |
||||
} |
@ -0,0 +1,117 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
*/ |
||||
#ifndef RV740_H |
||||
#define RV740_H |
||||
|
||||
#define CG_SPLL_FUNC_CNTL 0x600 |
||||
#define SPLL_RESET (1 << 0) |
||||
#define SPLL_SLEEP (1 << 1) |
||||
#define SPLL_BYPASS_EN (1 << 3) |
||||
#define SPLL_REF_DIV(x) ((x) << 4) |
||||
#define SPLL_REF_DIV_MASK (0x3f << 4) |
||||
#define SPLL_PDIV_A(x) ((x) << 20) |
||||
#define SPLL_PDIV_A_MASK (0x7f << 20) |
||||
#define CG_SPLL_FUNC_CNTL_2 0x604 |
||||
#define SCLK_MUX_SEL(x) ((x) << 0) |
||||
#define SCLK_MUX_SEL_MASK (0x1ff << 0) |
||||
#define CG_SPLL_FUNC_CNTL_3 0x608 |
||||
#define SPLL_FB_DIV(x) ((x) << 0) |
||||
#define SPLL_FB_DIV_MASK (0x3ffffff << 0) |
||||
#define SPLL_DITHEN (1 << 28) |
||||
|
||||
#define MPLL_CNTL_MODE 0x61c |
||||
#define SS_SSEN (1 << 24) |
||||
|
||||
#define MPLL_AD_FUNC_CNTL 0x624 |
||||
#define CLKF(x) ((x) << 0) |
||||
#define CLKF_MASK (0x7f << 0) |
||||
#define CLKR(x) ((x) << 7) |
||||
#define CLKR_MASK (0x1f << 7) |
||||
#define CLKFRAC(x) ((x) << 12) |
||||
#define CLKFRAC_MASK (0x1f << 12) |
||||
#define YCLK_POST_DIV(x) ((x) << 17) |
||||
#define YCLK_POST_DIV_MASK (3 << 17) |
||||
#define IBIAS(x) ((x) << 20) |
||||
#define IBIAS_MASK (0x3ff << 20) |
||||
#define RESET (1 << 30) |
||||
#define PDNB (1 << 31) |
||||
#define MPLL_AD_FUNC_CNTL_2 0x628 |
||||
#define BYPASS (1 << 19) |
||||
#define BIAS_GEN_PDNB (1 << 24) |
||||
#define RESET_EN (1 << 25) |
||||
#define VCO_MODE (1 << 29) |
||||
#define MPLL_DQ_FUNC_CNTL 0x62c |
||||
#define MPLL_DQ_FUNC_CNTL_2 0x630 |
||||
|
||||
#define MCLK_PWRMGT_CNTL 0x648 |
||||
#define DLL_SPEED(x) ((x) << 0) |
||||
#define DLL_SPEED_MASK (0x1f << 0) |
||||
# define MPLL_PWRMGT_OFF (1 << 5) |
||||
# define DLL_READY (1 << 6) |
||||
# define MC_INT_CNTL (1 << 7) |
||||
# define MRDCKA0_SLEEP (1 << 8) |
||||
# define MRDCKA1_SLEEP (1 << 9) |
||||
# define MRDCKB0_SLEEP (1 << 10) |
||||
# define MRDCKB1_SLEEP (1 << 11) |
||||
# define MRDCKC0_SLEEP (1 << 12) |
||||
# define MRDCKC1_SLEEP (1 << 13) |
||||
# define MRDCKD0_SLEEP (1 << 14) |
||||
# define MRDCKD1_SLEEP (1 << 15) |
||||
# define MRDCKA0_RESET (1 << 16) |
||||
# define MRDCKA1_RESET (1 << 17) |
||||
# define MRDCKB0_RESET (1 << 18) |
||||
# define MRDCKB1_RESET (1 << 19) |
||||
# define MRDCKC0_RESET (1 << 20) |
||||
# define MRDCKC1_RESET (1 << 21) |
||||
# define MRDCKD0_RESET (1 << 22) |
||||
# define MRDCKD1_RESET (1 << 23) |
||||
# define DLL_READY_READ (1 << 24) |
||||
# define USE_DISPLAY_GAP (1 << 25) |
||||
# define USE_DISPLAY_URGENT_NORMAL (1 << 26) |
||||
# define MPLL_TURNOFF_D2 (1 << 28) |
||||
#define DLL_CNTL 0x64c |
||||
# define MRDCKA0_BYPASS (1 << 24) |
||||
# define MRDCKA1_BYPASS (1 << 25) |
||||
# define MRDCKB0_BYPASS (1 << 26) |
||||
# define MRDCKB1_BYPASS (1 << 27) |
||||
# define MRDCKC0_BYPASS (1 << 28) |
||||
# define MRDCKC1_BYPASS (1 << 29) |
||||
# define MRDCKD0_BYPASS (1 << 30) |
||||
# define MRDCKD1_BYPASS (1 << 31) |
||||
|
||||
#define CG_SPLL_SPREAD_SPECTRUM 0x790 |
||||
#define SSEN (1 << 0) |
||||
#define CLK_S(x) ((x) << 4) |
||||
#define CLK_S_MASK (0xfff << 4) |
||||
#define CG_SPLL_SPREAD_SPECTRUM_2 0x794 |
||||
#define CLK_V(x) ((x) << 0) |
||||
#define CLK_V_MASK (0x3ffffff << 0) |
||||
|
||||
#define MPLL_SS1 0x85c |
||||
#define CLKV(x) ((x) << 0) |
||||
#define CLKV_MASK (0x3ffffff << 0) |
||||
#define MPLL_SS2 0x860 |
||||
#define CLKS(x) ((x) << 0) |
||||
#define CLKS_MASK (0xfff << 0) |
||||
|
||||
#endif |
File diff suppressed because it is too large
Load Diff
@ -0,0 +1,273 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
*/ |
||||
#ifndef __RV770_DPM_H__ |
||||
#define __RV770_DPM_H__ |
||||
|
||||
#include "rv770_smc.h" |
||||
|
||||
struct rv770_clock_registers { |
||||
u32 cg_spll_func_cntl; |
||||
u32 cg_spll_func_cntl_2; |
||||
u32 cg_spll_func_cntl_3; |
||||
u32 cg_spll_spread_spectrum; |
||||
u32 cg_spll_spread_spectrum_2; |
||||
u32 mpll_ad_func_cntl; |
||||
u32 mpll_ad_func_cntl_2; |
||||
u32 mpll_dq_func_cntl; |
||||
u32 mpll_dq_func_cntl_2; |
||||
u32 mclk_pwrmgt_cntl; |
||||
u32 dll_cntl; |
||||
u32 mpll_ss1; |
||||
u32 mpll_ss2; |
||||
}; |
||||
|
||||
struct rv730_clock_registers { |
||||
u32 cg_spll_func_cntl; |
||||
u32 cg_spll_func_cntl_2; |
||||
u32 cg_spll_func_cntl_3; |
||||
u32 cg_spll_spread_spectrum; |
||||
u32 cg_spll_spread_spectrum_2; |
||||
u32 mclk_pwrmgt_cntl; |
||||
u32 dll_cntl; |
||||
u32 mpll_func_cntl; |
||||
u32 mpll_func_cntl2; |
||||
u32 mpll_func_cntl3; |
||||
u32 mpll_ss; |
||||
u32 mpll_ss2; |
||||
}; |
||||
|
||||
union r7xx_clock_registers { |
||||
struct rv770_clock_registers rv770; |
||||
struct rv730_clock_registers rv730; |
||||
}; |
||||
|
||||
struct vddc_table_entry { |
||||
u16 vddc; |
||||
u8 vddc_index; |
||||
u8 high_smio; |
||||
u32 low_smio; |
||||
}; |
||||
|
||||
#define MAX_NO_OF_MVDD_VALUES 2 |
||||
#define MAX_NO_VREG_STEPS 32 |
||||
|
||||
struct rv7xx_power_info { |
||||
/* flags */ |
||||
bool mem_gddr5; |
||||
bool pcie_gen2; |
||||
bool dynamic_pcie_gen2; |
||||
bool acpi_pcie_gen2; |
||||
bool boot_in_gen2; |
||||
bool voltage_control; /* vddc */ |
||||
bool mvdd_control; |
||||
bool sclk_ss; |
||||
bool mclk_ss; |
||||
bool dynamic_ss; |
||||
bool gfx_clock_gating; |
||||
bool mg_clock_gating; |
||||
bool mgcgtssm; |
||||
bool power_gating; |
||||
bool thermal_protection; |
||||
bool display_gap; |
||||
bool dcodt; |
||||
bool ulps; |
||||
/* registers */ |
||||
union r7xx_clock_registers clk_regs; |
||||
u32 s0_vid_lower_smio_cntl; |
||||
/* voltage */ |
||||
u32 vddc_mask_low; |
||||
u32 mvdd_mask_low; |
||||
u32 mvdd_split_frequency; |
||||
u32 mvdd_low_smio[MAX_NO_OF_MVDD_VALUES]; |
||||
u16 max_vddc; |
||||
u16 max_vddc_in_table; |
||||
u16 min_vddc_in_table; |
||||
struct vddc_table_entry vddc_table[MAX_NO_VREG_STEPS]; |
||||
u8 valid_vddc_entries; |
||||
/* dc odt */ |
||||
u32 mclk_odt_threshold; |
||||
u8 odt_value_0[2]; |
||||
u8 odt_value_1[2]; |
||||
/* stored values */ |
||||
u32 boot_sclk; |
||||
u16 acpi_vddc; |
||||
u32 ref_div; |
||||
u32 active_auto_throttle_sources; |
||||
u32 mclk_stutter_mode_threshold; |
||||
u32 mclk_strobe_mode_threshold; |
||||
u32 mclk_edc_enable_threshold; |
||||
u32 bsp; |
||||
u32 bsu; |
||||
u32 pbsp; |
||||
u32 pbsu; |
||||
u32 dsp; |
||||
u32 psp; |
||||
u32 asi; |
||||
u32 pasi; |
||||
u32 vrc; |
||||
u32 restricted_levels; |
||||
/* smc offsets */ |
||||
u16 state_table_start; |
||||
u16 soft_regs_start; |
||||
u16 sram_end; |
||||
/* scratch structs */ |
||||
RV770_SMC_STATETABLE smc_statetable; |
||||
}; |
||||
|
||||
struct rv7xx_pl { |
||||
u32 sclk; |
||||
u32 mclk; |
||||
u16 vddc; |
||||
u16 vddci; /* eg+ only */ |
||||
u32 flags; |
||||
}; |
||||
|
||||
struct rv7xx_ps { |
||||
struct rv7xx_pl high; |
||||
struct rv7xx_pl medium; |
||||
struct rv7xx_pl low; |
||||
bool dc_compatible; |
||||
}; |
||||
|
||||
#define RV770_RLP_DFLT 10 |
||||
#define RV770_RMP_DFLT 25 |
||||
#define RV770_LHP_DFLT 25 |
||||
#define RV770_LMP_DFLT 10 |
||||
#define RV770_VRC_DFLT 0x003f |
||||
#define RV770_ASI_DFLT 1000 |
||||
#define RV770_HASI_DFLT 200000 |
||||
#define RV770_MGCGTTLOCAL0_DFLT 0x00100000 |
||||
#define RV7XX_MGCGTTLOCAL0_DFLT 0 |
||||
#define RV770_MGCGTTLOCAL1_DFLT 0xFFFF0000 |
||||
#define RV770_MGCGCGTSSMCTRL_DFLT 0x55940000 |
||||
|
||||
#define MVDD_LOW_INDEX 0 |
||||
#define MVDD_HIGH_INDEX 1 |
||||
|
||||
#define MVDD_LOW_VALUE 0 |
||||
#define MVDD_HIGH_VALUE 0xffff |
||||
|
||||
#define RV770_DEFAULT_VCLK_FREQ 53300 /* 10 khz */ |
||||
#define RV770_DEFAULT_DCLK_FREQ 40000 /* 10 khz */ |
||||
|
||||
/* rv730/rv710 */ |
||||
int rv730_populate_sclk_value(struct radeon_device *rdev, |
||||
u32 engine_clock, |
||||
RV770_SMC_SCLK_VALUE *sclk); |
||||
int rv730_populate_mclk_value(struct radeon_device *rdev, |
||||
u32 engine_clock, u32 memory_clock, |
||||
LPRV7XX_SMC_MCLK_VALUE mclk); |
||||
void rv730_read_clock_registers(struct radeon_device *rdev); |
||||
int rv730_populate_smc_acpi_state(struct radeon_device *rdev, |
||||
RV770_SMC_STATETABLE *table); |
||||
int rv730_populate_smc_initial_state(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_initial_state, |
||||
RV770_SMC_STATETABLE *table); |
||||
void rv730_program_memory_timing_parameters(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_state); |
||||
void rv730_power_gating_enable(struct radeon_device *rdev, |
||||
bool enable); |
||||
void rv730_start_dpm(struct radeon_device *rdev); |
||||
void rv730_stop_dpm(struct radeon_device *rdev); |
||||
void rv730_program_dcodt(struct radeon_device *rdev, bool use_dcodt); |
||||
void rv730_get_odt_values(struct radeon_device *rdev); |
||||
|
||||
/* rv740 */ |
||||
int rv740_populate_sclk_value(struct radeon_device *rdev, u32 engine_clock, |
||||
RV770_SMC_SCLK_VALUE *sclk); |
||||
int rv740_populate_mclk_value(struct radeon_device *rdev, |
||||
u32 engine_clock, u32 memory_clock, |
||||
RV7XX_SMC_MCLK_VALUE *mclk); |
||||
void rv740_read_clock_registers(struct radeon_device *rdev); |
||||
int rv740_populate_smc_acpi_state(struct radeon_device *rdev, |
||||
RV770_SMC_STATETABLE *table); |
||||
void rv740_enable_mclk_spread_spectrum(struct radeon_device *rdev, |
||||
bool enable); |
||||
u8 rv740_get_mclk_frequency_ratio(u32 memory_clock); |
||||
u32 rv740_get_dll_speed(bool is_gddr5, u32 memory_clock); |
||||
u32 rv740_get_decoded_reference_divider(u32 encoded_ref); |
||||
|
||||
/* rv770 */ |
||||
u32 rv770_map_clkf_to_ibias(struct radeon_device *rdev, u32 clkf); |
||||
int rv770_populate_vddc_value(struct radeon_device *rdev, u16 vddc, |
||||
RV770_SMC_VOLTAGE_VALUE *voltage); |
||||
int rv770_populate_mvdd_value(struct radeon_device *rdev, u32 mclk, |
||||
RV770_SMC_VOLTAGE_VALUE *voltage); |
||||
u8 rv770_get_seq_value(struct radeon_device *rdev, |
||||
struct rv7xx_pl *pl); |
||||
int rv770_populate_initial_mvdd_value(struct radeon_device *rdev, |
||||
RV770_SMC_VOLTAGE_VALUE *voltage); |
||||
u32 rv770_calculate_memory_refresh_rate(struct radeon_device *rdev, |
||||
u32 engine_clock); |
||||
void rv770_program_response_times(struct radeon_device *rdev); |
||||
int rv770_populate_smc_sp(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_state, |
||||
RV770_SMC_SWSTATE *smc_state); |
||||
int rv770_populate_smc_t(struct radeon_device *rdev, |
||||
struct radeon_ps *radeon_state, |
||||
RV770_SMC_SWSTATE *smc_state); |
||||
void rv770_read_voltage_smio_registers(struct radeon_device *rdev); |
||||
void rv770_get_memory_type(struct radeon_device *rdev); |
||||
void r7xx_start_smc(struct radeon_device *rdev); |
||||
u8 rv770_get_memory_module_index(struct radeon_device *rdev); |
||||
void rv770_get_max_vddc(struct radeon_device *rdev); |
||||
void rv770_get_pcie_gen2_status(struct radeon_device *rdev); |
||||
void rv770_enable_acpi_pm(struct radeon_device *rdev); |
||||
void rv770_restore_cgcg(struct radeon_device *rdev); |
||||
bool rv770_dpm_enabled(struct radeon_device *rdev); |
||||
void rv770_enable_voltage_control(struct radeon_device *rdev, |
||||
bool enable); |
||||
void rv770_enable_backbias(struct radeon_device *rdev, |
||||
bool enable); |
||||
void rv770_enable_thermal_protection(struct radeon_device *rdev, |
||||
bool enable); |
||||
void rv770_enable_auto_throttle_source(struct radeon_device *rdev, |
||||
enum radeon_dpm_auto_throttle_src source, |
||||
bool enable); |
||||
void rv770_setup_bsp(struct radeon_device *rdev); |
||||
void rv770_program_git(struct radeon_device *rdev); |
||||
void rv770_program_tp(struct radeon_device *rdev); |
||||
void rv770_program_tpp(struct radeon_device *rdev); |
||||
void rv770_program_sstp(struct radeon_device *rdev); |
||||
void rv770_program_engine_speed_parameters(struct radeon_device *rdev); |
||||
void rv770_program_vc(struct radeon_device *rdev); |
||||
void rv770_clear_vc(struct radeon_device *rdev); |
||||
int rv770_upload_firmware(struct radeon_device *rdev); |
||||
void rv770_stop_dpm(struct radeon_device *rdev); |
||||
void r7xx_stop_smc(struct radeon_device *rdev); |
||||
void rv770_reset_smio_status(struct radeon_device *rdev); |
||||
int rv770_restrict_performance_levels_before_switch(struct radeon_device *rdev); |
||||
int rv770_unrestrict_performance_levels_after_switch(struct radeon_device *rdev); |
||||
int rv770_halt_smc(struct radeon_device *rdev); |
||||
int rv770_resume_smc(struct radeon_device *rdev); |
||||
int rv770_set_sw_state(struct radeon_device *rdev); |
||||
int rv770_set_boot_state(struct radeon_device *rdev); |
||||
int rv7xx_parse_power_table(struct radeon_device *rdev); |
||||
|
||||
/* smc */ |
||||
int rv770_read_smc_soft_register(struct radeon_device *rdev, |
||||
u16 reg_offset, u32 *value); |
||||
int rv770_write_smc_soft_register(struct radeon_device *rdev, |
||||
u16 reg_offset, u32 value); |
||||
|
||||
#endif |
@ -0,0 +1,404 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
* Authors: Alex Deucher |
||||
*/ |
||||
|
||||
#include <linux/firmware.h> |
||||
#include "drmP.h" |
||||
#include "radeon.h" |
||||
#include "rv770d.h" |
||||
#include "rv770_dpm.h" |
||||
#include "rv770_smc.h" |
||||
#include "atom.h" |
||||
#include "radeon_ucode.h" |
||||
|
||||
#define FIRST_SMC_INT_VECT_REG 0xFFD8 |
||||
#define FIRST_INT_VECT_S19 0xFFC0 |
||||
|
||||
static const u8 rv770_smc_int_vectors[] = |
||||
{ |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x0C, 0xD7, |
||||
0x08, 0x2B, 0x08, 0x10, |
||||
0x03, 0x51, 0x03, 0x51, |
||||
0x03, 0x51, 0x03, 0x51 |
||||
}; |
||||
|
||||
static const u8 rv730_smc_int_vectors[] = |
||||
{ |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x08, 0x15, |
||||
0x08, 0x15, 0x0C, 0xBB, |
||||
0x08, 0x30, 0x08, 0x15, |
||||
0x03, 0x56, 0x03, 0x56, |
||||
0x03, 0x56, 0x03, 0x56 |
||||
}; |
||||
|
||||
static const u8 rv710_smc_int_vectors[] = |
||||
{ |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x08, 0x04, |
||||
0x08, 0x04, 0x0C, 0xCB, |
||||
0x08, 0x1F, 0x08, 0x04, |
||||
0x03, 0x51, 0x03, 0x51, |
||||
0x03, 0x51, 0x03, 0x51 |
||||
}; |
||||
|
||||
static const u8 rv740_smc_int_vectors[] = |
||||
{ |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x08, 0x10, |
||||
0x08, 0x10, 0x0C, 0xD7, |
||||
0x08, 0x2B, 0x08, 0x10, |
||||
0x03, 0x51, 0x03, 0x51, |
||||
0x03, 0x51, 0x03, 0x51 |
||||
}; |
||||
|
||||
int rv770_set_smc_sram_address(struct radeon_device *rdev, |
||||
u16 smc_address, u16 limit) |
||||
{ |
||||
u32 addr; |
||||
|
||||
if (smc_address & 3) |
||||
return -EINVAL; |
||||
if ((smc_address + 3) > limit) |
||||
return -EINVAL; |
||||
|
||||
addr = smc_address; |
||||
addr |= SMC_SRAM_AUTO_INC_DIS; |
||||
|
||||
WREG32(SMC_SRAM_ADDR, addr); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rv770_copy_bytes_to_smc(struct radeon_device *rdev, |
||||
u16 smc_start_address, const u8 *src, |
||||
u16 byte_count, u16 limit) |
||||
{ |
||||
u32 data, original_data, extra_shift; |
||||
u16 addr; |
||||
int ret; |
||||
|
||||
if (smc_start_address & 3) |
||||
return -EINVAL; |
||||
if ((smc_start_address + byte_count) > limit) |
||||
return -EINVAL; |
||||
|
||||
addr = smc_start_address; |
||||
|
||||
while (byte_count >= 4) { |
||||
/* SMC address space is BE */ |
||||
data = (src[0] << 24) | (src[1] << 16) | (src[2] << 8) | src[3]; |
||||
|
||||
ret = rv770_set_smc_sram_address(rdev, addr, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
WREG32(SMC_SRAM_DATA, data); |
||||
|
||||
src += 4; |
||||
byte_count -= 4; |
||||
addr += 4; |
||||
} |
||||
|
||||
/* RMW for final bytes */ |
||||
if (byte_count > 0) { |
||||
data = 0; |
||||
|
||||
ret = rv770_set_smc_sram_address(rdev, addr, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
original_data = RREG32(SMC_SRAM_DATA); |
||||
|
||||
extra_shift = 8 * (4 - byte_count); |
||||
|
||||
while (byte_count > 0) { |
||||
/* SMC address space is BE */ |
||||
data = (data << 8) + *src++; |
||||
byte_count--; |
||||
} |
||||
|
||||
data <<= extra_shift; |
||||
|
||||
data |= (original_data & ~((~0UL) << extra_shift)); |
||||
|
||||
ret = rv770_set_smc_sram_address(rdev, addr, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
WREG32(SMC_SRAM_DATA, data); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int rv770_program_interrupt_vectors(struct radeon_device *rdev, |
||||
u32 smc_first_vector, const u8 *src, |
||||
u32 byte_count) |
||||
{ |
||||
u32 tmp, i; |
||||
|
||||
if (byte_count % 4) |
||||
return -EINVAL; |
||||
|
||||
if (smc_first_vector < FIRST_SMC_INT_VECT_REG) { |
||||
tmp = FIRST_SMC_INT_VECT_REG - smc_first_vector; |
||||
|
||||
if (tmp > byte_count) |
||||
return 0; |
||||
|
||||
byte_count -= tmp; |
||||
src += tmp; |
||||
smc_first_vector = FIRST_SMC_INT_VECT_REG; |
||||
} |
||||
|
||||
for (i = 0; i < byte_count; i += 4) { |
||||
/* SMC address space is BE */ |
||||
tmp = (src[i] << 24) | (src[i + 1] << 16) | (src[i + 2] << 8) | src[i + 3]; |
||||
|
||||
WREG32(SMC_ISR_FFD8_FFDB + i, tmp); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
void rv770_start_smc(struct radeon_device *rdev) |
||||
{ |
||||
WREG32_P(SMC_IO, SMC_RST_N, ~SMC_RST_N); |
||||
} |
||||
|
||||
void rv770_reset_smc(struct radeon_device *rdev) |
||||
{ |
||||
WREG32_P(SMC_IO, 0, ~SMC_RST_N); |
||||
} |
||||
|
||||
void rv770_stop_smc_clock(struct radeon_device *rdev) |
||||
{ |
||||
WREG32_P(SMC_IO, 0, ~SMC_CLK_EN); |
||||
} |
||||
|
||||
void rv770_start_smc_clock(struct radeon_device *rdev) |
||||
{ |
||||
WREG32_P(SMC_IO, SMC_CLK_EN, ~SMC_CLK_EN); |
||||
} |
||||
|
||||
bool rv770_is_smc_running(struct radeon_device *rdev) |
||||
{ |
||||
u32 tmp; |
||||
|
||||
tmp = RREG32(SMC_IO); |
||||
|
||||
if ((tmp & SMC_RST_N) && (tmp & SMC_CLK_EN)) |
||||
return true; |
||||
else |
||||
return false; |
||||
} |
||||
|
||||
PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg) |
||||
{ |
||||
u32 tmp; |
||||
int i; |
||||
PPSMC_Result result; |
||||
|
||||
if (!rv770_is_smc_running(rdev)) |
||||
return PPSMC_Result_Failed; |
||||
|
||||
WREG32_P(SMC_MSG, HOST_SMC_MSG(msg), ~HOST_SMC_MSG_MASK); |
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) { |
||||
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; |
||||
tmp >>= HOST_SMC_RESP_SHIFT; |
||||
if (tmp != 0) |
||||
break; |
||||
udelay(1); |
||||
} |
||||
|
||||
tmp = RREG32(SMC_MSG) & HOST_SMC_RESP_MASK; |
||||
tmp >>= HOST_SMC_RESP_SHIFT; |
||||
|
||||
result = (PPSMC_Result)tmp; |
||||
return result; |
||||
} |
||||
|
||||
PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev) |
||||
{ |
||||
int i; |
||||
PPSMC_Result result = PPSMC_Result_OK; |
||||
|
||||
if (!rv770_is_smc_running(rdev)) |
||||
return result; |
||||
|
||||
for (i = 0; i < rdev->usec_timeout; i++) { |
||||
if (RREG32(SMC_IO) & SMC_STOP_MODE) |
||||
break; |
||||
udelay(1); |
||||
} |
||||
|
||||
return result; |
||||
} |
||||
|
||||
static void rv770_clear_smc_sram(struct radeon_device *rdev, u16 limit) |
||||
{ |
||||
u16 i; |
||||
|
||||
for (i = 0; i < limit; i += 4) { |
||||
rv770_set_smc_sram_address(rdev, i, limit); |
||||
WREG32(SMC_SRAM_DATA, 0); |
||||
} |
||||
} |
||||
|
||||
int rv770_load_smc_ucode(struct radeon_device *rdev, |
||||
u16 limit) |
||||
{ |
||||
int ret; |
||||
const u8 *int_vect; |
||||
u16 int_vect_start_address; |
||||
u16 int_vect_size; |
||||
const u8 *ucode_data; |
||||
u16 ucode_start_address; |
||||
u16 ucode_size; |
||||
|
||||
if (!rdev->smc_fw) |
||||
return -EINVAL; |
||||
|
||||
rv770_clear_smc_sram(rdev, limit); |
||||
|
||||
switch (rdev->family) { |
||||
case CHIP_RV770: |
||||
ucode_start_address = RV770_SMC_UCODE_START; |
||||
ucode_size = RV770_SMC_UCODE_SIZE; |
||||
int_vect = (const u8 *)&rv770_smc_int_vectors; |
||||
int_vect_start_address = RV770_SMC_INT_VECTOR_START; |
||||
int_vect_size = RV770_SMC_INT_VECTOR_SIZE; |
||||
break; |
||||
case CHIP_RV730: |
||||
ucode_start_address = RV730_SMC_UCODE_START; |
||||
ucode_size = RV730_SMC_UCODE_SIZE; |
||||
int_vect = (const u8 *)&rv730_smc_int_vectors; |
||||
int_vect_start_address = RV730_SMC_INT_VECTOR_START; |
||||
int_vect_size = RV730_SMC_INT_VECTOR_SIZE; |
||||
break; |
||||
case CHIP_RV710: |
||||
ucode_start_address = RV710_SMC_UCODE_START; |
||||
ucode_size = RV710_SMC_UCODE_SIZE; |
||||
int_vect = (const u8 *)&rv710_smc_int_vectors; |
||||
int_vect_start_address = RV710_SMC_INT_VECTOR_START; |
||||
int_vect_size = RV710_SMC_INT_VECTOR_SIZE; |
||||
break; |
||||
case CHIP_RV740: |
||||
ucode_start_address = RV740_SMC_UCODE_START; |
||||
ucode_size = RV740_SMC_UCODE_SIZE; |
||||
int_vect = (const u8 *)&rv740_smc_int_vectors; |
||||
int_vect_start_address = RV740_SMC_INT_VECTOR_START; |
||||
int_vect_size = RV740_SMC_INT_VECTOR_SIZE; |
||||
break; |
||||
default: |
||||
DRM_ERROR("unknown asic in smc ucode loader\n"); |
||||
BUG(); |
||||
} |
||||
|
||||
/* load the ucode */ |
||||
ucode_data = (const u8 *)rdev->smc_fw->data; |
||||
ret = rv770_copy_bytes_to_smc(rdev, ucode_start_address, |
||||
ucode_data, ucode_size, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
/* set up the int vectors */ |
||||
ret = rv770_program_interrupt_vectors(rdev, int_vect_start_address, |
||||
int_vect, int_vect_size); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rv770_read_smc_sram_dword(struct radeon_device *rdev, |
||||
u16 smc_address, u32 *value, u16 limit) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = rv770_set_smc_sram_address(rdev, smc_address, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
*value = RREG32(SMC_SRAM_DATA); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
int rv770_write_smc_sram_dword(struct radeon_device *rdev, |
||||
u16 smc_address, u32 value, u16 limit) |
||||
{ |
||||
int ret; |
||||
|
||||
ret = rv770_set_smc_sram_address(rdev, smc_address, limit); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
WREG32(SMC_SRAM_DATA, value); |
||||
|
||||
return 0; |
||||
} |
@ -0,0 +1,208 @@ |
||||
/*
|
||||
* Copyright 2011 Advanced Micro Devices, Inc. |
||||
* |
||||
* Permission is hereby granted, free of charge, to any person obtaining a |
||||
* copy of this software and associated documentation files (the "Software"), |
||||
* to deal in the Software without restriction, including without limitation |
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||||
* and/or sell copies of the Software, and to permit persons to whom the |
||||
* Software is furnished to do so, subject to the following conditions: |
||||
* |
||||
* The above copyright notice and this permission notice shall be included in |
||||
* all copies or substantial portions of the Software. |
||||
* |
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||||
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||||
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||||
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||||
* OTHER DEALINGS IN THE SOFTWARE. |
||||
* |
||||
*/ |
||||
#ifndef __RV770_SMC_H__ |
||||
#define __RV770_SMC_H__ |
||||
|
||||
#include "ppsmc.h" |
||||
|
||||
#pragma pack(push, 1) |
||||
|
||||
#define RV770_SMC_TABLE_ADDRESS 0xB000 |
||||
|
||||
#define RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE 3 |
||||
|
||||
struct RV770_SMC_SCLK_VALUE |
||||
{ |
||||
uint32_t vCG_SPLL_FUNC_CNTL; |
||||
uint32_t vCG_SPLL_FUNC_CNTL_2; |
||||
uint32_t vCG_SPLL_FUNC_CNTL_3; |
||||
uint32_t vCG_SPLL_SPREAD_SPECTRUM; |
||||
uint32_t vCG_SPLL_SPREAD_SPECTRUM_2; |
||||
uint32_t sclk_value; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_SCLK_VALUE RV770_SMC_SCLK_VALUE; |
||||
|
||||
struct RV770_SMC_MCLK_VALUE |
||||
{ |
||||
uint32_t vMPLL_AD_FUNC_CNTL; |
||||
uint32_t vMPLL_AD_FUNC_CNTL_2; |
||||
uint32_t vMPLL_DQ_FUNC_CNTL; |
||||
uint32_t vMPLL_DQ_FUNC_CNTL_2; |
||||
uint32_t vMCLK_PWRMGT_CNTL; |
||||
uint32_t vDLL_CNTL; |
||||
uint32_t vMPLL_SS; |
||||
uint32_t vMPLL_SS2; |
||||
uint32_t mclk_value; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_MCLK_VALUE RV770_SMC_MCLK_VALUE; |
||||
|
||||
|
||||
struct RV730_SMC_MCLK_VALUE |
||||
{ |
||||
uint32_t vMCLK_PWRMGT_CNTL; |
||||
uint32_t vDLL_CNTL; |
||||
uint32_t vMPLL_FUNC_CNTL; |
||||
uint32_t vMPLL_FUNC_CNTL2; |
||||
uint32_t vMPLL_FUNC_CNTL3; |
||||
uint32_t vMPLL_SS; |
||||
uint32_t vMPLL_SS2; |
||||
uint32_t mclk_value; |
||||
}; |
||||
|
||||
typedef struct RV730_SMC_MCLK_VALUE RV730_SMC_MCLK_VALUE; |
||||
|
||||
struct RV770_SMC_VOLTAGE_VALUE |
||||
{ |
||||
uint16_t value; |
||||
uint8_t index; |
||||
uint8_t padding; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_VOLTAGE_VALUE RV770_SMC_VOLTAGE_VALUE; |
||||
|
||||
union RV7XX_SMC_MCLK_VALUE |
||||
{ |
||||
RV770_SMC_MCLK_VALUE mclk770; |
||||
RV730_SMC_MCLK_VALUE mclk730; |
||||
}; |
||||
|
||||
typedef union RV7XX_SMC_MCLK_VALUE RV7XX_SMC_MCLK_VALUE, *LPRV7XX_SMC_MCLK_VALUE; |
||||
|
||||
struct RV770_SMC_HW_PERFORMANCE_LEVEL |
||||
{ |
||||
uint8_t arbValue; |
||||
union{ |
||||
uint8_t seqValue; |
||||
uint8_t ACIndex; |
||||
}; |
||||
uint8_t displayWatermark; |
||||
uint8_t gen2PCIE; |
||||
uint8_t gen2XSP; |
||||
uint8_t backbias; |
||||
uint8_t strobeMode; |
||||
uint8_t mcFlags; |
||||
uint32_t aT; |
||||
uint32_t bSP; |
||||
RV770_SMC_SCLK_VALUE sclk; |
||||
RV7XX_SMC_MCLK_VALUE mclk; |
||||
RV770_SMC_VOLTAGE_VALUE vddc; |
||||
RV770_SMC_VOLTAGE_VALUE mvdd; |
||||
RV770_SMC_VOLTAGE_VALUE vddci; |
||||
uint8_t reserved1; |
||||
uint8_t reserved2; |
||||
uint8_t stateFlags; |
||||
uint8_t padding; |
||||
}; |
||||
|
||||
#define SMC_STROBE_RATIO 0x0F |
||||
#define SMC_STROBE_ENABLE 0x10 |
||||
|
||||
#define SMC_MC_EDC_RD_FLAG 0x01 |
||||
#define SMC_MC_EDC_WR_FLAG 0x02 |
||||
#define SMC_MC_RTT_ENABLE 0x04 |
||||
#define SMC_MC_STUTTER_EN 0x08 |
||||
|
||||
typedef struct RV770_SMC_HW_PERFORMANCE_LEVEL RV770_SMC_HW_PERFORMANCE_LEVEL; |
||||
|
||||
struct RV770_SMC_SWSTATE |
||||
{ |
||||
uint8_t flags; |
||||
uint8_t padding1; |
||||
uint8_t padding2; |
||||
uint8_t padding3; |
||||
RV770_SMC_HW_PERFORMANCE_LEVEL levels[RV770_SMC_PERFORMANCE_LEVELS_PER_SWSTATE]; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_SWSTATE RV770_SMC_SWSTATE; |
||||
|
||||
#define RV770_SMC_VOLTAGEMASK_VDDC 0 |
||||
#define RV770_SMC_VOLTAGEMASK_MVDD 1 |
||||
#define RV770_SMC_VOLTAGEMASK_VDDCI 2 |
||||
#define RV770_SMC_VOLTAGEMASK_MAX 4 |
||||
|
||||
struct RV770_SMC_VOLTAGEMASKTABLE |
||||
{ |
||||
uint8_t highMask[RV770_SMC_VOLTAGEMASK_MAX]; |
||||
uint32_t lowMask[RV770_SMC_VOLTAGEMASK_MAX]; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_VOLTAGEMASKTABLE RV770_SMC_VOLTAGEMASKTABLE; |
||||
|
||||
#define MAX_NO_VREG_STEPS 32 |
||||
|
||||
struct RV770_SMC_STATETABLE |
||||
{ |
||||
uint8_t thermalProtectType; |
||||
uint8_t systemFlags; |
||||
uint8_t maxVDDCIndexInPPTable; |
||||
uint8_t extraFlags; |
||||
uint8_t highSMIO[MAX_NO_VREG_STEPS]; |
||||
uint32_t lowSMIO[MAX_NO_VREG_STEPS]; |
||||
RV770_SMC_VOLTAGEMASKTABLE voltageMaskTable; |
||||
RV770_SMC_SWSTATE initialState; |
||||
RV770_SMC_SWSTATE ACPIState; |
||||
RV770_SMC_SWSTATE driverState; |
||||
RV770_SMC_SWSTATE ULVState; |
||||
}; |
||||
|
||||
typedef struct RV770_SMC_STATETABLE RV770_SMC_STATETABLE; |
||||
|
||||
#define PPSMC_STATEFLAG_AUTO_PULSE_SKIP 0x01 |
||||
|
||||
#pragma pack(pop) |
||||
|
||||
#define RV770_SMC_SOFT_REGISTERS_START 0x104 |
||||
|
||||
#define RV770_SMC_SOFT_REGISTER_mclk_chg_timeout 0x0 |
||||
#define RV770_SMC_SOFT_REGISTER_baby_step_timer 0x8 |
||||
#define RV770_SMC_SOFT_REGISTER_delay_bbias 0xC |
||||
#define RV770_SMC_SOFT_REGISTER_delay_vreg 0x10 |
||||
#define RV770_SMC_SOFT_REGISTER_delay_acpi 0x2C |
||||
#define RV770_SMC_SOFT_REGISTER_seq_index 0x64 |
||||
#define RV770_SMC_SOFT_REGISTER_mvdd_chg_time 0x68 |
||||
#define RV770_SMC_SOFT_REGISTER_mclk_switch_lim 0x78 |
||||
#define RV770_SMC_SOFT_REGISTER_mc_block_delay 0x90 |
||||
#define RV770_SMC_SOFT_REGISTER_is_asic_lombok 0xA0 |
||||
|
||||
int rv770_set_smc_sram_address(struct radeon_device *rdev, |
||||
u16 smc_address, u16 limit); |
||||
int rv770_copy_bytes_to_smc(struct radeon_device *rdev, |
||||
u16 smc_start_address, const u8 *src, |
||||
u16 byte_count, u16 limit); |
||||
void rv770_start_smc(struct radeon_device *rdev); |
||||
void rv770_reset_smc(struct radeon_device *rdev); |
||||
void rv770_stop_smc_clock(struct radeon_device *rdev); |
||||
void rv770_start_smc_clock(struct radeon_device *rdev); |
||||
bool rv770_is_smc_running(struct radeon_device *rdev); |
||||
PPSMC_Result rv770_send_msg_to_smc(struct radeon_device *rdev, PPSMC_Msg msg); |
||||
PPSMC_Result rv770_wait_for_smc_inactive(struct radeon_device *rdev); |
||||
int rv770_read_smc_sram_dword(struct radeon_device *rdev, |
||||
u16 smc_address, u32 *value, u16 limit); |
||||
int rv770_write_smc_sram_dword(struct radeon_device *rdev, |
||||
u16 smc_address, u32 value, u16 limit); |
||||
int rv770_load_smc_ucode(struct radeon_device *rdev, |
||||
u16 limit); |
||||
|
||||
#endif |
Loading…
Reference in new issue