Looks like people wanted these merged via the omap tree as it's the only user for the GIC crossbar. -----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.15 (GNU/Linux) iQIcBAABAgAGBQJTE7tJAAoJEBvUPslcq6VzdnQP/i+SLcdTcG6osw8mSoiodK3n BC2/ByQBzI5Q2u3CrISqayPX7lpCP4XWABJ9eEYOC9S5CVda7SjW3nobH764HBre 7y5fRg2OV5kRZZbvS66akcuMys2iwS3ExTZfn6W1ZKgIckqd0t2Q/7ds3mrgVFwv NzI5qEgHjHyNW2dNaVqW+7RblXbyRi8A1VGZofVduBbS2bxq7GPUWNM6CaFYW7aK 8ioYo6sMATUztvqCI/JbNnIWUZV/pfgZXeBYuO5nWgxY/EVd+m2CBMaBKD2bP+Z7 gdzRGEpVqKMZzeo8E10vJML0cLVq53PfBnobEjXFFXgR2Lt63KOsgZov4iHmIIrH FAccTryFfcsD30yunygPLjyYYsOcQEgMGK4aSRiGfmKJS5fxKgIaeBcr8wL9x3ac k3oThe9c19O2jt+sLN0ZVrG7y59th3t4a+mZ9AMFIEjrFm7ExDZ+NOhyLfx7LKsM dKO+FD0sXsRgCdFZXgC/nmSgE9t3pqKotTrPthZY3rivZan0mspdIJzkaU7TEqSw EqThl55cqpexlUfB7YwxsfmJ7y1O2Bxk3ShGhxZ+Wwfhgm8QDeH8VEaACfmkSukq NaNAYdi2yEV8HydXgsd5XhBazGN2ju3fT+/gqFjOKqT8zJrJI7QkDiNH1QcOTTAb XbKBumhC3ClwyFNlfhvx =MLEE -----END PGP SIGNATURE----- Merge tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/drivers Merge OMAP crossbar support from Tony Lindgren: Add support for GIC crossbar that routes interrupts on newer omaps. Looks like people wanted these merged via the omap tree as it's the only user for the GIC crossbar. * tag 'omap-for-v3.15/crossbar-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: ARM: DRA: Enable Crossbar IP support for DRA7XX ARM: OMAP4+: Correct Wakeup-gen code to use physical irq number DRIVERS: IRQCHIP: CROSSBAR: Add support for Crossbar IP DRIVERS: IRQCHIP: IRQ-GIC: Add support for routable irqs Signed-off-by: Olof Johansson <olof@lixom.net>tirimbino
Olof Johansson
11 years ago
commit
63261d76c8
@ -0,0 +1,27 @@ |
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Some socs have a large number of interrupts requests to service |
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the needs of its many peripherals and subsystems. All of the |
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interrupt lines from the subsystems are not needed at the same |
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time, so they have to be muxed to the irq-controller appropriately. |
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In such places a interrupt controllers are preceded by an CROSSBAR |
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that provides flexibility in muxing the device requests to the controller |
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inputs. |
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|
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Required properties: |
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- compatible : Should be "ti,irq-crossbar" |
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- reg: Base address and the size of the crossbar registers. |
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- ti,max-irqs: Total number of irqs available at the interrupt controller. |
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- ti,reg-size: Size of a individual register in bytes. Every individual |
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register is assumed to be of same size. Valid sizes are 1, 2, 4. |
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- ti,irqs-reserved: List of the reserved irq lines that are not muxed using |
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crossbar. These interrupt lines are reserved in the soc, |
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so crossbar bar driver should not consider them as free |
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lines. |
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|
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Examples: |
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crossbar_mpu: @4a020000 { |
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compatible = "ti,irq-crossbar"; |
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reg = <0x4a002a48 0x130>; |
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ti,max-irqs = <160>; |
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ti,reg-size = <2>; |
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ti,irqs-reserved = <0 1 2 3 5 6 131 132 139 140>; |
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}; |
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@ -0,0 +1,208 @@ |
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/*
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* drivers/irqchip/irq-crossbar.c |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* Author: Sricharan R <r.sricharan@ti.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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*/ |
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#include <linux/err.h> |
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#include <linux/io.h> |
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#include <linux/of_address.h> |
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#include <linux/of_irq.h> |
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#include <linux/slab.h> |
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#include <linux/irqchip/arm-gic.h> |
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|
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#define IRQ_FREE -1 |
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#define GIC_IRQ_START 32 |
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|
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/*
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* @int_max: maximum number of supported interrupts |
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* @irq_map: array of interrupts to crossbar number mapping |
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* @crossbar_base: crossbar base address |
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* @register_offsets: offsets for each irq number |
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*/ |
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struct crossbar_device { |
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uint int_max; |
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uint *irq_map; |
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void __iomem *crossbar_base; |
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int *register_offsets; |
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void (*write) (int, int); |
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}; |
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static struct crossbar_device *cb; |
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static inline void crossbar_writel(int irq_no, int cb_no) |
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{ |
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writel(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); |
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} |
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|
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static inline void crossbar_writew(int irq_no, int cb_no) |
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{ |
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writew(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); |
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} |
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|
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static inline void crossbar_writeb(int irq_no, int cb_no) |
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{ |
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writeb(cb_no, cb->crossbar_base + cb->register_offsets[irq_no]); |
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} |
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static inline int allocate_free_irq(int cb_no) |
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{ |
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int i; |
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for (i = 0; i < cb->int_max; i++) { |
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if (cb->irq_map[i] == IRQ_FREE) { |
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cb->irq_map[i] = cb_no; |
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return i; |
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} |
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} |
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return -ENODEV; |
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} |
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static int crossbar_domain_map(struct irq_domain *d, unsigned int irq, |
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irq_hw_number_t hw) |
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{ |
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cb->write(hw - GIC_IRQ_START, cb->irq_map[hw - GIC_IRQ_START]); |
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return 0; |
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} |
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static void crossbar_domain_unmap(struct irq_domain *d, unsigned int irq) |
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{ |
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irq_hw_number_t hw = irq_get_irq_data(irq)->hwirq; |
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if (hw > GIC_IRQ_START) |
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cb->irq_map[hw - GIC_IRQ_START] = IRQ_FREE; |
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} |
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static int crossbar_domain_xlate(struct irq_domain *d, |
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struct device_node *controller, |
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const u32 *intspec, unsigned int intsize, |
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unsigned long *out_hwirq, |
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unsigned int *out_type) |
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{ |
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unsigned long ret; |
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ret = allocate_free_irq(intspec[1]); |
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if (IS_ERR_VALUE(ret)) |
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return ret; |
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*out_hwirq = ret + GIC_IRQ_START; |
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return 0; |
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} |
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const struct irq_domain_ops routable_irq_domain_ops = { |
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.map = crossbar_domain_map, |
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.unmap = crossbar_domain_unmap, |
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.xlate = crossbar_domain_xlate |
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}; |
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static int __init crossbar_of_init(struct device_node *node) |
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{ |
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int i, size, max, reserved = 0, entry; |
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const __be32 *irqsr; |
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cb = kzalloc(sizeof(struct cb_device *), GFP_KERNEL); |
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if (!cb) |
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return -ENOMEM; |
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cb->crossbar_base = of_iomap(node, 0); |
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if (!cb->crossbar_base) |
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goto err1; |
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of_property_read_u32(node, "ti,max-irqs", &max); |
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cb->irq_map = kzalloc(max * sizeof(int), GFP_KERNEL); |
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if (!cb->irq_map) |
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goto err2; |
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cb->int_max = max; |
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for (i = 0; i < max; i++) |
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cb->irq_map[i] = IRQ_FREE; |
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/* Get and mark reserved irqs */ |
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irqsr = of_get_property(node, "ti,irqs-reserved", &size); |
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if (irqsr) { |
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size /= sizeof(__be32); |
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for (i = 0; i < size; i++) { |
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of_property_read_u32_index(node, |
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"ti,irqs-reserved", |
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i, &entry); |
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if (entry > max) { |
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pr_err("Invalid reserved entry\n"); |
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goto err3; |
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} |
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cb->irq_map[entry] = 0; |
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} |
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} |
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cb->register_offsets = kzalloc(max * sizeof(int), GFP_KERNEL); |
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if (!cb->register_offsets) |
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goto err3; |
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of_property_read_u32(node, "ti,reg-size", &size); |
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switch (size) { |
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case 1: |
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cb->write = crossbar_writeb; |
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break; |
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case 2: |
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cb->write = crossbar_writew; |
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break; |
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case 4: |
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cb->write = crossbar_writel; |
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break; |
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default: |
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pr_err("Invalid reg-size property\n"); |
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goto err4; |
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break; |
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} |
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/*
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* Register offsets are not linear because of the |
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* reserved irqs. so find and store the offsets once. |
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*/ |
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for (i = 0; i < max; i++) { |
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if (!cb->irq_map[i]) |
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continue; |
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cb->register_offsets[i] = reserved; |
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reserved += size; |
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} |
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register_routable_domain_ops(&routable_irq_domain_ops); |
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return 0; |
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err4: |
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kfree(cb->register_offsets); |
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err3: |
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kfree(cb->irq_map); |
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err2: |
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iounmap(cb->crossbar_base); |
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err1: |
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kfree(cb); |
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return -ENOMEM; |
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} |
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static const struct of_device_id crossbar_match[] __initconst = { |
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{ .compatible = "ti,irq-crossbar" }, |
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{} |
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}; |
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int __init irqcrossbar_init(void) |
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{ |
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struct device_node *np; |
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np = of_find_matching_node(NULL, crossbar_match); |
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if (!np) |
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return -ENODEV; |
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crossbar_of_init(np); |
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return 0; |
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} |
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@ -0,0 +1,11 @@ |
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/*
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* drivers/irqchip/irq-crossbar.h |
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* |
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* Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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*/ |
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int irqcrossbar_init(void); |
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