@ -32,6 +32,9 @@
ppa_zero_params :
.word 0x0
ppa_por_params :
.word 1 , 0
/ *
* = = = = = = = = = = = = = = = = = = = = = = = = = = = = =
* = = CPU s u s p e n d f i n i s h e r = =
@ -132,6 +135,54 @@ skip_scu_gp_set:
mcrne p15 , 0 , r0 , c1 , c0 , 1
isb
dsb
# ifdef C O N F I G _ C A C H E _ L 2 X 0
/ *
* Clean a n d i n v a l i d a t e t h e L 2 c a c h e .
* Common c a c h e - l 2 x0 . c f u n c t i o n s c a n ' t b e u s e d h e r e s i n c e i t
* uses s p i n l o c k s . W e a r e o u t o f c o h e r e n c y h e r e w i t h d a t a c a c h e
* disabled. T h e s p i n l o c k i m p l e m e n t a t i o n u s e s e x c l u s i v e l o a d / s t o r e
* instruction w h i c h c a n f a i l w i t h o u t d a t a c a c h e b e i n g e n a b l e d .
* OMAP4 h a r d w a r e d o e s n ' t s u p p o r t e x c l u s i v e m o n i t o r w h i c h c a n
* overcome e x c l u s i v e a c c e s s i s s u e . B e c a u s e o f t h i s , C P U c a n
* lead t o d e a d l o c k .
* /
bl o m a p4 _ g e t _ s a r _ r a m _ b a s e
mov r8 , r0
mrc p15 , 0 , r5 , c0 , c0 , 5 @ Read MPIDR
ands r5 , r5 , #0x0f
ldreq r0 , [ r8 , #L 2 X 0 _ S A V E _ O F F S E T 0 ] @ Retrieve L2 state from SAR
ldrne r0 , [ r8 , #L 2 X 0 _ S A V E _ O F F S E T 1 ] @ memory.
cmp r0 , #3
bne d o _ W F I
# ifdef C O N F I G _ P L 3 1 0 _ E R R A T A _ 7 2 7 9 1 5
mov r0 , #0x03
mov r12 , #O M A P 4 _ M O N _ L 2 X 0 _ D B G _ C T R L _ I N D E X
DO_ S M C
# endif
bl o m a p4 _ g e t _ l 2 c a c h e _ b a s e
mov r2 , r0
ldr r0 , =0xffff
str r0 , [ r2 , #L 2 X 0 _ C L E A N _ I N V _ W A Y ]
wait :
ldr r0 , [ r2 , #L 2 X 0 _ C L E A N _ I N V _ W A Y ]
ldr r1 , =0xffff
ands r0 , r0 , r1
bne w a i t
# ifdef C O N F I G _ P L 3 1 0 _ E R R A T A _ 7 2 7 9 1 5
mov r0 , #0x00
mov r12 , #O M A P 4 _ M O N _ L 2 X 0 _ D B G _ C T R L _ I N D E X
DO_ S M C
# endif
l2x_sync :
bl o m a p4 _ g e t _ l 2 c a c h e _ b a s e
mov r2 , r0
mov r0 , #0x0
str r0 , [ r2 , #L 2 X 0 _ C A C H E _ S Y N C ]
sync :
ldr r0 , [ r2 , #L 2 X 0 _ C A C H E _ S Y N C ]
ands r0 , r0 , #0x1
bne s y n c
# endif
do_WFI :
bl o m a p _ d o _ w f i
@ -225,6 +276,50 @@ enable_smp_bit:
mcreq p15 , 0 , r0 , c1 , c0 , 1
isb
skip_ns_smp_enable :
# ifdef C O N F I G _ C A C H E _ L 2 X 0
/ *
* Restore t h e L 2 A U X C T R L a n d e n a b l e t h e L 2 c a c h e .
* OMAP4 _ M O N _ L 2 X 0 _ A U X C T R L _ I N D E X = P r o g r a m t h e L 2 X 0 A U X C T R L
* OMAP4 _ M O N _ L 2 X 0 _ C T R L _ I N D E X = E n a b l e t h e L 2 u s i n g L 2 X 0 C T R L
* register r0 c o n t a i n s v a l u e t o b e p r o g r a m m e d .
* L2 c a c h e i s a l r e a d y i n v a l i d a t e b y R O M c o d e a s p a r t
* of M P U S S O F F w a k e u p p a t h .
* /
ldr r2 , =OMAP44XX_L2CACHE_BASE
ldr r0 , [ r2 , #L 2 X 0 _ C T R L ]
and r0 , #0x0f
cmp r0 , #1
beq s k i p _ l 2 e n @ Skip if already enabled
ldr r3 , =OMAP44XX_SAR_RAM_BASE
ldr r1 , [ r3 , #O M A P _ T Y P E _ O F F S E T ]
cmp r1 , #0x1 @ Check for HS device
bne s e t _ g p _ p o r
ldr r0 , =OMAP4_PPA_L2_POR_INDEX
ldr r1 , =OMAP44XX_SAR_RAM_BASE
ldr r4 , [ r1 , #L 2 X 0 _ P R E F E T C H _ C T R L _ O F F S E T ]
adr r3 , p p a _ p o r _ p a r a m s
str r4 , [ r3 , #0x04 ]
mov r1 , #0x0 @ Process ID
mov r2 , #0x4 @ Flag
mov r6 , #0xff
mov r12 , #0x00 @ Secure Service ID
DO_ S M C
b s e t _ a u x _ c t r l
set_gp_por :
ldr r1 , =OMAP44XX_SAR_RAM_BASE
ldr r0 , [ r1 , #L 2 X 0 _ P R E F E T C H _ C T R L _ O F F S E T ]
ldr r12 , =OMAP4_MON_L2X0_PREFETCH_INDEX @ Setup L2 PREFETCH
DO_ S M C
set_aux_ctrl :
ldr r1 , =OMAP44XX_SAR_RAM_BASE
ldr r0 , [ r1 , #L 2 X 0 _ A U X C T R L _ O F F S E T ]
ldr r12 , =OMAP4_MON_L2X0_AUXCTRL_INDEX @ Setup L2 AUXCTRL
DO_ S M C
mov r0 , #0x1
ldr r12 , =OMAP4_MON_L2X0_CTRL_INDEX @ Enable L2 cache
DO_ S M C
skip_l2en :
# endif
b c p u _ r e s u m e @ Jump to generic resume
ENDPROC( o m a p4 _ c p u _ r e s u m e )
Santosh Shilimkar
14 years ago
committed by