The AC100 is a multifunction device with an audio codec subsystem and an RTC subsystem. These two subsystems share a common register space and host interface. Signed-off-by: Chen-Yu Tsai <wens@csie.org> Signed-off-by: Lee Jones <lee.jones@linaro.org>tirimbino
Chen-Yu Tsai
9 years ago
committed by
Lee Jones
parent
44fb25d031
commit
585083c539
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/*
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* MFD core driver for X-Powers' AC100 Audio Codec IC |
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* |
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* The AC100 is a highly integrated audio codec and RTC subsystem designed |
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* for mobile applications. It has 3 I2S/PCM interfaces, a 2 channel DAC, |
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* a 2 channel ADC with 5 inputs and a builtin mixer. The RTC subsystem has |
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* 3 clock outputs. |
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* |
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* The audio codec and RTC parts are completely separate, sharing only the |
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* host interface for access to its registers. |
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* |
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* Copyright (2016) Chen-Yu Tsai |
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* |
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* Author: Chen-Yu Tsai <wens@csie.org> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#include <linux/interrupt.h> |
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#include <linux/kernel.h> |
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#include <linux/mfd/core.h> |
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#include <linux/mfd/ac100.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/regmap.h> |
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#include <linux/sunxi-rsb.h> |
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static const struct regmap_range ac100_writeable_ranges[] = { |
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regmap_reg_range(AC100_CHIP_AUDIO_RST, AC100_I2S_SR_CTRL), |
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regmap_reg_range(AC100_I2S1_CLK_CTRL, AC100_I2S1_MXR_GAIN), |
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regmap_reg_range(AC100_I2S2_CLK_CTRL, AC100_I2S2_MXR_GAIN), |
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regmap_reg_range(AC100_I2S3_CLK_CTRL, AC100_I2S3_SIG_PATH_CTRL), |
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regmap_reg_range(AC100_ADC_DIG_CTRL, AC100_ADC_VOL_CTRL), |
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regmap_reg_range(AC100_HMIC_CTRL1, AC100_HMIC_STATUS), |
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regmap_reg_range(AC100_DAC_DIG_CTRL, AC100_DAC_MXR_GAIN), |
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regmap_reg_range(AC100_ADC_APC_CTRL, AC100_LINEOUT_CTRL), |
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regmap_reg_range(AC100_ADC_DAP_L_CTRL, AC100_ADC_DAP_OPT), |
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regmap_reg_range(AC100_DAC_DAP_CTRL, AC100_DAC_DAP_OPT), |
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regmap_reg_range(AC100_ADC_DAP_ENA, AC100_DAC_DAP_ENA), |
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regmap_reg_range(AC100_SRC1_CTRL1, AC100_SRC1_CTRL2), |
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regmap_reg_range(AC100_SRC2_CTRL1, AC100_SRC2_CTRL2), |
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regmap_reg_range(AC100_CLK32K_ANALOG_CTRL, AC100_CLKOUT_CTRL3), |
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regmap_reg_range(AC100_RTC_RST, AC100_RTC_UPD), |
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regmap_reg_range(AC100_ALM_INT_ENA, AC100_ALM_INT_STA), |
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regmap_reg_range(AC100_ALM_SEC, AC100_RTC_GP(15)), |
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}; |
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static const struct regmap_range ac100_volatile_ranges[] = { |
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regmap_reg_range(AC100_CHIP_AUDIO_RST, AC100_PLL_CTRL2), |
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regmap_reg_range(AC100_HMIC_STATUS, AC100_HMIC_STATUS), |
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regmap_reg_range(AC100_ADC_DAP_L_STA, AC100_ADC_DAP_L_STA), |
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regmap_reg_range(AC100_SRC1_CTRL1, AC100_SRC1_CTRL1), |
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regmap_reg_range(AC100_SRC1_CTRL3, AC100_SRC2_CTRL1), |
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regmap_reg_range(AC100_SRC2_CTRL3, AC100_SRC2_CTRL4), |
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regmap_reg_range(AC100_RTC_RST, AC100_RTC_RST), |
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regmap_reg_range(AC100_RTC_SEC, AC100_ALM_INT_STA), |
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regmap_reg_range(AC100_ALM_SEC, AC100_ALM_UPD), |
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}; |
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static const struct regmap_access_table ac100_writeable_table = { |
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.yes_ranges = ac100_writeable_ranges, |
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.n_yes_ranges = ARRAY_SIZE(ac100_writeable_ranges), |
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}; |
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static const struct regmap_access_table ac100_volatile_table = { |
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.yes_ranges = ac100_volatile_ranges, |
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.n_yes_ranges = ARRAY_SIZE(ac100_volatile_ranges), |
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}; |
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static const struct regmap_config ac100_regmap_config = { |
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.reg_bits = 8, |
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.val_bits = 16, |
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.wr_table = &ac100_writeable_table, |
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.volatile_table = &ac100_volatile_table, |
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.max_register = AC100_RTC_GP(15), |
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.cache_type = REGCACHE_RBTREE, |
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}; |
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static struct mfd_cell ac100_cells[] = { |
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{ |
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.name = "ac100-codec", |
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.of_compatible = "x-powers,ac100-codec", |
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}, { |
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.name = "ac100-rtc", |
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.of_compatible = "x-powers,ac100-rtc", |
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}, |
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}; |
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static int ac100_rsb_probe(struct sunxi_rsb_device *rdev) |
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{ |
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struct ac100_dev *ac100; |
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int ret; |
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ac100 = devm_kzalloc(&rdev->dev, sizeof(*ac100), GFP_KERNEL); |
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if (!ac100) |
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return -ENOMEM; |
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ac100->dev = &rdev->dev; |
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sunxi_rsb_device_set_drvdata(rdev, ac100); |
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ac100->regmap = devm_regmap_init_sunxi_rsb(rdev, &ac100_regmap_config); |
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if (IS_ERR(ac100->regmap)) { |
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ret = PTR_ERR(ac100->regmap); |
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dev_err(ac100->dev, "regmap init failed: %d\n", ret); |
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return ret; |
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} |
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ret = devm_mfd_add_devices(ac100->dev, PLATFORM_DEVID_NONE, ac100_cells, |
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ARRAY_SIZE(ac100_cells), NULL, 0, NULL); |
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if (ret) { |
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dev_err(ac100->dev, "failed to add MFD devices: %d\n", ret); |
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return ret; |
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} |
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return 0; |
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} |
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static const struct of_device_id ac100_of_match[] = { |
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{ .compatible = "x-powers,ac100" }, |
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{ }, |
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}; |
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MODULE_DEVICE_TABLE(of, ac100_of_match); |
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static struct sunxi_rsb_driver ac100_rsb_driver = { |
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.driver = { |
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.name = "ac100", |
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.of_match_table = of_match_ptr(ac100_of_match), |
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}, |
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.probe = ac100_rsb_probe, |
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}; |
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module_sunxi_rsb_driver(ac100_rsb_driver); |
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MODULE_DESCRIPTION("Audio codec MFD core driver for AC100"); |
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MODULE_AUTHOR("Chen-Yu Tsai <wens@csie.org>"); |
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MODULE_LICENSE("GPL v2"); |
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@ -0,0 +1,178 @@ |
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/*
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* Functions and registers to access AC100 codec / RTC combo IC. |
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* |
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* Copyright (C) 2016 Chen-Yu Tsai |
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* |
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* Chen-Yu Tsai <wens@csie.org> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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#ifndef __LINUX_MFD_AC100_H |
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#define __LINUX_MFD_AC100_H |
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#include <linux/regmap.h> |
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struct ac100_dev { |
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struct device *dev; |
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struct regmap *regmap; |
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}; |
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/* Audio codec related registers */ |
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#define AC100_CHIP_AUDIO_RST 0x00 |
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#define AC100_PLL_CTRL1 0x01 |
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#define AC100_PLL_CTRL2 0x02 |
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#define AC100_SYSCLK_CTRL 0x03 |
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#define AC100_MOD_CLK_ENA 0x04 |
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#define AC100_MOD_RST_CTRL 0x05 |
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#define AC100_I2S_SR_CTRL 0x06 |
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/* I2S1 interface */ |
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#define AC100_I2S1_CLK_CTRL 0x10 |
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#define AC100_I2S1_SND_OUT_CTRL 0x11 |
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#define AC100_I2S1_SND_IN_CTRL 0x12 |
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#define AC100_I2S1_MXR_SRC 0x13 |
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#define AC100_I2S1_VOL_CTRL1 0x14 |
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#define AC100_I2S1_VOL_CTRL2 0x15 |
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#define AC100_I2S1_VOL_CTRL3 0x16 |
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#define AC100_I2S1_VOL_CTRL4 0x17 |
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#define AC100_I2S1_MXR_GAIN 0x18 |
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/* I2S2 interface */ |
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#define AC100_I2S2_CLK_CTRL 0x20 |
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#define AC100_I2S2_SND_OUT_CTRL 0x21 |
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#define AC100_I2S2_SND_IN_CTRL 0x22 |
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#define AC100_I2S2_MXR_SRC 0x23 |
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#define AC100_I2S2_VOL_CTRL1 0x24 |
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#define AC100_I2S2_VOL_CTRL2 0x25 |
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#define AC100_I2S2_VOL_CTRL3 0x26 |
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#define AC100_I2S2_VOL_CTRL4 0x27 |
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#define AC100_I2S2_MXR_GAIN 0x28 |
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/* I2S3 interface */ |
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#define AC100_I2S3_CLK_CTRL 0x30 |
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#define AC100_I2S3_SND_OUT_CTRL 0x31 |
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#define AC100_I2S3_SND_IN_CTRL 0x32 |
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#define AC100_I2S3_SIG_PATH_CTRL 0x33 |
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/* ADC digital controls */ |
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#define AC100_ADC_DIG_CTRL 0x40 |
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#define AC100_ADC_VOL_CTRL 0x41 |
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/* HMIC plug sensing / key detection */ |
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#define AC100_HMIC_CTRL1 0x44 |
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#define AC100_HMIC_CTRL2 0x45 |
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#define AC100_HMIC_STATUS 0x46 |
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/* DAC digital controls */ |
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#define AC100_DAC_DIG_CTRL 0x48 |
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#define AC100_DAC_VOL_CTRL 0x49 |
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#define AC100_DAC_MXR_SRC 0x4c |
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#define AC100_DAC_MXR_GAIN 0x4d |
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/* Analog controls */ |
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#define AC100_ADC_APC_CTRL 0x50 |
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#define AC100_ADC_SRC 0x51 |
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#define AC100_ADC_SRC_BST_CTRL 0x52 |
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#define AC100_OUT_MXR_DAC_A_CTRL 0x53 |
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#define AC100_OUT_MXR_SRC 0x54 |
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#define AC100_OUT_MXR_SRC_BST 0x55 |
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#define AC100_HPOUT_CTRL 0x56 |
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#define AC100_ERPOUT_CTRL 0x57 |
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#define AC100_SPKOUT_CTRL 0x58 |
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#define AC100_LINEOUT_CTRL 0x59 |
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/* ADC digital audio processing (high pass filter & auto gain control */ |
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#define AC100_ADC_DAP_L_STA 0x80 |
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#define AC100_ADC_DAP_R_STA 0x81 |
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#define AC100_ADC_DAP_L_CTRL 0x82 |
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#define AC100_ADC_DAP_R_CTRL 0x83 |
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#define AC100_ADC_DAP_L_T_L 0x84 /* Left Target Level */ |
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#define AC100_ADC_DAP_R_T_L 0x85 /* Right Target Level */ |
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#define AC100_ADC_DAP_L_H_A_C 0x86 /* Left High Avg. Coef */ |
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#define AC100_ADC_DAP_L_L_A_C 0x87 /* Left Low Avg. Coef */ |
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#define AC100_ADC_DAP_R_H_A_C 0x88 /* Right High Avg. Coef */ |
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#define AC100_ADC_DAP_R_L_A_C 0x89 /* Right Low Avg. Coef */ |
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#define AC100_ADC_DAP_L_D_T 0x8a /* Left Decay Time */ |
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#define AC100_ADC_DAP_L_A_T 0x8b /* Left Attack Time */ |
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#define AC100_ADC_DAP_R_D_T 0x8c /* Right Decay Time */ |
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#define AC100_ADC_DAP_R_A_T 0x8d /* Right Attack Time */ |
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#define AC100_ADC_DAP_N_TH 0x8e /* Noise Threshold */ |
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#define AC100_ADC_DAP_L_H_N_A_C 0x8f /* Left High Noise Avg. Coef */ |
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#define AC100_ADC_DAP_L_L_N_A_C 0x90 /* Left Low Noise Avg. Coef */ |
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#define AC100_ADC_DAP_R_H_N_A_C 0x91 /* Right High Noise Avg. Coef */ |
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#define AC100_ADC_DAP_R_L_N_A_C 0x92 /* Right Low Noise Avg. Coef */ |
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#define AC100_ADC_DAP_H_HPF_C 0x93 /* High High-Pass-Filter Coef */ |
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#define AC100_ADC_DAP_L_HPF_C 0x94 /* Low High-Pass-Filter Coef */ |
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#define AC100_ADC_DAP_OPT 0x95 /* AGC Optimum */ |
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/* DAC digital audio processing (high pass filter & dynamic range control) */ |
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#define AC100_DAC_DAP_CTRL 0xa0 |
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#define AC100_DAC_DAP_H_HPF_C 0xa1 /* High High-Pass-Filter Coef */ |
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#define AC100_DAC_DAP_L_HPF_C 0xa2 /* Low High-Pass-Filter Coef */ |
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#define AC100_DAC_DAP_L_H_E_A_C 0xa3 /* Left High Energy Avg Coef */ |
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#define AC100_DAC_DAP_L_L_E_A_C 0xa4 /* Left Low Energy Avg Coef */ |
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#define AC100_DAC_DAP_R_H_E_A_C 0xa5 /* Right High Energy Avg Coef */ |
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#define AC100_DAC_DAP_R_L_E_A_C 0xa6 /* Right Low Energy Avg Coef */ |
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#define AC100_DAC_DAP_H_G_D_T_C 0xa7 /* High Gain Delay Time Coef */ |
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#define AC100_DAC_DAP_L_G_D_T_C 0xa8 /* Low Gain Delay Time Coef */ |
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#define AC100_DAC_DAP_H_G_A_T_C 0xa9 /* High Gain Attack Time Coef */ |
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#define AC100_DAC_DAP_L_G_A_T_C 0xaa /* Low Gain Attack Time Coef */ |
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#define AC100_DAC_DAP_H_E_TH 0xab /* High Energy Threshold */ |
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#define AC100_DAC_DAP_L_E_TH 0xac /* Low Energy Threshold */ |
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#define AC100_DAC_DAP_H_G_K 0xad /* High Gain K parameter */ |
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#define AC100_DAC_DAP_L_G_K 0xae /* Low Gain K parameter */ |
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#define AC100_DAC_DAP_H_G_OFF 0xaf /* High Gain offset */ |
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#define AC100_DAC_DAP_L_G_OFF 0xb0 /* Low Gain offset */ |
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#define AC100_DAC_DAP_OPT 0xb1 /* DRC optimum */ |
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/* Digital audio processing enable */ |
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#define AC100_ADC_DAP_ENA 0xb4 |
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#define AC100_DAC_DAP_ENA 0xb5 |
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/* SRC control */ |
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#define AC100_SRC1_CTRL1 0xb8 |
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#define AC100_SRC1_CTRL2 0xb9 |
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#define AC100_SRC1_CTRL3 0xba |
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#define AC100_SRC1_CTRL4 0xbb |
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#define AC100_SRC2_CTRL1 0xbc |
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#define AC100_SRC2_CTRL2 0xbd |
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#define AC100_SRC2_CTRL3 0xbe |
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#define AC100_SRC2_CTRL4 0xbf |
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/* RTC clk control */ |
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#define AC100_CLK32K_ANALOG_CTRL 0xc0 |
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#define AC100_CLKOUT_CTRL1 0xc1 |
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#define AC100_CLKOUT_CTRL2 0xc2 |
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#define AC100_CLKOUT_CTRL3 0xc3 |
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/* RTC module */ |
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#define AC100_RTC_RST 0xc6 |
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#define AC100_RTC_CTRL 0xc7 |
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#define AC100_RTC_SEC 0xc8 /* second */ |
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#define AC100_RTC_MIN 0xc9 /* minute */ |
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#define AC100_RTC_HOU 0xca /* hour */ |
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#define AC100_RTC_WEE 0xcb /* weekday */ |
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#define AC100_RTC_DAY 0xcc /* day */ |
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#define AC100_RTC_MON 0xcd /* month */ |
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#define AC100_RTC_YEA 0xce /* year */ |
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#define AC100_RTC_UPD 0xcf /* update trigger */ |
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/* RTC alarm */ |
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#define AC100_ALM_INT_ENA 0xd0 |
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#define AC100_ALM_INT_STA 0xd1 |
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#define AC100_ALM_SEC 0xd8 |
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#define AC100_ALM_MIN 0xd9 |
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#define AC100_ALM_HOU 0xda |
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#define AC100_ALM_WEE 0xdb |
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#define AC100_ALM_DAY 0xdc |
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#define AC100_ALM_MON 0xdd |
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#define AC100_ALM_YEA 0xde |
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#define AC100_ALM_UPD 0xdf |
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/* RTC general purpose register 0 ~ 15 */ |
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#define AC100_RTC_GP(x) (0xe0 + (x)) |
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#endif /* __LINUX_MFD_AC100_H */ |
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