@ -156,19 +156,19 @@ static int i82443bxgx_edacmc_process_error_info(struct mem_ctl_info *mci,
if ( info - > eap & I82443BXGX_EAP_OFFSET_SBE ) {
error_found = 1 ;
if ( handle_errors )
edac_mc_handle_ce ( mci , page , pageoffset ,
/* 440BX/GX don't make syndrome information
* available */
0 , edac_mc_find_csrow_by_page ( mci , page ) , 0 ,
mci - > ctl_name ) ;
edac_mc_handle_error ( HW_EVENT_ERR_CORRECTED , mci ,
page , pageoffset , 0 ,
edac_mc_find_csrow_by_page ( mci , page ) ,
0 , - 1 , mci - > ctl_name , " " , NULL ) ;
}
if ( info - > eap & I82443BXGX_EAP_OFFSET_MBE ) {
error_found = 1 ;
if ( handle_errors )
edac_mc_handle_ue ( mci , page , pageoffset ,
edac_mc_find_csrow_by_page ( mci , page ) ,
mci - > ctl_name ) ;
edac_mc_handle_error ( HW_EVENT_ERR_UNCORRECTED , mci ,
page , pageoffset , 0 ,
edac_mc_find_csrow_by_page ( mci , page ) ,
0 , - 1 , mci - > ctl_name , " " , NULL ) ;
}
return error_found ;
@ -235,6 +235,7 @@ static void i82443bxgx_init_csrows(struct mem_ctl_info *mci,
static int i82443bxgx_edacmc_probe1 ( struct pci_dev * pdev , int dev_idx )
{
struct mem_ctl_info * mci ;
struct edac_mc_layer layers [ 2 ] ;
u8 dramc ;
u32 nbxcfg , ecc_mode ;
enum mem_type mtype ;
@ -248,8 +249,13 @@ static int i82443bxgx_edacmc_probe1(struct pci_dev *pdev, int dev_idx)
if ( pci_read_config_dword ( pdev , I82443BXGX_NBXCFG , & nbxcfg ) )
return - EIO ;
mci = edac_mc_alloc ( 0 , I82443BXGX_NR_CSROWS , I82443BXGX_NR_CHANS , 0 ) ;
layers [ 0 ] . type = EDAC_MC_LAYER_CHIP_SELECT ;
layers [ 0 ] . size = I82443BXGX_NR_CSROWS ;
layers [ 0 ] . is_virt_csrow = true ;
layers [ 1 ] . type = EDAC_MC_LAYER_CHANNEL ;
layers [ 1 ] . size = I82443BXGX_NR_CHANS ;
layers [ 1 ] . is_virt_csrow = false ;
mci = new_edac_mc_alloc ( 0 , ARRAY_SIZE ( layers ) , layers , 0 ) ;
if ( mci = = NULL )
return - ENOMEM ;