Mike Turquette
11 years ago
commit
3f6eec9969
@ -0,0 +1,96 @@ |
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Device Tree Clock bindings for ATL (Audio Tracking Logic) of DRA7 SoC. |
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|
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The ATL IP is used to generate clock to be used to synchronize baseband and |
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audio codec. A single ATL IP provides four ATL clock instances sharing the same |
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functional clock but can be configured to provide different clocks. |
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ATL can maintain a clock averages to some desired frequency based on the bws/aws |
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signals - can compensate the drift between the two ws signal. |
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|
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In order to provide the support for ATL and it's output clocks (which can be used |
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internally within the SoC or external components) two sets of bindings is needed: |
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|
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Clock tree binding: |
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This binding uses the common clock binding[1]. |
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To be able to integrate the ATL clocks with DT clock tree. |
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Provides ccf level representation of the ATL clocks to be used by drivers. |
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Since the clock instances are part of a single IP this binding is used as a node |
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for the DT clock tree, the IP driver is needed to handle the actual configuration |
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of the IP. |
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|
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[1] Documentation/devicetree/bindings/clock/clock-bindings.txt |
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|
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Required properties: |
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- compatible : shall be "ti,dra7-atl-clock" |
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- #clock-cells : from common clock binding; shall be set to 0. |
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- clocks : link phandles to functional clock of ATL |
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|
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Binding for the IP driver: |
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This binding is used to configure the IP driver which is going to handle the |
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configuration of the IP for the ATL clock instances. |
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|
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Required properties: |
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- compatible : shall be "ti,dra7-atl" |
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- reg : base address for the ATL IP |
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- ti,provided-clocks : List of phandles to the clocks associated with the ATL |
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- clocks : link phandles to functional clock of ATL |
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- clock-names : Shall be set to "fck" |
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- ti,hwmods : Shall be set to "atl" |
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|
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Optional properties: |
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Configuration of ATL instances: |
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- atl{0/1/2/3} { |
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- bws : Baseband word select signal selection |
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- aws : Audio word select signal selection |
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}; |
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|
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For valid word select signals, see the dt-bindings/clk/ti-dra7-atl.h include |
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file. |
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|
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Examples: |
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/* clock bindings for atl provided clocks */ |
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atl_clkin0_ck: atl_clkin0_ck { |
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#clock-cells = <0>; |
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compatible = "ti,dra7-atl-clock"; |
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clocks = <&atl_gfclk_mux>; |
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}; |
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atl_clkin1_ck: atl_clkin1_ck { |
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#clock-cells = <0>; |
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compatible = "ti,dra7-atl-clock"; |
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clocks = <&atl_gfclk_mux>; |
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}; |
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atl_clkin2_ck: atl_clkin2_ck { |
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#clock-cells = <0>; |
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compatible = "ti,dra7-atl-clock"; |
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clocks = <&atl_gfclk_mux>; |
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}; |
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atl_clkin3_ck: atl_clkin3_ck { |
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#clock-cells = <0>; |
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compatible = "ti,dra7-atl-clock"; |
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clocks = <&atl_gfclk_mux>; |
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}; |
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|
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/* binding for the IP */ |
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atl: atl@4843c000 { |
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compatible = "ti,dra7-atl"; |
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reg = <0x4843c000 0x3ff>; |
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ti,hwmods = "atl"; |
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ti,provided-clocks = <&atl_clkin0_ck>, <&atl_clkin1_ck>, |
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<&atl_clkin2_ck>, <&atl_clkin3_ck>; |
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clocks = <&atl_gfclk_mux>; |
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clock-names = "fck"; |
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status = "disabled"; |
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}; |
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#include <dt-bindings/clk/ti-dra7-atl.h> |
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&atl { |
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status = "okay"; |
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atl2 { |
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bws = <DRA7_ATL_WS_MCASP2_FSX>; |
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aws = <DRA7_ATL_WS_MCASP3_FSX>; |
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}; |
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}; |
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@ -0,0 +1,256 @@ |
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/*
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* OMAP2 Clock init |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc |
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* Tero Kristo (t-kristo@ti.com) |
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* |
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* This program is free software; you can redistribute it and/or |
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* modify it under the terms of the GNU General Public License as |
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* published by the Free Software Foundation version 2. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
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* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <linux/kernel.h> |
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#include <linux/list.h> |
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#include <linux/clk-provider.h> |
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#include <linux/clk/ti.h> |
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|
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static struct ti_dt_clk omap2xxx_clks[] = { |
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DT_CLK(NULL, "func_32k_ck", "func_32k_ck"), |
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DT_CLK(NULL, "secure_32k_ck", "secure_32k_ck"), |
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DT_CLK(NULL, "virt_12m_ck", "virt_12m_ck"), |
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DT_CLK(NULL, "virt_13m_ck", "virt_13m_ck"), |
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DT_CLK(NULL, "virt_19200000_ck", "virt_19200000_ck"), |
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DT_CLK(NULL, "virt_26m_ck", "virt_26m_ck"), |
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DT_CLK(NULL, "aplls_clkin_ck", "aplls_clkin_ck"), |
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DT_CLK(NULL, "aplls_clkin_x2_ck", "aplls_clkin_x2_ck"), |
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DT_CLK(NULL, "osc_ck", "osc_ck"), |
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DT_CLK(NULL, "sys_ck", "sys_ck"), |
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DT_CLK(NULL, "alt_ck", "alt_ck"), |
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DT_CLK(NULL, "mcbsp_clks", "mcbsp_clks"), |
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DT_CLK(NULL, "dpll_ck", "dpll_ck"), |
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DT_CLK(NULL, "apll96_ck", "apll96_ck"), |
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DT_CLK(NULL, "apll54_ck", "apll54_ck"), |
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DT_CLK(NULL, "func_54m_ck", "func_54m_ck"), |
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DT_CLK(NULL, "core_ck", "core_ck"), |
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DT_CLK(NULL, "func_96m_ck", "func_96m_ck"), |
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DT_CLK(NULL, "func_48m_ck", "func_48m_ck"), |
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DT_CLK(NULL, "func_12m_ck", "func_12m_ck"), |
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DT_CLK(NULL, "sys_clkout_src", "sys_clkout_src"), |
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DT_CLK(NULL, "sys_clkout", "sys_clkout"), |
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DT_CLK(NULL, "emul_ck", "emul_ck"), |
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DT_CLK(NULL, "mpu_ck", "mpu_ck"), |
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DT_CLK(NULL, "dsp_fck", "dsp_fck"), |
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DT_CLK(NULL, "gfx_3d_fck", "gfx_3d_fck"), |
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DT_CLK(NULL, "gfx_2d_fck", "gfx_2d_fck"), |
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DT_CLK(NULL, "gfx_ick", "gfx_ick"), |
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DT_CLK("omapdss_dss", "ick", "dss_ick"), |
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DT_CLK(NULL, "dss_ick", "dss_ick"), |
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DT_CLK(NULL, "dss1_fck", "dss1_fck"), |
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DT_CLK(NULL, "dss2_fck", "dss2_fck"), |
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DT_CLK(NULL, "dss_54m_fck", "dss_54m_fck"), |
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DT_CLK(NULL, "core_l3_ck", "core_l3_ck"), |
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DT_CLK(NULL, "ssi_fck", "ssi_ssr_sst_fck"), |
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DT_CLK(NULL, "usb_l4_ick", "usb_l4_ick"), |
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DT_CLK(NULL, "l4_ck", "l4_ck"), |
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DT_CLK(NULL, "ssi_l4_ick", "ssi_l4_ick"), |
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DT_CLK(NULL, "gpt1_ick", "gpt1_ick"), |
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DT_CLK(NULL, "gpt1_fck", "gpt1_fck"), |
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DT_CLK(NULL, "gpt2_ick", "gpt2_ick"), |
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DT_CLK(NULL, "gpt2_fck", "gpt2_fck"), |
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DT_CLK(NULL, "gpt3_ick", "gpt3_ick"), |
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DT_CLK(NULL, "gpt3_fck", "gpt3_fck"), |
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DT_CLK(NULL, "gpt4_ick", "gpt4_ick"), |
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DT_CLK(NULL, "gpt4_fck", "gpt4_fck"), |
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DT_CLK(NULL, "gpt5_ick", "gpt5_ick"), |
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DT_CLK(NULL, "gpt5_fck", "gpt5_fck"), |
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DT_CLK(NULL, "gpt6_ick", "gpt6_ick"), |
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DT_CLK(NULL, "gpt6_fck", "gpt6_fck"), |
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DT_CLK(NULL, "gpt7_ick", "gpt7_ick"), |
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DT_CLK(NULL, "gpt7_fck", "gpt7_fck"), |
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DT_CLK(NULL, "gpt8_ick", "gpt8_ick"), |
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DT_CLK(NULL, "gpt8_fck", "gpt8_fck"), |
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DT_CLK(NULL, "gpt9_ick", "gpt9_ick"), |
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DT_CLK(NULL, "gpt9_fck", "gpt9_fck"), |
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DT_CLK(NULL, "gpt10_ick", "gpt10_ick"), |
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DT_CLK(NULL, "gpt10_fck", "gpt10_fck"), |
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DT_CLK(NULL, "gpt11_ick", "gpt11_ick"), |
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DT_CLK(NULL, "gpt11_fck", "gpt11_fck"), |
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DT_CLK(NULL, "gpt12_ick", "gpt12_ick"), |
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DT_CLK(NULL, "gpt12_fck", "gpt12_fck"), |
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DT_CLK("omap-mcbsp.1", "ick", "mcbsp1_ick"), |
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DT_CLK(NULL, "mcbsp1_ick", "mcbsp1_ick"), |
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DT_CLK(NULL, "mcbsp1_fck", "mcbsp1_fck"), |
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DT_CLK("omap-mcbsp.2", "ick", "mcbsp2_ick"), |
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DT_CLK(NULL, "mcbsp2_ick", "mcbsp2_ick"), |
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DT_CLK(NULL, "mcbsp2_fck", "mcbsp2_fck"), |
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DT_CLK("omap2_mcspi.1", "ick", "mcspi1_ick"), |
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DT_CLK(NULL, "mcspi1_ick", "mcspi1_ick"), |
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DT_CLK(NULL, "mcspi1_fck", "mcspi1_fck"), |
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DT_CLK("omap2_mcspi.2", "ick", "mcspi2_ick"), |
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DT_CLK(NULL, "mcspi2_ick", "mcspi2_ick"), |
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DT_CLK(NULL, "mcspi2_fck", "mcspi2_fck"), |
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DT_CLK(NULL, "uart1_ick", "uart1_ick"), |
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DT_CLK(NULL, "uart1_fck", "uart1_fck"), |
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DT_CLK(NULL, "uart2_ick", "uart2_ick"), |
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DT_CLK(NULL, "uart2_fck", "uart2_fck"), |
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DT_CLK(NULL, "uart3_ick", "uart3_ick"), |
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DT_CLK(NULL, "uart3_fck", "uart3_fck"), |
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DT_CLK(NULL, "gpios_ick", "gpios_ick"), |
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DT_CLK(NULL, "gpios_fck", "gpios_fck"), |
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DT_CLK("omap_wdt", "ick", "mpu_wdt_ick"), |
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DT_CLK(NULL, "mpu_wdt_ick", "mpu_wdt_ick"), |
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DT_CLK(NULL, "mpu_wdt_fck", "mpu_wdt_fck"), |
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DT_CLK(NULL, "sync_32k_ick", "sync_32k_ick"), |
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DT_CLK(NULL, "wdt1_ick", "wdt1_ick"), |
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DT_CLK(NULL, "omapctrl_ick", "omapctrl_ick"), |
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DT_CLK("omap24xxcam", "fck", "cam_fck"), |
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DT_CLK(NULL, "cam_fck", "cam_fck"), |
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DT_CLK("omap24xxcam", "ick", "cam_ick"), |
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DT_CLK(NULL, "cam_ick", "cam_ick"), |
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DT_CLK(NULL, "mailboxes_ick", "mailboxes_ick"), |
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DT_CLK(NULL, "wdt4_ick", "wdt4_ick"), |
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DT_CLK(NULL, "wdt4_fck", "wdt4_fck"), |
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DT_CLK(NULL, "mspro_ick", "mspro_ick"), |
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DT_CLK(NULL, "mspro_fck", "mspro_fck"), |
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DT_CLK(NULL, "fac_ick", "fac_ick"), |
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DT_CLK(NULL, "fac_fck", "fac_fck"), |
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DT_CLK("omap_hdq.0", "ick", "hdq_ick"), |
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DT_CLK(NULL, "hdq_ick", "hdq_ick"), |
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DT_CLK("omap_hdq.0", "fck", "hdq_fck"), |
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DT_CLK(NULL, "hdq_fck", "hdq_fck"), |
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DT_CLK("omap_i2c.1", "ick", "i2c1_ick"), |
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DT_CLK(NULL, "i2c1_ick", "i2c1_ick"), |
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DT_CLK("omap_i2c.2", "ick", "i2c2_ick"), |
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DT_CLK(NULL, "i2c2_ick", "i2c2_ick"), |
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DT_CLK(NULL, "gpmc_fck", "gpmc_fck"), |
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DT_CLK(NULL, "sdma_fck", "sdma_fck"), |
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DT_CLK(NULL, "sdma_ick", "sdma_ick"), |
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DT_CLK(NULL, "sdrc_ick", "sdrc_ick"), |
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DT_CLK(NULL, "des_ick", "des_ick"), |
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DT_CLK("omap-sham", "ick", "sha_ick"), |
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DT_CLK(NULL, "sha_ick", "sha_ick"), |
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DT_CLK("omap_rng", "ick", "rng_ick"), |
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DT_CLK(NULL, "rng_ick", "rng_ick"), |
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DT_CLK("omap-aes", "ick", "aes_ick"), |
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DT_CLK(NULL, "aes_ick", "aes_ick"), |
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DT_CLK(NULL, "pka_ick", "pka_ick"), |
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DT_CLK(NULL, "usb_fck", "usb_fck"), |
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DT_CLK(NULL, "timer_32k_ck", "func_32k_ck"), |
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DT_CLK(NULL, "timer_sys_ck", "sys_ck"), |
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DT_CLK(NULL, "timer_ext_ck", "alt_ck"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk omap2420_clks[] = { |
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DT_CLK(NULL, "sys_clkout2_src", "sys_clkout2_src"), |
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DT_CLK(NULL, "sys_clkout2", "sys_clkout2"), |
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DT_CLK(NULL, "dsp_ick", "dsp_ick"), |
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DT_CLK(NULL, "iva1_ifck", "iva1_ifck"), |
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DT_CLK(NULL, "iva1_mpu_int_ifck", "iva1_mpu_int_ifck"), |
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DT_CLK(NULL, "wdt3_ick", "wdt3_ick"), |
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DT_CLK(NULL, "wdt3_fck", "wdt3_fck"), |
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DT_CLK("mmci-omap.0", "ick", "mmc_ick"), |
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DT_CLK(NULL, "mmc_ick", "mmc_ick"), |
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DT_CLK("mmci-omap.0", "fck", "mmc_fck"), |
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DT_CLK(NULL, "mmc_fck", "mmc_fck"), |
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DT_CLK(NULL, "eac_ick", "eac_ick"), |
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DT_CLK(NULL, "eac_fck", "eac_fck"), |
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DT_CLK(NULL, "i2c1_fck", "i2c1_fck"), |
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DT_CLK(NULL, "i2c2_fck", "i2c2_fck"), |
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DT_CLK(NULL, "vlynq_ick", "vlynq_ick"), |
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DT_CLK(NULL, "vlynq_fck", "vlynq_fck"), |
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DT_CLK("musb-hdrc", "fck", "osc_ck"), |
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{ .node_name = NULL }, |
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}; |
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static struct ti_dt_clk omap2430_clks[] = { |
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DT_CLK("twl", "fck", "osc_ck"), |
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DT_CLK(NULL, "iva2_1_ick", "iva2_1_ick"), |
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DT_CLK(NULL, "mdm_ick", "mdm_ick"), |
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DT_CLK(NULL, "mdm_osc_ck", "mdm_osc_ck"), |
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DT_CLK("omap-mcbsp.3", "ick", "mcbsp3_ick"), |
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DT_CLK(NULL, "mcbsp3_ick", "mcbsp3_ick"), |
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DT_CLK(NULL, "mcbsp3_fck", "mcbsp3_fck"), |
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DT_CLK("omap-mcbsp.4", "ick", "mcbsp4_ick"), |
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DT_CLK(NULL, "mcbsp4_ick", "mcbsp4_ick"), |
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DT_CLK(NULL, "mcbsp4_fck", "mcbsp4_fck"), |
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DT_CLK("omap-mcbsp.5", "ick", "mcbsp5_ick"), |
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DT_CLK(NULL, "mcbsp5_ick", "mcbsp5_ick"), |
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DT_CLK(NULL, "mcbsp5_fck", "mcbsp5_fck"), |
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DT_CLK("omap2_mcspi.3", "ick", "mcspi3_ick"), |
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DT_CLK(NULL, "mcspi3_ick", "mcspi3_ick"), |
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DT_CLK(NULL, "mcspi3_fck", "mcspi3_fck"), |
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DT_CLK(NULL, "icr_ick", "icr_ick"), |
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DT_CLK(NULL, "i2chs1_fck", "i2chs1_fck"), |
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DT_CLK(NULL, "i2chs2_fck", "i2chs2_fck"), |
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DT_CLK("musb-omap2430", "ick", "usbhs_ick"), |
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DT_CLK(NULL, "usbhs_ick", "usbhs_ick"), |
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DT_CLK("omap_hsmmc.0", "ick", "mmchs1_ick"), |
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DT_CLK(NULL, "mmchs1_ick", "mmchs1_ick"), |
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DT_CLK(NULL, "mmchs1_fck", "mmchs1_fck"), |
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DT_CLK("omap_hsmmc.1", "ick", "mmchs2_ick"), |
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DT_CLK(NULL, "mmchs2_ick", "mmchs2_ick"), |
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DT_CLK(NULL, "mmchs2_fck", "mmchs2_fck"), |
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DT_CLK(NULL, "gpio5_ick", "gpio5_ick"), |
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DT_CLK(NULL, "gpio5_fck", "gpio5_fck"), |
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DT_CLK(NULL, "mdm_intc_ick", "mdm_intc_ick"), |
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DT_CLK("omap_hsmmc.0", "mmchsdb_fck", "mmchsdb1_fck"), |
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DT_CLK(NULL, "mmchsdb1_fck", "mmchsdb1_fck"), |
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DT_CLK("omap_hsmmc.1", "mmchsdb_fck", "mmchsdb2_fck"), |
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DT_CLK(NULL, "mmchsdb2_fck", "mmchsdb2_fck"), |
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{ .node_name = NULL }, |
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}; |
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static const char *enable_init_clks[] = { |
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"apll96_ck", |
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"apll54_ck", |
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"sync_32k_ick", |
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"omapctrl_ick", |
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"gpmc_fck", |
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"sdrc_ick", |
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}; |
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|
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enum { |
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OMAP2_SOC_OMAP2420, |
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OMAP2_SOC_OMAP2430, |
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}; |
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|
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static int __init omap2xxx_dt_clk_init(int soc_type) |
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{ |
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ti_dt_clocks_register(omap2xxx_clks); |
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|
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if (soc_type == OMAP2_SOC_OMAP2420) |
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ti_dt_clocks_register(omap2420_clks); |
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else |
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ti_dt_clocks_register(omap2430_clks); |
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|
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omap2xxx_clkt_vps_init(); |
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|
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omap2_clk_disable_autoidle_all(); |
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|
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omap2_clk_enable_init_clocks(enable_init_clks, |
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ARRAY_SIZE(enable_init_clks)); |
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|
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pr_info("Clocking rate (Crystal/DPLL/MPU): %ld.%01ld/%ld/%ld MHz\n", |
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(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 1000000), |
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(clk_get_rate(clk_get_sys(NULL, "sys_ck")) / 100000) % 10, |
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(clk_get_rate(clk_get_sys(NULL, "dpll_ck")) / 1000000), |
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(clk_get_rate(clk_get_sys(NULL, "mpu_ck")) / 1000000)); |
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|
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return 0; |
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} |
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|
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int __init omap2420_dt_clk_init(void) |
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{ |
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return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2420); |
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} |
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|
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int __init omap2430_dt_clk_init(void) |
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{ |
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return omap2xxx_dt_clk_init(OMAP2_SOC_OMAP2430); |
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} |
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@ -0,0 +1,312 @@ |
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/*
|
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* DRA7 ATL (Audio Tracking Logic) clock driver |
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* |
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* Copyright (C) 2013 Texas Instruments, Inc. |
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* |
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* Peter Ujfalusi <peter.ujfalusi@ti.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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* |
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* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
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* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <linux/module.h> |
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#include <linux/clk-provider.h> |
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#include <linux/slab.h> |
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#include <linux/io.h> |
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#include <linux/of.h> |
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#include <linux/of_address.h> |
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#include <linux/platform_device.h> |
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#include <linux/pm_runtime.h> |
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|
||||
#define DRA7_ATL_INSTANCES 4 |
||||
|
||||
#define DRA7_ATL_PPMR_REG(id) (0x200 + (id * 0x80)) |
||||
#define DRA7_ATL_BBSR_REG(id) (0x204 + (id * 0x80)) |
||||
#define DRA7_ATL_ATLCR_REG(id) (0x208 + (id * 0x80)) |
||||
#define DRA7_ATL_SWEN_REG(id) (0x210 + (id * 0x80)) |
||||
#define DRA7_ATL_BWSMUX_REG(id) (0x214 + (id * 0x80)) |
||||
#define DRA7_ATL_AWSMUX_REG(id) (0x218 + (id * 0x80)) |
||||
#define DRA7_ATL_PCLKMUX_REG(id) (0x21c + (id * 0x80)) |
||||
|
||||
#define DRA7_ATL_SWEN BIT(0) |
||||
#define DRA7_ATL_DIVIDER_MASK (0x1f) |
||||
#define DRA7_ATL_PCLKMUX BIT(0) |
||||
struct dra7_atl_clock_info; |
||||
|
||||
struct dra7_atl_desc { |
||||
struct clk *clk; |
||||
struct clk_hw hw; |
||||
struct dra7_atl_clock_info *cinfo; |
||||
int id; |
||||
|
||||
bool probed; /* the driver for the IP has been loaded */ |
||||
bool valid; /* configured */ |
||||
bool enabled; |
||||
u32 bws; /* Baseband Word Select Mux */ |
||||
u32 aws; /* Audio Word Select Mux */ |
||||
u32 divider; /* Cached divider value */ |
||||
}; |
||||
|
||||
struct dra7_atl_clock_info { |
||||
struct device *dev; |
||||
void __iomem *iobase; |
||||
|
||||
struct dra7_atl_desc *cdesc; |
||||
}; |
||||
|
||||
#define to_atl_desc(_hw) container_of(_hw, struct dra7_atl_desc, hw) |
||||
|
||||
static inline void atl_write(struct dra7_atl_clock_info *cinfo, u32 reg, |
||||
u32 val) |
||||
{ |
||||
__raw_writel(val, cinfo->iobase + reg); |
||||
} |
||||
|
||||
static inline int atl_read(struct dra7_atl_clock_info *cinfo, u32 reg) |
||||
{ |
||||
return __raw_readl(cinfo->iobase + reg); |
||||
} |
||||
|
||||
static int atl_clk_enable(struct clk_hw *hw) |
||||
{ |
||||
struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
||||
|
||||
if (!cdesc->probed) |
||||
goto out; |
||||
|
||||
if (unlikely(!cdesc->valid)) |
||||
dev_warn(cdesc->cinfo->dev, "atl%d has not been configured\n", |
||||
cdesc->id); |
||||
pm_runtime_get_sync(cdesc->cinfo->dev); |
||||
|
||||
atl_write(cdesc->cinfo, DRA7_ATL_ATLCR_REG(cdesc->id), |
||||
cdesc->divider - 1); |
||||
atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), DRA7_ATL_SWEN); |
||||
|
||||
out: |
||||
cdesc->enabled = true; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void atl_clk_disable(struct clk_hw *hw) |
||||
{ |
||||
struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
||||
|
||||
if (!cdesc->probed) |
||||
goto out; |
||||
|
||||
atl_write(cdesc->cinfo, DRA7_ATL_SWEN_REG(cdesc->id), 0); |
||||
pm_runtime_put_sync(cdesc->cinfo->dev); |
||||
|
||||
out: |
||||
cdesc->enabled = false; |
||||
} |
||||
|
||||
static int atl_clk_is_enabled(struct clk_hw *hw) |
||||
{ |
||||
struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
||||
|
||||
return cdesc->enabled; |
||||
} |
||||
|
||||
static unsigned long atl_clk_recalc_rate(struct clk_hw *hw, |
||||
unsigned long parent_rate) |
||||
{ |
||||
struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
||||
|
||||
return parent_rate / cdesc->divider; |
||||
} |
||||
|
||||
static long atl_clk_round_rate(struct clk_hw *hw, unsigned long rate, |
||||
unsigned long *parent_rate) |
||||
{ |
||||
unsigned divider; |
||||
|
||||
divider = (*parent_rate + rate / 2) / rate; |
||||
if (divider > DRA7_ATL_DIVIDER_MASK + 1) |
||||
divider = DRA7_ATL_DIVIDER_MASK + 1; |
||||
|
||||
return *parent_rate / divider; |
||||
} |
||||
|
||||
static int atl_clk_set_rate(struct clk_hw *hw, unsigned long rate, |
||||
unsigned long parent_rate) |
||||
{ |
||||
struct dra7_atl_desc *cdesc = to_atl_desc(hw); |
||||
u32 divider; |
||||
|
||||
divider = ((parent_rate + rate / 2) / rate) - 1; |
||||
if (divider > DRA7_ATL_DIVIDER_MASK) |
||||
divider = DRA7_ATL_DIVIDER_MASK; |
||||
|
||||
cdesc->divider = divider + 1; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
const struct clk_ops atl_clk_ops = { |
||||
.enable = atl_clk_enable, |
||||
.disable = atl_clk_disable, |
||||
.is_enabled = atl_clk_is_enabled, |
||||
.recalc_rate = atl_clk_recalc_rate, |
||||
.round_rate = atl_clk_round_rate, |
||||
.set_rate = atl_clk_set_rate, |
||||
}; |
||||
|
||||
static void __init of_dra7_atl_clock_setup(struct device_node *node) |
||||
{ |
||||
struct dra7_atl_desc *clk_hw = NULL; |
||||
struct clk_init_data init = { 0 }; |
||||
const char **parent_names = NULL; |
||||
struct clk *clk; |
||||
|
||||
clk_hw = kzalloc(sizeof(*clk_hw), GFP_KERNEL); |
||||
if (!clk_hw) { |
||||
pr_err("%s: could not allocate dra7_atl_desc\n", __func__); |
||||
return; |
||||
} |
||||
|
||||
clk_hw->hw.init = &init; |
||||
clk_hw->divider = 1; |
||||
init.name = node->name; |
||||
init.ops = &atl_clk_ops; |
||||
init.flags = CLK_IGNORE_UNUSED; |
||||
init.num_parents = of_clk_get_parent_count(node); |
||||
|
||||
if (init.num_parents != 1) { |
||||
pr_err("%s: atl clock %s must have 1 parent\n", __func__, |
||||
node->name); |
||||
goto cleanup; |
||||
} |
||||
|
||||
parent_names = kzalloc(sizeof(char *), GFP_KERNEL); |
||||
|
||||
if (!parent_names) |
||||
goto cleanup; |
||||
|
||||
parent_names[0] = of_clk_get_parent_name(node, 0); |
||||
|
||||
init.parent_names = parent_names; |
||||
|
||||
clk = clk_register(NULL, &clk_hw->hw); |
||||
|
||||
if (!IS_ERR(clk)) { |
||||
of_clk_add_provider(node, of_clk_src_simple_get, clk); |
||||
return; |
||||
} |
||||
cleanup: |
||||
kfree(parent_names); |
||||
kfree(clk_hw); |
||||
} |
||||
CLK_OF_DECLARE(dra7_atl_clock, "ti,dra7-atl-clock", of_dra7_atl_clock_setup); |
||||
|
||||
static int of_dra7_atl_clk_probe(struct platform_device *pdev) |
||||
{ |
||||
struct device_node *node = pdev->dev.of_node; |
||||
struct dra7_atl_clock_info *cinfo; |
||||
int i; |
||||
int ret = 0; |
||||
|
||||
if (!node) |
||||
return -ENODEV; |
||||
|
||||
cinfo = devm_kzalloc(&pdev->dev, sizeof(*cinfo), GFP_KERNEL); |
||||
if (!cinfo) |
||||
return -ENOMEM; |
||||
|
||||
cinfo->iobase = of_iomap(node, 0); |
||||
cinfo->dev = &pdev->dev; |
||||
pm_runtime_enable(cinfo->dev); |
||||
|
||||
pm_runtime_get_sync(cinfo->dev); |
||||
atl_write(cinfo, DRA7_ATL_PCLKMUX_REG(0), DRA7_ATL_PCLKMUX); |
||||
|
||||
for (i = 0; i < DRA7_ATL_INSTANCES; i++) { |
||||
struct device_node *cfg_node; |
||||
char prop[5]; |
||||
struct dra7_atl_desc *cdesc; |
||||
struct of_phandle_args clkspec; |
||||
struct clk *clk; |
||||
int rc; |
||||
|
||||
rc = of_parse_phandle_with_args(node, "ti,provided-clocks", |
||||
NULL, i, &clkspec); |
||||
|
||||
if (rc) { |
||||
pr_err("%s: failed to lookup atl clock %d\n", __func__, |
||||
i); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
clk = of_clk_get_from_provider(&clkspec); |
||||
|
||||
cdesc = to_atl_desc(__clk_get_hw(clk)); |
||||
cdesc->cinfo = cinfo; |
||||
cdesc->id = i; |
||||
|
||||
/* Get configuration for the ATL instances */ |
||||
snprintf(prop, sizeof(prop), "atl%u", i); |
||||
cfg_node = of_find_node_by_name(node, prop); |
||||
if (cfg_node) { |
||||
ret = of_property_read_u32(cfg_node, "bws", |
||||
&cdesc->bws); |
||||
ret |= of_property_read_u32(cfg_node, "aws", |
||||
&cdesc->aws); |
||||
if (!ret) { |
||||
cdesc->valid = true; |
||||
atl_write(cinfo, DRA7_ATL_BWSMUX_REG(i), |
||||
cdesc->bws); |
||||
atl_write(cinfo, DRA7_ATL_AWSMUX_REG(i), |
||||
cdesc->aws); |
||||
} |
||||
} |
||||
|
||||
cdesc->probed = true; |
||||
/*
|
||||
* Enable the clock if it has been asked prior to loading the |
||||
* hw driver |
||||
*/ |
||||
if (cdesc->enabled) |
||||
atl_clk_enable(__clk_get_hw(clk)); |
||||
} |
||||
pm_runtime_put_sync(cinfo->dev); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int of_dra7_atl_clk_remove(struct platform_device *pdev) |
||||
{ |
||||
pm_runtime_disable(&pdev->dev); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct of_device_id of_dra7_atl_clk_match_tbl[] = { |
||||
{ .compatible = "ti,dra7-atl", }, |
||||
{}, |
||||
}; |
||||
MODULE_DEVICE_TABLE(of, of_dra7_atl_clk_match_tbl); |
||||
|
||||
static struct platform_driver dra7_atl_clk_driver = { |
||||
.driver = { |
||||
.name = "dra7-atl", |
||||
.owner = THIS_MODULE, |
||||
.of_match_table = of_dra7_atl_clk_match_tbl, |
||||
}, |
||||
.probe = of_dra7_atl_clk_probe, |
||||
.remove = of_dra7_atl_clk_remove, |
||||
}; |
||||
|
||||
module_platform_driver(dra7_atl_clk_driver); |
||||
|
||||
MODULE_DESCRIPTION("Clock driver for DRA7 Audio Tracking Logic"); |
||||
MODULE_ALIAS("platform:dra7-atl-clock"); |
||||
MODULE_AUTHOR("Peter Ujfalusi <peter.ujfalusi@ti.com>"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
@ -0,0 +1,40 @@ |
||||
/*
|
||||
* This header provides constants for DRA7 ATL (Audio Tracking Logic) |
||||
* |
||||
* The constants defined in this header are used in dts files |
||||
* |
||||
* Copyright (C) 2013 Texas Instruments, Inc. |
||||
* |
||||
* Peter Ujfalusi <peter.ujfalusi@ti.com> |
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 as |
||||
* published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed "as is" WITHOUT ANY WARRANTY of any |
||||
* kind, whether express or implied; without even the implied warranty |
||||
* of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#ifndef _DT_BINDINGS_CLK_DRA7_ATL_H |
||||
#define _DT_BINDINGS_CLK_DRA7_ATL_H |
||||
|
||||
#define DRA7_ATL_WS_MCASP1_FSR 0 |
||||
#define DRA7_ATL_WS_MCASP1_FSX 1 |
||||
#define DRA7_ATL_WS_MCASP2_FSR 2 |
||||
#define DRA7_ATL_WS_MCASP2_FSX 3 |
||||
#define DRA7_ATL_WS_MCASP3_FSX 4 |
||||
#define DRA7_ATL_WS_MCASP4_FSX 5 |
||||
#define DRA7_ATL_WS_MCASP5_FSX 6 |
||||
#define DRA7_ATL_WS_MCASP6_FSX 7 |
||||
#define DRA7_ATL_WS_MCASP7_FSX 8 |
||||
#define DRA7_ATL_WS_MCASP8_FSX 9 |
||||
#define DRA7_ATL_WS_MCASP8_AHCLKX 10 |
||||
#define DRA7_ATL_WS_XREF_CLK3 11 |
||||
#define DRA7_ATL_WS_XREF_CLK0 12 |
||||
#define DRA7_ATL_WS_XREF_CLK1 13 |
||||
#define DRA7_ATL_WS_XREF_CLK2 14 |
||||
#define DRA7_ATL_WS_OSC1_X1 15 |
||||
|
||||
#endif |
||||
Loading…
Reference in new issue