@ -344,6 +344,41 @@ ENTRY(cpu_mohawk_set_pte_ext)
mcr p15 , 0 , r0 , c7 , c10 , 4 @ drain WB
mov p c , l r
.globl cpu_mohawk_suspend_size
.equ cpu_ m o h a w k _ s u s p e n d _ s i z e , 4 * 6
# ifdef C O N F I G _ P M _ S L E E P
ENTRY( c p u _ m o h a w k _ d o _ s u s p e n d )
stmfd s p ! , { r4 - r9 , l r }
mrc p14 , 0 , r4 , c6 , c0 , 0 @ clock configuration, for turbo mode
mrc p15 , 0 , r5 , c15 , c1 , 0 @ CP access reg
mrc p15 , 0 , r6 , c13 , c0 , 0 @ PID
mrc p15 , 0 , r7 , c3 , c0 , 0 @ domain ID
mrc p15 , 0 , r8 , c1 , c0 , 1 @ auxiliary control reg
mrc p15 , 0 , r9 , c1 , c0 , 0 @ control reg
bic r4 , r4 , #2 @ clear frequency change bit
stmia r0 , { r4 - r9 } @ store cp regs
ldmia s p ! , { r4 - r9 , p c }
ENDPROC( c p u _ m o h a w k _ d o _ s u s p e n d )
ENTRY( c p u _ m o h a w k _ d o _ r e s u m e )
ldmia r0 , { r4 - r9 } @ load cp regs
mov i p , #0
mcr p15 , 0 , i p , c7 , c7 , 0 @ invalidate I & D caches, BTB
mcr p15 , 0 , i p , c7 , c10 , 4 @ drain write (&fill) buffer
mcr p15 , 0 , i p , c7 , c5 , 4 @ flush prefetch buffer
mcr p15 , 0 , i p , c8 , c7 , 0 @ invalidate I & D TLBs
mcr p14 , 0 , r4 , c6 , c0 , 0 @ clock configuration, turbo mode.
mcr p15 , 0 , r5 , c15 , c1 , 0 @ CP access reg
mcr p15 , 0 , r6 , c13 , c0 , 0 @ PID
mcr p15 , 0 , r7 , c3 , c0 , 0 @ domain ID
orr r1 , r1 , #0x18 @ cache the page table in L2
mcr p15 , 0 , r1 , c2 , c0 , 0 @ translation table base addr
mcr p15 , 0 , r8 , c1 , c0 , 1 @ auxiliary control reg
mov r0 , r9 @ control register
b c p u _ r e s u m e _ m m u
ENDPROC( c p u _ m o h a w k _ d o _ r e s u m e )
# endif
_ _ CPUINIT
.type _ _ mohawk_ s e t u p , #f u n c t i o n