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@ -2593,16 +2593,16 @@ void ironlake_teardown_rc6(struct drm_device *dev) |
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{ |
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struct drm_i915_private *dev_priv = dev->dev_private; |
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if (dev_priv->renderctx) { |
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i915_gem_object_unpin(dev_priv->renderctx); |
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drm_gem_object_unreference(&dev_priv->renderctx->base); |
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dev_priv->renderctx = NULL; |
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if (dev_priv->ips.renderctx) { |
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i915_gem_object_unpin(dev_priv->ips.renderctx); |
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drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
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dev_priv->ips.renderctx = NULL; |
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} |
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if (dev_priv->pwrctx) { |
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i915_gem_object_unpin(dev_priv->pwrctx); |
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drm_gem_object_unreference(&dev_priv->pwrctx->base); |
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dev_priv->pwrctx = NULL; |
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if (dev_priv->ips.pwrctx) { |
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i915_gem_object_unpin(dev_priv->ips.pwrctx); |
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drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
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dev_priv->ips.pwrctx = NULL; |
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} |
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} |
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@ -2628,14 +2628,14 @@ static int ironlake_setup_rc6(struct drm_device *dev) |
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{ |
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struct drm_i915_private *dev_priv = dev->dev_private; |
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if (dev_priv->renderctx == NULL) |
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dev_priv->renderctx = intel_alloc_context_page(dev); |
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if (!dev_priv->renderctx) |
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if (dev_priv->ips.renderctx == NULL) |
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dev_priv->ips.renderctx = intel_alloc_context_page(dev); |
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if (!dev_priv->ips.renderctx) |
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return -ENOMEM; |
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if (dev_priv->pwrctx == NULL) |
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dev_priv->pwrctx = intel_alloc_context_page(dev); |
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if (!dev_priv->pwrctx) { |
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if (dev_priv->ips.pwrctx == NULL) |
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dev_priv->ips.pwrctx = intel_alloc_context_page(dev); |
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if (!dev_priv->ips.pwrctx) { |
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ironlake_teardown_rc6(dev); |
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return -ENOMEM; |
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} |
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@ -2673,7 +2673,7 @@ static void ironlake_enable_rc6(struct drm_device *dev) |
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intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
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intel_ring_emit(ring, MI_SET_CONTEXT); |
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intel_ring_emit(ring, dev_priv->renderctx->gtt_offset | |
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intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset | |
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MI_MM_SPACE_GTT | |
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MI_SAVE_EXT_STATE_EN | |
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MI_RESTORE_EXT_STATE_EN | |
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@ -2695,7 +2695,7 @@ static void ironlake_enable_rc6(struct drm_device *dev) |
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return; |
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} |
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I915_WRITE(PWRCTXA, dev_priv->pwrctx->gtt_offset | PWRCTX_EN); |
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I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN); |
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I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
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} |
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