The serial peripheral interface (SPI) module implemented on Freescale Vybrid platform provides a synchronous serial bus for communication between Vybrid and the external peripheral device. The SPI supports full-duplex, three-wire synchronous transfer, has TX/RX FIFO with depth of four entries. This driver is the SPI master mode driver and has been tested on Vybrid VF610TWR board. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Chao Fu <b44548@freescale.com> Signed-off-by: Mark Brown <broonie@linaro.org>tirimbino
Chao Fu
12 years ago
committed by
Mark Brown
parent
9cbd72e577
commit
349ad66c0a
@ -0,0 +1,557 @@ |
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/*
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* drivers/spi/spi-fsl-dspi.c |
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* |
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* Copyright 2013 Freescale Semiconductor, Inc. |
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* |
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* Freescale DSPI driver |
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* This file contains a driver for the Freescale DSPI |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License as published by |
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* the Free Software Foundation; either version 2 of the License, or |
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* (at your option) any later version. |
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* |
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*/ |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/interrupt.h> |
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#include <linux/errno.h> |
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#include <linux/platform_device.h> |
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#include <linux/sched.h> |
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#include <linux/delay.h> |
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#include <linux/io.h> |
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#include <linux/clk.h> |
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#include <linux/err.h> |
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#include <linux/spi/spi.h> |
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#include <linux/spi/spi_bitbang.h> |
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#include <linux/pm_runtime.h> |
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#include <linux/of.h> |
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#include <linux/of_device.h> |
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#define DRIVER_NAME "fsl-dspi" |
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#define TRAN_STATE_RX_VOID 0x01 |
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#define TRAN_STATE_TX_VOID 0x02 |
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#define TRAN_STATE_WORD_ODD_NUM 0x04 |
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#define DSPI_FIFO_SIZE 4 |
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#define SPI_MCR 0x00 |
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#define SPI_MCR_MASTER (1 << 31) |
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#define SPI_MCR_PCSIS (0x3F << 16) |
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#define SPI_MCR_CLR_TXF (1 << 11) |
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#define SPI_MCR_CLR_RXF (1 << 10) |
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#define SPI_TCR 0x08 |
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#define SPI_CTAR(x) (0x0c + (x * 4)) |
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#define SPI_CTAR_FMSZ(x) (((x) & 0x0000000f) << 27) |
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#define SPI_CTAR_CPOL(x) ((x) << 26) |
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#define SPI_CTAR_CPHA(x) ((x) << 25) |
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#define SPI_CTAR_LSBFE(x) ((x) << 24) |
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#define SPI_CTAR_PCSSCR(x) (((x) & 0x00000003) << 22) |
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#define SPI_CTAR_PASC(x) (((x) & 0x00000003) << 20) |
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#define SPI_CTAR_PDT(x) (((x) & 0x00000003) << 18) |
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#define SPI_CTAR_PBR(x) (((x) & 0x00000003) << 16) |
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#define SPI_CTAR_CSSCK(x) (((x) & 0x0000000f) << 12) |
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#define SPI_CTAR_ASC(x) (((x) & 0x0000000f) << 8) |
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#define SPI_CTAR_DT(x) (((x) & 0x0000000f) << 4) |
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#define SPI_CTAR_BR(x) ((x) & 0x0000000f) |
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#define SPI_CTAR0_SLAVE 0x0c |
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#define SPI_SR 0x2c |
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#define SPI_SR_EOQF 0x10000000 |
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#define SPI_RSER 0x30 |
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#define SPI_RSER_EOQFE 0x10000000 |
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#define SPI_PUSHR 0x34 |
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#define SPI_PUSHR_CONT (1 << 31) |
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#define SPI_PUSHR_CTAS(x) (((x) & 0x00000007) << 28) |
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#define SPI_PUSHR_EOQ (1 << 27) |
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#define SPI_PUSHR_CTCNT (1 << 26) |
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#define SPI_PUSHR_PCS(x) (((1 << x) & 0x0000003f) << 16) |
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#define SPI_PUSHR_TXDATA(x) ((x) & 0x0000ffff) |
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#define SPI_PUSHR_SLAVE 0x34 |
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#define SPI_POPR 0x38 |
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#define SPI_POPR_RXDATA(x) ((x) & 0x0000ffff) |
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#define SPI_TXFR0 0x3c |
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#define SPI_TXFR1 0x40 |
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#define SPI_TXFR2 0x44 |
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#define SPI_TXFR3 0x48 |
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#define SPI_RXFR0 0x7c |
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#define SPI_RXFR1 0x80 |
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#define SPI_RXFR2 0x84 |
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#define SPI_RXFR3 0x88 |
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#define SPI_FRAME_BITS(bits) SPI_CTAR_FMSZ((bits) - 1) |
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#define SPI_FRAME_BITS_MASK SPI_CTAR_FMSZ(0xf) |
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#define SPI_FRAME_BITS_16 SPI_CTAR_FMSZ(0xf) |
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#define SPI_FRAME_BITS_8 SPI_CTAR_FMSZ(0x7) |
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#define SPI_CS_INIT 0x01 |
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#define SPI_CS_ASSERT 0x02 |
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#define SPI_CS_DROP 0x04 |
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struct chip_data { |
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u32 mcr_val; |
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u32 ctar_val; |
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u16 void_write_data; |
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}; |
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struct fsl_dspi { |
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struct spi_bitbang bitbang; |
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struct platform_device *pdev; |
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void *base; |
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int irq; |
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struct clk *clk; |
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struct spi_transfer *cur_transfer; |
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struct chip_data *cur_chip; |
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size_t len; |
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void *tx; |
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void *tx_end; |
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void *rx; |
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void *rx_end; |
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char dataflags; |
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u8 cs; |
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u16 void_write_data; |
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wait_queue_head_t waitq; |
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u32 waitflags; |
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}; |
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static inline int is_double_byte_mode(struct fsl_dspi *dspi) |
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{ |
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return ((readl(dspi->base + SPI_CTAR(dspi->cs)) & SPI_FRAME_BITS_MASK) |
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== SPI_FRAME_BITS(8)) ? 0 : 1; |
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} |
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static void set_bit_mode(struct fsl_dspi *dspi, unsigned char bits) |
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{ |
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u32 temp; |
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temp = readl(dspi->base + SPI_CTAR(dspi->cs)); |
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temp &= ~SPI_FRAME_BITS_MASK; |
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temp |= SPI_FRAME_BITS(bits); |
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writel(temp, dspi->base + SPI_CTAR(dspi->cs)); |
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} |
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static void hz_to_spi_baud(char *pbr, char *br, int speed_hz, |
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unsigned long clkrate) |
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{ |
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/* Valid baud rate pre-scaler values */ |
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int pbr_tbl[4] = {2, 3, 5, 7}; |
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int brs[16] = { 2, 4, 6, 8, |
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16, 32, 64, 128, |
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256, 512, 1024, 2048, |
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4096, 8192, 16384, 32768 }; |
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int temp, i = 0, j = 0; |
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temp = clkrate / 2 / speed_hz; |
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for (i = 0; i < ARRAY_SIZE(pbr_tbl); i++) |
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for (j = 0; j < ARRAY_SIZE(brs); j++) { |
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if (pbr_tbl[i] * brs[j] >= temp) { |
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*pbr = i; |
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*br = j; |
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return; |
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} |
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} |
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pr_warn("Can not find valid buad rate,speed_hz is %d,clkrate is %ld\
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,we use the max prescaler value.\n", speed_hz, clkrate); |
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*pbr = ARRAY_SIZE(pbr_tbl) - 1; |
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*br = ARRAY_SIZE(brs) - 1; |
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} |
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static int dspi_transfer_write(struct fsl_dspi *dspi) |
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{ |
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int tx_count = 0; |
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int tx_word; |
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u16 d16; |
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u8 d8; |
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u32 dspi_pushr = 0; |
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int first = 1; |
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tx_word = is_double_byte_mode(dspi); |
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/* If we are in word mode, but only have a single byte to transfer
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* then switch to byte mode temporarily. Will switch back at the |
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* end of the transfer. |
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*/ |
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if (tx_word && (dspi->len == 1)) { |
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dspi->dataflags |= TRAN_STATE_WORD_ODD_NUM; |
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set_bit_mode(dspi, 8); |
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tx_word = 0; |
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} |
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while (dspi->len && (tx_count < DSPI_FIFO_SIZE)) { |
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if (tx_word) { |
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if (dspi->len == 1) |
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break; |
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if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { |
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d16 = *(u16 *)dspi->tx; |
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dspi->tx += 2; |
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} else { |
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d16 = dspi->void_write_data; |
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} |
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dspi_pushr = SPI_PUSHR_TXDATA(d16) | |
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SPI_PUSHR_PCS(dspi->cs) | |
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SPI_PUSHR_CTAS(dspi->cs) | |
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SPI_PUSHR_CONT; |
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dspi->len -= 2; |
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} else { |
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if (!(dspi->dataflags & TRAN_STATE_TX_VOID)) { |
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d8 = *(u8 *)dspi->tx; |
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dspi->tx++; |
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} else { |
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d8 = (u8)dspi->void_write_data; |
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} |
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dspi_pushr = SPI_PUSHR_TXDATA(d8) | |
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SPI_PUSHR_PCS(dspi->cs) | |
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SPI_PUSHR_CTAS(dspi->cs) | |
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SPI_PUSHR_CONT; |
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dspi->len--; |
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} |
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if (dspi->len == 0 || tx_count == DSPI_FIFO_SIZE - 1) { |
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/* last transfer in the transfer */ |
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dspi_pushr |= SPI_PUSHR_EOQ; |
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} else if (tx_word && (dspi->len == 1)) |
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dspi_pushr |= SPI_PUSHR_EOQ; |
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if (first) { |
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first = 0; |
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dspi_pushr |= SPI_PUSHR_CTCNT; /* clear counter */ |
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} |
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writel(dspi_pushr, dspi->base + SPI_PUSHR); |
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tx_count++; |
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} |
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return tx_count * (tx_word + 1); |
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} |
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static int dspi_transfer_read(struct fsl_dspi *dspi) |
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{ |
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int rx_count = 0; |
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int rx_word = is_double_byte_mode(dspi); |
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u16 d; |
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while ((dspi->rx < dspi->rx_end) |
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&& (rx_count < DSPI_FIFO_SIZE)) { |
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if (rx_word) { |
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if ((dspi->rx_end - dspi->rx) == 1) |
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break; |
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d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); |
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
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*(u16 *)dspi->rx = d; |
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dspi->rx += 2; |
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} else { |
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d = SPI_POPR_RXDATA(readl(dspi->base + SPI_POPR)); |
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if (!(dspi->dataflags & TRAN_STATE_RX_VOID)) |
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*(u8 *)dspi->rx = d; |
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dspi->rx++; |
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} |
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rx_count++; |
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} |
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return rx_count; |
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} |
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static int dspi_txrx_transfer(struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
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dspi->cur_transfer = t; |
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dspi->cur_chip = spi_get_ctldata(spi); |
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dspi->cs = spi->chip_select; |
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dspi->void_write_data = dspi->cur_chip->void_write_data; |
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dspi->dataflags = 0; |
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dspi->tx = (void *)t->tx_buf; |
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dspi->tx_end = dspi->tx + t->len; |
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dspi->rx = t->rx_buf; |
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dspi->rx_end = dspi->rx + t->len; |
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dspi->len = t->len; |
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if (!dspi->rx) |
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dspi->dataflags |= TRAN_STATE_RX_VOID; |
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if (!dspi->tx) |
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dspi->dataflags |= TRAN_STATE_TX_VOID; |
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writel(dspi->cur_chip->mcr_val, dspi->base + SPI_MCR); |
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writel(dspi->cur_chip->ctar_val, dspi->base + SPI_CTAR(dspi->cs)); |
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writel(SPI_RSER_EOQFE, dspi->base + SPI_RSER); |
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if (t->speed_hz) |
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writel(dspi->cur_chip->ctar_val, |
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dspi->base + SPI_CTAR(dspi->cs)); |
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dspi_transfer_write(dspi); |
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if (wait_event_interruptible(dspi->waitq, dspi->waitflags)) |
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dev_err(&dspi->pdev->dev, "wait transfer complete fail!\n"); |
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dspi->waitflags = 0; |
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return t->len - dspi->len; |
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} |
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static void dspi_chipselect(struct spi_device *spi, int value) |
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{ |
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struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
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u32 pushr = readl(dspi->base + SPI_PUSHR); |
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switch (value) { |
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case BITBANG_CS_ACTIVE: |
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pushr |= SPI_PUSHR_CONT; |
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case BITBANG_CS_INACTIVE: |
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pushr &= ~SPI_PUSHR_CONT; |
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} |
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writel(pushr, dspi->base + SPI_PUSHR); |
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} |
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static int dspi_setup_transfer(struct spi_device *spi, struct spi_transfer *t) |
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{ |
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struct chip_data *chip; |
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struct fsl_dspi *dspi = spi_master_get_devdata(spi->master); |
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unsigned char br = 0, pbr = 0, fmsz = 0; |
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/* Only alloc on first setup */ |
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chip = spi_get_ctldata(spi); |
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if (chip == NULL) { |
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chip = kcalloc(1, sizeof(struct chip_data), GFP_KERNEL); |
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if (!chip) |
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return -ENOMEM; |
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} |
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chip->mcr_val = SPI_MCR_MASTER | SPI_MCR_PCSIS | |
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SPI_MCR_CLR_TXF | SPI_MCR_CLR_RXF; |
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if ((spi->bits_per_word >= 4) && (spi->bits_per_word <= 16)) { |
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fmsz = spi->bits_per_word - 1; |
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} else { |
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pr_err("Invalid wordsize\n"); |
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kfree(chip); |
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return -ENODEV; |
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} |
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chip->void_write_data = 0; |
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hz_to_spi_baud(&pbr, &br, |
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spi->max_speed_hz, clk_get_rate(dspi->clk)); |
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chip->ctar_val = SPI_CTAR_FMSZ(fmsz) |
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| SPI_CTAR_CPOL(spi->mode & SPI_CPOL ? 1 : 0) |
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| SPI_CTAR_CPHA(spi->mode & SPI_CPHA ? 1 : 0) |
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| SPI_CTAR_LSBFE(spi->mode & SPI_LSB_FIRST ? 1 : 0) |
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| SPI_CTAR_PBR(pbr) |
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| SPI_CTAR_BR(br); |
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spi_set_ctldata(spi, chip); |
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return 0; |
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} |
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static int dspi_setup(struct spi_device *spi) |
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{ |
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if (!spi->max_speed_hz) |
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return -EINVAL; |
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if (!spi->bits_per_word) |
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spi->bits_per_word = 8; |
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return dspi_setup_transfer(spi, NULL); |
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} |
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static irqreturn_t dspi_interrupt(int irq, void *dev_id) |
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{ |
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struct fsl_dspi *dspi = (struct fsl_dspi *)dev_id; |
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writel(SPI_SR_EOQF, dspi->base + SPI_SR); |
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dspi_transfer_read(dspi); |
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if (!dspi->len) { |
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if (dspi->dataflags & TRAN_STATE_WORD_ODD_NUM) |
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set_bit_mode(dspi, 16); |
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dspi->waitflags = 1; |
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wake_up_interruptible(&dspi->waitq); |
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} else { |
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dspi_transfer_write(dspi); |
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return IRQ_HANDLED; |
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} |
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return IRQ_HANDLED; |
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} |
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static struct of_device_id fsl_dspi_dt_ids[] = { |
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{ .compatible = "fsl,vf610-dspi", .data = NULL, }, |
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{ /* sentinel */ } |
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}; |
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MODULE_DEVICE_TABLE(of, fsl_dspi_dt_ids); |
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#ifdef CONFIG_PM_SLEEP |
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static int dspi_suspend(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct fsl_dspi *dspi = spi_master_get_devdata(master); |
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spi_master_suspend(master); |
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clk_disable_unprepare(dspi->clk); |
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return 0; |
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} |
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static int dspi_resume(struct device *dev) |
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{ |
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struct spi_master *master = dev_get_drvdata(dev); |
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struct fsl_dspi *dspi = spi_master_get_devdata(master); |
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clk_prepare_enable(dspi->clk); |
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spi_master_resume(master); |
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return 0; |
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} |
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#endif /* CONFIG_PM_SLEEP */ |
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static const struct dev_pm_ops dspi_pm = { |
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SET_SYSTEM_SLEEP_PM_OPS(dspi_suspend, dspi_resume) |
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}; |
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static int dspi_probe(struct platform_device *pdev) |
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{ |
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struct device_node *np = pdev->dev.of_node; |
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struct spi_master *master; |
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struct fsl_dspi *dspi; |
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struct resource *res; |
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int ret = 0, cs_num, bus_num; |
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master = spi_alloc_master(&pdev->dev, sizeof(struct fsl_dspi)); |
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if (!master) |
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return -ENOMEM; |
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dspi = spi_master_get_devdata(master); |
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dspi->pdev = pdev; |
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dspi->bitbang.master = spi_master_get(master); |
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dspi->bitbang.chipselect = dspi_chipselect; |
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dspi->bitbang.setup_transfer = dspi_setup_transfer; |
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dspi->bitbang.txrx_bufs = dspi_txrx_transfer; |
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dspi->bitbang.master->setup = dspi_setup; |
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dspi->bitbang.master->dev.of_node = pdev->dev.of_node; |
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master->mode_bits = SPI_CPOL | SPI_CPHA; |
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master->bits_per_word_mask = SPI_BPW_MASK(4) | SPI_BPW_MASK(8) | |
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SPI_BPW_MASK(16); |
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ret = of_property_read_u32(np, "spi-num-chipselects", &cs_num); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "can't get spi-num-chipselects\n"); |
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goto out_master_put; |
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} |
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master->num_chipselect = cs_num; |
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ret = of_property_read_u32(np, "bus-num", &bus_num); |
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if (ret < 0) { |
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dev_err(&pdev->dev, "can't get bus-num\n"); |
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goto out_master_put; |
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} |
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master->bus_num = bus_num; |
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
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if (!res) { |
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dev_err(&pdev->dev, "can't get platform resource\n"); |
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ret = -EINVAL; |
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goto out_master_put; |
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} |
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dspi->base = devm_ioremap_resource(&pdev->dev, res); |
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if (!dspi->base) { |
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ret = -EINVAL; |
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goto out_master_put; |
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} |
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dspi->irq = platform_get_irq(pdev, 0); |
||||
if (dspi->irq < 0) { |
||||
dev_err(&pdev->dev, "can't get platform irq\n"); |
||||
ret = dspi->irq; |
||||
goto out_master_put; |
||||
} |
||||
|
||||
ret = devm_request_irq(&pdev->dev, dspi->irq, dspi_interrupt, 0, |
||||
pdev->name, dspi); |
||||
if (ret < 0) { |
||||
dev_err(&pdev->dev, "Unable to attach DSPI interrupt\n"); |
||||
goto out_master_put; |
||||
} |
||||
|
||||
dspi->clk = devm_clk_get(&pdev->dev, "dspi"); |
||||
if (IS_ERR(dspi->clk)) { |
||||
ret = PTR_ERR(dspi->clk); |
||||
dev_err(&pdev->dev, "unable to get clock\n"); |
||||
goto out_master_put; |
||||
} |
||||
clk_prepare_enable(dspi->clk); |
||||
|
||||
init_waitqueue_head(&dspi->waitq); |
||||
platform_set_drvdata(pdev, dspi); |
||||
|
||||
ret = spi_bitbang_start(&dspi->bitbang); |
||||
if (ret != 0) { |
||||
dev_err(&pdev->dev, "Problem registering DSPI master\n"); |
||||
goto out_clk_put; |
||||
} |
||||
|
||||
pr_info(KERN_INFO "Freescale DSPI master initialized\n"); |
||||
return ret; |
||||
|
||||
out_clk_put: |
||||
clk_disable_unprepare(dspi->clk); |
||||
out_master_put: |
||||
spi_master_put(master); |
||||
platform_set_drvdata(pdev, NULL); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int dspi_remove(struct platform_device *pdev) |
||||
{ |
||||
struct fsl_dspi *dspi = platform_get_drvdata(pdev); |
||||
|
||||
/* Disconnect from the SPI framework */ |
||||
spi_bitbang_stop(&dspi->bitbang); |
||||
spi_master_put(dspi->bitbang.master); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct platform_driver fsl_dspi_driver = { |
||||
.driver.name = DRIVER_NAME, |
||||
.driver.of_match_table = fsl_dspi_dt_ids, |
||||
.driver.owner = THIS_MODULE, |
||||
.driver.pm = &dspi_pm, |
||||
.probe = dspi_probe, |
||||
.remove = dspi_remove, |
||||
}; |
||||
module_platform_driver(fsl_dspi_driver); |
||||
|
||||
MODULE_DESCRIPTION("Freescale DSPI Controller Driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
MODULE_ALIAS("platform:" DRIVER_NAME); |
||||
Loading…
Reference in new issue