Merge remote-tracking branches 'asoc/topic/of-graph', 'asoc/topic/pxa', 'asoc/topic/qcom' and 'asoc/topic/rk808' into asoc-next
Mark Brown
8 years ago
commit
2f028b15a2
@ -0,0 +1,85 @@ |
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msm8916 analog audio CODEC |
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|
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Bindings for codec Analog IP which is integrated in pmic pm8916, |
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## Bindings for codec core on pmic: |
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|
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Required properties |
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- compatible = "qcom,pm8916-wcd-analog-codec"; |
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- reg: represents the slave base address provided to the peripheral. |
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- interrupt-parent : The parent interrupt controller. |
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- interrupts: List of interrupts in given SPMI peripheral. |
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- interrupt-names: Names specified to above list of interrupts in same |
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order. List of supported interrupt names are: |
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"cdc_spk_cnp_int" - Speaker click and pop interrupt. |
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"cdc_spk_clip_int" - Speaker clip interrupt. |
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"cdc_spk_ocp_int" - Speaker over current protect interrupt. |
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"mbhc_ins_rem_det1" - jack insert removal detect interrupt 1. |
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"mbhc_but_rel_det" - button release interrupt. |
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"mbhc_but_press_det" - button press event |
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"mbhc_ins_rem_det" - jack insert removal detect interrupt. |
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"mbhc_switch_int" - multi button headset interrupt. |
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"cdc_ear_ocp_int" - Earphone over current protect interrupt. |
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"cdc_hphr_ocp_int" - Headphone R over current protect interrupt. |
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"cdc_hphl_ocp_det" - Headphone L over current protect interrupt. |
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"cdc_ear_cnp_int" - earphone cnp interrupt. |
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"cdc_hphr_cnp_int" - hphr click and pop interrupt. |
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"cdc_hphl_cnp_int" - hphl click and pop interrupt. |
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|
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- clocks: Handle to mclk. |
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- clock-names: should be "mclk" |
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- vdd-cdc-io-supply: phandle to VDD_CDC_IO regulator DT node. |
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- vdd-cdc-tx-rx-cx-supply: phandle to VDD_CDC_TX/RX/CX regulator DT node. |
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- vdd-micbias-supply: phandle of VDD_MICBIAS supply's regulator DT node. |
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|
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Optional Properties: |
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- qcom,micbias1-ext-cap: boolean, present if micbias1 has external capacitor |
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connected. |
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- qcom,micbias2-ext-cap: boolean, present if micbias2 has external capacitor |
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connected. |
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|
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Example: |
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spmi_bus { |
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... |
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audio-codec@f000{ |
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compatible = "qcom,pm8916-wcd-analog-codec"; |
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reg = <0xf000 0x200>; |
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reg-names = "pmic-codec-core"; |
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clocks = <&gcc GCC_CODEC_DIGCODEC_CLK>; |
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clock-names = "mclk"; |
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interrupt-parent = <&spmi_bus>; |
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interrupts = <0x1 0xf0 0x0 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x1 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x2 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x3 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x4 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x5 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x6 IRQ_TYPE_NONE>, |
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<0x1 0xf0 0x7 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x0 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x1 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x2 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x3 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x4 IRQ_TYPE_NONE>, |
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<0x1 0xf1 0x5 IRQ_TYPE_NONE>; |
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interrupt-names = "cdc_spk_cnp_int", |
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"cdc_spk_clip_int", |
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"cdc_spk_ocp_int", |
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"mbhc_ins_rem_det1", |
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"mbhc_but_rel_det", |
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"mbhc_but_press_det", |
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"mbhc_ins_rem_det", |
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"mbhc_switch_int", |
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"cdc_ear_ocp_int", |
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"cdc_hphr_ocp_int", |
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"cdc_hphl_ocp_det", |
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"cdc_ear_cnp_int", |
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"cdc_hphr_cnp_int", |
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"cdc_hphl_cnp_int"; |
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VDD-CDC-IO-supply = <&pm8916_l5>; |
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VDD-CDC-TX-RX-CX-supply = <&pm8916_l5>; |
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VDD-MICBIAS-supply = <&pm8916_l13>; |
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#sound-dai-cells = <1>; |
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}; |
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}; |
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@ -0,0 +1,20 @@ |
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msm8916 digital audio CODEC |
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## Bindings for codec core in lpass: |
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Required properties |
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- compatible = "qcom,msm8916-wcd-digital-codec"; |
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- reg: address space for lpass codec. |
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- clocks: Handle to mclk and ahbclk |
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- clock-names: should be "mclk", "ahbix-clk". |
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Example: |
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audio-codec@771c000{ |
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compatible = "qcom,msm8916-wcd-digital-codec"; |
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reg = <0x0771c000 0x400>; |
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clocks = <&gcc GCC_ULTAUDIO_AHBFABRIC_IXFABRIC_CLK>, |
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<&gcc GCC_CODEC_DIGCODEC_CLK>; |
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clock-names = "ahbix-clk", "mclk"; |
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#sound-dai-cells = <1>; |
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}; |
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@ -0,0 +1,890 @@ |
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#include <linux/module.h> |
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#include <linux/err.h> |
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#include <linux/kernel.h> |
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#include <linux/delay.h> |
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#include <linux/regulator/consumer.h> |
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#include <linux/types.h> |
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#include <linux/clk.h> |
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#include <linux/of.h> |
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#include <linux/platform_device.h> |
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#include <linux/regmap.h> |
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#include <sound/soc.h> |
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#include <sound/pcm.h> |
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#include <sound/pcm_params.h> |
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#include <sound/tlv.h> |
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|
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#define CDC_D_REVISION1 (0xf000) |
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#define CDC_D_PERPH_SUBTYPE (0xf005) |
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#define CDC_D_CDC_RST_CTL (0xf046) |
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#define RST_CTL_DIG_SW_RST_N_MASK BIT(7) |
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#define RST_CTL_DIG_SW_RST_N_RESET 0 |
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#define RST_CTL_DIG_SW_RST_N_REMOVE_RESET BIT(7) |
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|
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#define CDC_D_CDC_TOP_CLK_CTL (0xf048) |
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#define TOP_CLK_CTL_A_MCLK_MCLK2_EN_MASK (BIT(2) | BIT(3)) |
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#define TOP_CLK_CTL_A_MCLK_EN_ENABLE BIT(2) |
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#define TOP_CLK_CTL_A_MCLK2_EN_ENABLE BIT(3) |
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|
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#define CDC_D_CDC_ANA_CLK_CTL (0xf049) |
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#define ANA_CLK_CTL_EAR_HPHR_CLK_EN_MASK BIT(0) |
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#define ANA_CLK_CTL_EAR_HPHR_CLK_EN BIT(0) |
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#define ANA_CLK_CTL_EAR_HPHL_CLK_EN BIT(1) |
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#define ANA_CLK_CTL_SPKR_CLK_EN_MASK BIT(4) |
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#define ANA_CLK_CTL_SPKR_CLK_EN BIT(4) |
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#define ANA_CLK_CTL_TXA_CLK25_EN BIT(5) |
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|
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#define CDC_D_CDC_DIG_CLK_CTL (0xf04A) |
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#define DIG_CLK_CTL_RXD1_CLK_EN BIT(0) |
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#define DIG_CLK_CTL_RXD2_CLK_EN BIT(1) |
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#define DIG_CLK_CTL_RXD3_CLK_EN BIT(3) |
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#define DIG_CLK_CTL_TXD_CLK_EN BIT(4) |
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#define DIG_CLK_CTL_NCP_CLK_EN_MASK BIT(6) |
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#define DIG_CLK_CTL_NCP_CLK_EN BIT(6) |
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#define DIG_CLK_CTL_RXD_PDM_CLK_EN_MASK BIT(7) |
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#define DIG_CLK_CTL_RXD_PDM_CLK_EN BIT(7) |
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|
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#define CDC_D_CDC_CONN_TX1_CTL (0xf050) |
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#define CONN_TX1_SERIAL_TX1_MUX GENMASK(1, 0) |
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#define CONN_TX1_SERIAL_TX1_ADC_1 0x0 |
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#define CONN_TX1_SERIAL_TX1_RX_PDM_LB 0x1 |
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#define CONN_TX1_SERIAL_TX1_ZERO 0x2 |
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|
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#define CDC_D_CDC_CONN_TX2_CTL (0xf051) |
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#define CONN_TX2_SERIAL_TX2_MUX GENMASK(1, 0) |
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#define CONN_TX2_SERIAL_TX2_ADC_2 0x0 |
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#define CONN_TX2_SERIAL_TX2_RX_PDM_LB 0x1 |
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#define CONN_TX2_SERIAL_TX2_ZERO 0x2 |
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#define CDC_D_CDC_CONN_HPHR_DAC_CTL (0xf052) |
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#define CDC_D_CDC_CONN_RX1_CTL (0xf053) |
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#define CDC_D_CDC_CONN_RX2_CTL (0xf054) |
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#define CDC_D_CDC_CONN_RX3_CTL (0xf055) |
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#define CDC_D_CDC_CONN_RX_LB_CTL (0xf056) |
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#define CDC_D_SEC_ACCESS (0xf0D0) |
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#define CDC_D_PERPH_RESET_CTL3 (0xf0DA) |
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#define CDC_D_PERPH_RESET_CTL4 (0xf0DB) |
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#define CDC_A_REVISION1 (0xf100) |
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#define CDC_A_REVISION2 (0xf101) |
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#define CDC_A_REVISION3 (0xf102) |
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#define CDC_A_REVISION4 (0xf103) |
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#define CDC_A_PERPH_TYPE (0xf104) |
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#define CDC_A_PERPH_SUBTYPE (0xf105) |
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#define CDC_A_INT_RT_STS (0xf110) |
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#define CDC_A_INT_SET_TYPE (0xf111) |
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#define CDC_A_INT_POLARITY_HIGH (0xf112) |
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#define CDC_A_INT_POLARITY_LOW (0xf113) |
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#define CDC_A_INT_LATCHED_CLR (0xf114) |
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#define CDC_A_INT_EN_SET (0xf115) |
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#define CDC_A_INT_EN_CLR (0xf116) |
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#define CDC_A_INT_LATCHED_STS (0xf118) |
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#define CDC_A_INT_PENDING_STS (0xf119) |
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#define CDC_A_INT_MID_SEL (0xf11A) |
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#define CDC_A_INT_PRIORITY (0xf11B) |
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#define CDC_A_MICB_1_EN (0xf140) |
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#define MICB_1_EN_MICB_ENABLE BIT(7) |
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#define MICB_1_EN_BYP_CAP_MASK BIT(6) |
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#define MICB_1_EN_NO_EXT_BYP_CAP BIT(6) |
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#define MICB_1_EN_EXT_BYP_CAP 0 |
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#define MICB_1_EN_PULL_DOWN_EN_MASK BIT(5) |
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#define MICB_1_EN_PULL_DOWN_EN_ENABLE BIT(5) |
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#define MICB_1_EN_OPA_STG2_TAIL_CURR_MASK GENMASK(3, 1) |
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#define MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA (0x4) |
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#define MICB_1_EN_PULL_UP_EN_MASK BIT(4) |
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#define MICB_1_EN_TX3_GND_SEL_MASK BIT(0) |
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#define MICB_1_EN_TX3_GND_SEL_TX_GND 0 |
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|
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#define CDC_A_MICB_1_VAL (0xf141) |
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#define MICB_1_VAL_MICB_OUT_VAL_MASK GENMASK(7, 3) |
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#define MICB_1_VAL_MICB_OUT_VAL_V2P70V ((0x16) << 3) |
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#define CDC_A_MICB_1_CTL (0xf142) |
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#define MICB_1_CTL_CFILT_REF_SEL_MASK BIT(1) |
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#define MICB_1_CTL_CFILT_REF_SEL_HPF_REF BIT(1) |
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#define MICB_1_CTL_EXT_PRECHARG_EN_MASK BIT(5) |
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#define MICB_1_CTL_EXT_PRECHARG_EN_ENABLE BIT(5) |
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#define MICB_1_CTL_INT_PRECHARG_BYP_MASK BIT(6) |
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#define MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL BIT(6) |
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|
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#define CDC_A_MICB_1_INT_RBIAS (0xf143) |
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#define MICB_1_INT_TX1_INT_RBIAS_EN_MASK BIT(7) |
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#define MICB_1_INT_TX1_INT_RBIAS_EN_ENABLE BIT(7) |
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#define MICB_1_INT_TX1_INT_RBIAS_EN_DISABLE 0 |
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#define MICB_1_INT_TX1_INT_PULLUP_EN_MASK BIT(6) |
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#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(6) |
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#define MICB_1_INT_TX1_INT_PULLUP_EN_TX1N_TO_GND 0 |
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|
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#define MICB_1_INT_TX2_INT_RBIAS_EN_MASK BIT(4) |
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#define MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE BIT(4) |
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#define MICB_1_INT_TX2_INT_RBIAS_EN_DISABLE 0 |
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#define MICB_1_INT_TX2_INT_PULLUP_EN_MASK BIT(3) |
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#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(3) |
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#define MICB_1_INT_TX2_INT_PULLUP_EN_TX1N_TO_GND 0 |
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|
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#define MICB_1_INT_TX3_INT_RBIAS_EN_MASK BIT(1) |
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#define MICB_1_INT_TX3_INT_RBIAS_EN_ENABLE BIT(1) |
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#define MICB_1_INT_TX3_INT_RBIAS_EN_DISABLE 0 |
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#define MICB_1_INT_TX3_INT_PULLUP_EN_MASK BIT(0) |
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#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_MICBIAS BIT(0) |
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#define MICB_1_INT_TX3_INT_PULLUP_EN_TX1N_TO_GND 0 |
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|
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#define CDC_A_MICB_2_EN (0xf144) |
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#define CDC_A_TX_1_2_ATEST_CTL_2 (0xf145) |
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#define CDC_A_MASTER_BIAS_CTL (0xf146) |
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#define CDC_A_TX_1_EN (0xf160) |
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#define CDC_A_TX_2_EN (0xf161) |
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#define CDC_A_TX_1_2_TEST_CTL_1 (0xf162) |
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#define CDC_A_TX_1_2_TEST_CTL_2 (0xf163) |
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#define CDC_A_TX_1_2_ATEST_CTL (0xf164) |
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#define CDC_A_TX_1_2_OPAMP_BIAS (0xf165) |
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#define CDC_A_TX_3_EN (0xf167) |
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#define CDC_A_NCP_EN (0xf180) |
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#define CDC_A_NCP_CLK (0xf181) |
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#define CDC_A_NCP_FBCTRL (0xf183) |
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#define CDC_A_NCP_FBCTRL_FB_CLK_INV_MASK BIT(5) |
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#define CDC_A_NCP_FBCTRL_FB_CLK_INV BIT(5) |
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#define CDC_A_NCP_BIAS (0xf184) |
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#define CDC_A_NCP_VCTRL (0xf185) |
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#define CDC_A_NCP_TEST (0xf186) |
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#define CDC_A_NCP_CLIM_ADDR (0xf187) |
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#define CDC_A_RX_CLOCK_DIVIDER (0xf190) |
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#define CDC_A_RX_COM_OCP_CTL (0xf191) |
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#define CDC_A_RX_COM_OCP_COUNT (0xf192) |
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#define CDC_A_RX_COM_BIAS_DAC (0xf193) |
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#define RX_COM_BIAS_DAC_RX_BIAS_EN_MASK BIT(7) |
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#define RX_COM_BIAS_DAC_RX_BIAS_EN_ENABLE BIT(7) |
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#define RX_COM_BIAS_DAC_DAC_REF_EN_MASK BIT(0) |
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#define RX_COM_BIAS_DAC_DAC_REF_EN_ENABLE BIT(0) |
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|
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#define CDC_A_RX_HPH_BIAS_PA (0xf194) |
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#define CDC_A_RX_HPH_BIAS_LDO_OCP (0xf195) |
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#define CDC_A_RX_HPH_BIAS_CNP (0xf196) |
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#define CDC_A_RX_HPH_CNP_EN (0xf197) |
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#define CDC_A_RX_HPH_L_PA_DAC_CTL (0xf19B) |
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#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_MASK BIT(1) |
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#define RX_HPA_L_PA_DAC_CTL_DATA_RESET_RESET BIT(1) |
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#define CDC_A_RX_HPH_R_PA_DAC_CTL (0xf19D) |
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#define RX_HPH_R_PA_DAC_CTL_DATA_RESET BIT(1) |
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#define RX_HPH_R_PA_DAC_CTL_DATA_RESET_MASK BIT(1) |
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|
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#define CDC_A_RX_EAR_CTL (0xf19E) |
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#define RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK BIT(0) |
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#define RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE BIT(0) |
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|
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#define CDC_A_SPKR_DAC_CTL (0xf1B0) |
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#define SPKR_DAC_CTL_DAC_RESET_MASK BIT(4) |
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#define SPKR_DAC_CTL_DAC_RESET_NORMAL 0 |
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|
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#define CDC_A_SPKR_DRV_CTL (0xf1B2) |
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#define SPKR_DRV_CTL_DEF_MASK 0xEF |
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#define SPKR_DRV_CLASSD_PA_EN_MASK BIT(7) |
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#define SPKR_DRV_CLASSD_PA_EN_ENABLE BIT(7) |
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#define SPKR_DRV_CAL_EN BIT(6) |
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#define SPKR_DRV_SETTLE_EN BIT(5) |
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#define SPKR_DRV_FW_EN BIT(3) |
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#define SPKR_DRV_BOOST_SET BIT(2) |
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#define SPKR_DRV_CMFB_SET BIT(1) |
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#define SPKR_DRV_GAIN_SET BIT(0) |
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#define SPKR_DRV_CTL_DEF_VAL (SPKR_DRV_CLASSD_PA_EN_ENABLE | \ |
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SPKR_DRV_CAL_EN | SPKR_DRV_SETTLE_EN | \
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SPKR_DRV_FW_EN | SPKR_DRV_BOOST_SET | \
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SPKR_DRV_CMFB_SET | SPKR_DRV_GAIN_SET) |
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#define CDC_A_SPKR_OCP_CTL (0xf1B4) |
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#define CDC_A_SPKR_PWRSTG_CTL (0xf1B5) |
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#define SPKR_PWRSTG_CTL_DAC_EN_MASK BIT(0) |
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#define SPKR_PWRSTG_CTL_DAC_EN BIT(0) |
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#define SPKR_PWRSTG_CTL_MASK 0xE0 |
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#define SPKR_PWRSTG_CTL_BBM_MASK BIT(7) |
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#define SPKR_PWRSTG_CTL_BBM_EN BIT(7) |
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#define SPKR_PWRSTG_CTL_HBRDGE_EN_MASK BIT(6) |
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#define SPKR_PWRSTG_CTL_HBRDGE_EN BIT(6) |
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#define SPKR_PWRSTG_CTL_CLAMP_EN_MASK BIT(5) |
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#define SPKR_PWRSTG_CTL_CLAMP_EN BIT(5) |
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|
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#define CDC_A_SPKR_DRV_DBG (0xf1B7) |
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#define CDC_A_CURRENT_LIMIT (0xf1C0) |
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#define CDC_A_BOOST_EN_CTL (0xf1C3) |
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#define CDC_A_SLOPE_COMP_IP_ZERO (0xf1C4) |
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#define CDC_A_SEC_ACCESS (0xf1D0) |
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#define CDC_A_PERPH_RESET_CTL3 (0xf1DA) |
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#define CDC_A_PERPH_RESET_CTL4 (0xf1DB) |
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|
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#define MSM8916_WCD_ANALOG_RATES (SNDRV_PCM_RATE_8000 | SNDRV_PCM_RATE_16000 |\ |
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SNDRV_PCM_RATE_32000 | SNDRV_PCM_RATE_48000) |
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#define MSM8916_WCD_ANALOG_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
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SNDRV_PCM_FMTBIT_S24_LE) |
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|
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static const char * const supply_names[] = { |
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"vdd-cdc-io", |
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"vdd-cdc-tx-rx-cx", |
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}; |
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|
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struct pm8916_wcd_analog_priv { |
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u16 pmic_rev; |
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u16 codec_version; |
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struct clk *mclk; |
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struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)]; |
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bool micbias1_cap_mode; |
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bool micbias2_cap_mode; |
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}; |
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|
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static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; |
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static const char *const rdac2_mux_text[] = { "ZERO", "RX2", "RX1" }; |
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static const char *const hph_text[] = { "ZERO", "Switch", }; |
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static const struct soc_enum hph_enum = SOC_ENUM_SINGLE_VIRT( |
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ARRAY_SIZE(hph_text), hph_text); |
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|
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static const struct snd_kcontrol_new hphl_mux = SOC_DAPM_ENUM("HPHL", hph_enum); |
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static const struct snd_kcontrol_new hphr_mux = SOC_DAPM_ENUM("HPHR", hph_enum); |
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|
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/* ADC2 MUX */ |
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static const struct soc_enum adc2_enum = SOC_ENUM_SINGLE_VIRT( |
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ARRAY_SIZE(adc2_mux_text), adc2_mux_text); |
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|
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/* RDAC2 MUX */ |
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static const struct soc_enum rdac2_mux_enum = SOC_ENUM_SINGLE( |
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CDC_D_CDC_CONN_HPHR_DAC_CTL, 0, 3, rdac2_mux_text); |
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|
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static const struct snd_kcontrol_new spkr_switch[] = { |
||||
SOC_DAPM_SINGLE("Switch", CDC_A_SPKR_DAC_CTL, 7, 1, 0) |
||||
}; |
||||
|
||||
static const struct snd_kcontrol_new rdac2_mux = SOC_DAPM_ENUM( |
||||
"RDAC2 MUX Mux", rdac2_mux_enum); |
||||
static const struct snd_kcontrol_new tx_adc2_mux = SOC_DAPM_ENUM( |
||||
"ADC2 MUX Mux", adc2_enum); |
||||
|
||||
/* Analog Gain control 0 dB to +24 dB in 6 dB steps */ |
||||
static const DECLARE_TLV_DB_SCALE(analog_gain, 0, 600, 0); |
||||
|
||||
static const struct snd_kcontrol_new pm8916_wcd_analog_snd_controls[] = { |
||||
SOC_SINGLE_TLV("ADC1 Volume", CDC_A_TX_1_EN, 3, 8, 0, analog_gain), |
||||
SOC_SINGLE_TLV("ADC2 Volume", CDC_A_TX_2_EN, 3, 8, 0, analog_gain), |
||||
SOC_SINGLE_TLV("ADC3 Volume", CDC_A_TX_3_EN, 3, 8, 0, analog_gain), |
||||
}; |
||||
|
||||
static void pm8916_wcd_analog_micbias_enable(struct snd_soc_codec *codec) |
||||
{ |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, |
||||
MICB_1_CTL_EXT_PRECHARG_EN_MASK | |
||||
MICB_1_CTL_INT_PRECHARG_BYP_MASK, |
||||
MICB_1_CTL_INT_PRECHARG_BYP_EXT_PRECHRG_SEL |
||||
| MICB_1_CTL_EXT_PRECHARG_EN_ENABLE); |
||||
|
||||
snd_soc_write(codec, CDC_A_MICB_1_VAL, MICB_1_VAL_MICB_OUT_VAL_V2P70V); |
||||
/*
|
||||
* Special headset needs MICBIAS as 2.7V so wait for |
||||
* 50 msec for the MICBIAS to reach 2.7 volts. |
||||
*/ |
||||
msleep(50); |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, |
||||
MICB_1_CTL_EXT_PRECHARG_EN_MASK | |
||||
MICB_1_CTL_INT_PRECHARG_BYP_MASK, 0); |
||||
|
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_ext(struct snd_soc_codec |
||||
*codec, int event, |
||||
int reg, u32 cap_mode) |
||||
{ |
||||
switch (event) { |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
pm8916_wcd_analog_micbias_enable(codec); |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_EN, |
||||
MICB_1_EN_BYP_CAP_MASK, cap_mode); |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_int(struct snd_soc_codec |
||||
*codec, int event, |
||||
int reg, u32 cap_mode) |
||||
{ |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_PRE_PMU: |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_INT_RBIAS, |
||||
MICB_1_INT_TX2_INT_RBIAS_EN_MASK, |
||||
MICB_1_INT_TX2_INT_RBIAS_EN_ENABLE); |
||||
snd_soc_update_bits(codec, reg, MICB_1_EN_PULL_DOWN_EN_MASK, 0); |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_EN, |
||||
MICB_1_EN_OPA_STG2_TAIL_CURR_MASK, |
||||
MICB_1_EN_OPA_STG2_TAIL_CURR_1_60UA); |
||||
|
||||
break; |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
pm8916_wcd_analog_micbias_enable(codec); |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_EN, |
||||
MICB_1_EN_BYP_CAP_MASK, cap_mode); |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_ext1(struct |
||||
snd_soc_dapm_widget |
||||
*w, struct snd_kcontrol |
||||
*kcontrol, int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); |
||||
|
||||
return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg, |
||||
wcd->micbias1_cap_mode); |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_ext2(struct |
||||
snd_soc_dapm_widget |
||||
*w, struct snd_kcontrol |
||||
*kcontrol, int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); |
||||
|
||||
return pm8916_wcd_analog_enable_micbias_ext(codec, event, w->reg, |
||||
wcd->micbias2_cap_mode); |
||||
|
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_int1(struct |
||||
snd_soc_dapm_widget |
||||
*w, struct snd_kcontrol |
||||
*kcontrol, int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); |
||||
|
||||
return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg, |
||||
wcd->micbias1_cap_mode); |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_micbias_int2(struct |
||||
snd_soc_dapm_widget |
||||
*w, struct snd_kcontrol |
||||
*kcontrol, int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
struct pm8916_wcd_analog_priv *wcd = snd_soc_codec_get_drvdata(codec); |
||||
|
||||
return pm8916_wcd_analog_enable_micbias_int(codec, event, w->reg, |
||||
wcd->micbias2_cap_mode); |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_adc(struct snd_soc_dapm_widget *w, |
||||
struct snd_kcontrol *kcontrol, |
||||
int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
u16 adc_reg = CDC_A_TX_1_2_TEST_CTL_2; |
||||
u8 init_bit_shift; |
||||
|
||||
if (w->reg == CDC_A_TX_1_EN) |
||||
init_bit_shift = 5; |
||||
else |
||||
init_bit_shift = 4; |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_PRE_PMU: |
||||
if (w->reg == CDC_A_TX_2_EN) |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, |
||||
MICB_1_CTL_CFILT_REF_SEL_MASK, |
||||
MICB_1_CTL_CFILT_REF_SEL_HPF_REF); |
||||
/*
|
||||
* Add delay of 10 ms to give sufficient time for the voltage |
||||
* to shoot up and settle so that the txfe init does not |
||||
* happen when the input voltage is changing too much. |
||||
*/ |
||||
usleep_range(10000, 10010); |
||||
snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, |
||||
1 << init_bit_shift); |
||||
switch (w->reg) { |
||||
case CDC_A_TX_1_EN: |
||||
snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL, |
||||
CONN_TX1_SERIAL_TX1_MUX, |
||||
CONN_TX1_SERIAL_TX1_ADC_1); |
||||
break; |
||||
case CDC_A_TX_2_EN: |
||||
case CDC_A_TX_3_EN: |
||||
snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL, |
||||
CONN_TX2_SERIAL_TX2_MUX, |
||||
CONN_TX2_SERIAL_TX2_ADC_2); |
||||
break; |
||||
} |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
/*
|
||||
* Add delay of 12 ms before deasserting the init |
||||
* to reduce the tx pop |
||||
*/ |
||||
usleep_range(12000, 12010); |
||||
snd_soc_update_bits(codec, adc_reg, 1 << init_bit_shift, 0x00); |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMD: |
||||
switch (w->reg) { |
||||
case CDC_A_TX_1_EN: |
||||
snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX1_CTL, |
||||
CONN_TX1_SERIAL_TX1_MUX, |
||||
CONN_TX1_SERIAL_TX1_ZERO); |
||||
break; |
||||
case CDC_A_TX_2_EN: |
||||
snd_soc_update_bits(codec, CDC_A_MICB_1_CTL, |
||||
MICB_1_CTL_CFILT_REF_SEL_MASK, 0); |
||||
case CDC_A_TX_3_EN: |
||||
snd_soc_update_bits(codec, CDC_D_CDC_CONN_TX2_CTL, |
||||
CONN_TX2_SERIAL_TX2_MUX, |
||||
CONN_TX2_SERIAL_TX2_ZERO); |
||||
break; |
||||
} |
||||
|
||||
|
||||
break; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_enable_spk_pa(struct snd_soc_dapm_widget *w, |
||||
struct snd_kcontrol *kcontrol, |
||||
int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_PRE_PMU: |
||||
snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL, |
||||
SPKR_PWRSTG_CTL_DAC_EN_MASK | |
||||
SPKR_PWRSTG_CTL_BBM_MASK | |
||||
SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | |
||||
SPKR_PWRSTG_CTL_CLAMP_EN_MASK, |
||||
SPKR_PWRSTG_CTL_DAC_EN| |
||||
SPKR_PWRSTG_CTL_BBM_EN | |
||||
SPKR_PWRSTG_CTL_HBRDGE_EN | |
||||
SPKR_PWRSTG_CTL_CLAMP_EN); |
||||
|
||||
snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL, |
||||
RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, |
||||
RX_EAR_CTL_SPK_VBAT_LDO_EN_ENABLE); |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
snd_soc_update_bits(codec, CDC_A_SPKR_DRV_CTL, |
||||
SPKR_DRV_CTL_DEF_MASK, |
||||
SPKR_DRV_CTL_DEF_VAL); |
||||
snd_soc_update_bits(codec, w->reg, |
||||
SPKR_DRV_CLASSD_PA_EN_MASK, |
||||
SPKR_DRV_CLASSD_PA_EN_ENABLE); |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMD: |
||||
snd_soc_update_bits(codec, CDC_A_SPKR_PWRSTG_CTL, |
||||
SPKR_PWRSTG_CTL_DAC_EN_MASK| |
||||
SPKR_PWRSTG_CTL_BBM_MASK | |
||||
SPKR_PWRSTG_CTL_HBRDGE_EN_MASK | |
||||
SPKR_PWRSTG_CTL_CLAMP_EN_MASK, 0); |
||||
|
||||
snd_soc_update_bits(codec, CDC_A_SPKR_DAC_CTL, |
||||
SPKR_DAC_CTL_DAC_RESET_MASK, |
||||
SPKR_DAC_CTL_DAC_RESET_NORMAL); |
||||
snd_soc_update_bits(codec, CDC_A_RX_EAR_CTL, |
||||
RX_EAR_CTL_SPK_VBAT_LDO_EN_MASK, 0); |
||||
break; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static const struct reg_default wcd_reg_defaults_2_0[] = { |
||||
{CDC_A_RX_COM_OCP_CTL, 0xD1}, |
||||
{CDC_A_RX_COM_OCP_COUNT, 0xFF}, |
||||
{CDC_D_SEC_ACCESS, 0xA5}, |
||||
{CDC_D_PERPH_RESET_CTL3, 0x0F}, |
||||
{CDC_A_TX_1_2_OPAMP_BIAS, 0x4F}, |
||||
{CDC_A_NCP_FBCTRL, 0x28}, |
||||
{CDC_A_SPKR_DRV_CTL, 0x69}, |
||||
{CDC_A_SPKR_DRV_DBG, 0x01}, |
||||
{CDC_A_BOOST_EN_CTL, 0x5F}, |
||||
{CDC_A_SLOPE_COMP_IP_ZERO, 0x88}, |
||||
{CDC_A_SEC_ACCESS, 0xA5}, |
||||
{CDC_A_PERPH_RESET_CTL3, 0x0F}, |
||||
{CDC_A_CURRENT_LIMIT, 0x82}, |
||||
{CDC_A_SPKR_DAC_CTL, 0x03}, |
||||
{CDC_A_SPKR_OCP_CTL, 0xE1}, |
||||
{CDC_A_MASTER_BIAS_CTL, 0x30}, |
||||
}; |
||||
|
||||
static int pm8916_wcd_analog_probe(struct snd_soc_codec *codec) |
||||
{ |
||||
struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev); |
||||
int err, reg; |
||||
|
||||
err = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies); |
||||
if (err != 0) { |
||||
dev_err(codec->dev, "failed to enable regulators (%d)\n", err); |
||||
return err; |
||||
} |
||||
|
||||
snd_soc_codec_set_drvdata(codec, priv); |
||||
priv->pmic_rev = snd_soc_read(codec, CDC_D_REVISION1); |
||||
priv->codec_version = snd_soc_read(codec, CDC_D_PERPH_SUBTYPE); |
||||
|
||||
dev_info(codec->dev, "PMIC REV: %d\t CODEC Version: %d\n", |
||||
priv->pmic_rev, priv->codec_version); |
||||
|
||||
snd_soc_write(codec, CDC_D_PERPH_RESET_CTL4, 0x01); |
||||
snd_soc_write(codec, CDC_A_PERPH_RESET_CTL4, 0x01); |
||||
|
||||
for (reg = 0; reg < ARRAY_SIZE(wcd_reg_defaults_2_0); reg++) |
||||
snd_soc_write(codec, wcd_reg_defaults_2_0[reg].reg, |
||||
wcd_reg_defaults_2_0[reg].def); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_remove(struct snd_soc_codec *codec) |
||||
{ |
||||
struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(codec->dev); |
||||
|
||||
return regulator_bulk_disable(ARRAY_SIZE(priv->supplies), |
||||
priv->supplies); |
||||
} |
||||
|
||||
static const struct snd_soc_dapm_route pm8916_wcd_analog_audio_map[] = { |
||||
|
||||
{"PDM_RX1", NULL, "PDM Playback"}, |
||||
{"PDM_RX2", NULL, "PDM Playback"}, |
||||
{"PDM_RX3", NULL, "PDM Playback"}, |
||||
{"PDM Capture", NULL, "PDM_TX"}, |
||||
|
||||
/* ADC Connections */ |
||||
{"PDM_TX", NULL, "ADC2"}, |
||||
{"PDM_TX", NULL, "ADC3"}, |
||||
{"ADC2", NULL, "ADC2 MUX"}, |
||||
{"ADC3", NULL, "ADC2 MUX"}, |
||||
{"ADC2 MUX", "INP2", "ADC2_INP2"}, |
||||
{"ADC2 MUX", "INP3", "ADC2_INP3"}, |
||||
|
||||
{"PDM_TX", NULL, "ADC1"}, |
||||
{"ADC1", NULL, "AMIC1"}, |
||||
{"ADC2_INP2", NULL, "AMIC2"}, |
||||
{"ADC2_INP3", NULL, "AMIC3"}, |
||||
|
||||
/* RDAC Connections */ |
||||
{"HPHR DAC", NULL, "RDAC2 MUX"}, |
||||
{"RDAC2 MUX", "RX1", "PDM_RX1"}, |
||||
{"RDAC2 MUX", "RX2", "PDM_RX2"}, |
||||
{"HPHL DAC", NULL, "PDM_RX1"}, |
||||
{"PDM_RX1", NULL, "RXD1_CLK"}, |
||||
{"PDM_RX2", NULL, "RXD2_CLK"}, |
||||
{"PDM_RX3", NULL, "RXD3_CLK"}, |
||||
|
||||
{"PDM_RX1", NULL, "RXD_PDM_CLK"}, |
||||
{"PDM_RX2", NULL, "RXD_PDM_CLK"}, |
||||
{"PDM_RX3", NULL, "RXD_PDM_CLK"}, |
||||
|
||||
{"ADC1", NULL, "TXD_CLK"}, |
||||
{"ADC2", NULL, "TXD_CLK"}, |
||||
{"ADC3", NULL, "TXD_CLK"}, |
||||
|
||||
{"ADC1", NULL, "TXA_CLK25"}, |
||||
{"ADC2", NULL, "TXA_CLK25"}, |
||||
{"ADC3", NULL, "TXA_CLK25"}, |
||||
|
||||
{"PDM_RX1", NULL, "A_MCLK2"}, |
||||
{"PDM_RX2", NULL, "A_MCLK2"}, |
||||
{"PDM_RX3", NULL, "A_MCLK2"}, |
||||
|
||||
{"PDM_TX", NULL, "A_MCLK2"}, |
||||
{"A_MCLK2", NULL, "A_MCLK"}, |
||||
|
||||
/* Headset (RX MIX1 and RX MIX2) */ |
||||
{"HEADPHONE", NULL, "HPHL PA"}, |
||||
{"HEADPHONE", NULL, "HPHR PA"}, |
||||
|
||||
{"HPHL PA", NULL, "EAR_HPHL_CLK"}, |
||||
{"HPHR PA", NULL, "EAR_HPHR_CLK"}, |
||||
|
||||
{"CP", NULL, "NCP_CLK"}, |
||||
|
||||
{"HPHL PA", NULL, "HPHL"}, |
||||
{"HPHR PA", NULL, "HPHR"}, |
||||
{"HPHL PA", NULL, "CP"}, |
||||
{"HPHL PA", NULL, "RX_BIAS"}, |
||||
{"HPHR PA", NULL, "CP"}, |
||||
{"HPHR PA", NULL, "RX_BIAS"}, |
||||
{"HPHL", "Switch", "HPHL DAC"}, |
||||
{"HPHR", "Switch", "HPHR DAC"}, |
||||
|
||||
{"RX_BIAS", NULL, "DAC_REF"}, |
||||
|
||||
{"SPK_OUT", NULL, "SPK PA"}, |
||||
{"SPK PA", NULL, "RX_BIAS"}, |
||||
{"SPK PA", NULL, "SPKR_CLK"}, |
||||
{"SPK PA", NULL, "SPK DAC"}, |
||||
{"SPK DAC", "Switch", "PDM_RX3"}, |
||||
|
||||
{"MIC BIAS Internal1", NULL, "INT_LDO_H"}, |
||||
{"MIC BIAS Internal2", NULL, "INT_LDO_H"}, |
||||
{"MIC BIAS External1", NULL, "INT_LDO_H"}, |
||||
{"MIC BIAS External2", NULL, "INT_LDO_H"}, |
||||
{"MIC BIAS Internal1", NULL, "vdd-micbias"}, |
||||
{"MIC BIAS Internal2", NULL, "vdd-micbias"}, |
||||
{"MIC BIAS External1", NULL, "vdd-micbias"}, |
||||
{"MIC BIAS External2", NULL, "vdd-micbias"}, |
||||
}; |
||||
|
||||
static const struct snd_soc_dapm_widget pm8916_wcd_analog_dapm_widgets[] = { |
||||
|
||||
SND_SOC_DAPM_AIF_IN("PDM_RX1", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_IN("PDM_RX2", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_IN("PDM_RX3", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_OUT("PDM_TX", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
|
||||
SND_SOC_DAPM_INPUT("AMIC1"), |
||||
SND_SOC_DAPM_INPUT("AMIC3"), |
||||
SND_SOC_DAPM_INPUT("AMIC2"), |
||||
SND_SOC_DAPM_OUTPUT("HEADPHONE"), |
||||
|
||||
/* RX stuff */ |
||||
SND_SOC_DAPM_SUPPLY("INT_LDO_H", SND_SOC_NOPM, 1, 0, NULL, 0), |
||||
|
||||
SND_SOC_DAPM_PGA("HPHL PA", CDC_A_RX_HPH_CNP_EN, 5, 0, NULL, 0), |
||||
SND_SOC_DAPM_MUX("HPHL", SND_SOC_NOPM, 0, 0, &hphl_mux), |
||||
SND_SOC_DAPM_MIXER("HPHL DAC", CDC_A_RX_HPH_L_PA_DAC_CTL, 3, 0, NULL, |
||||
0), |
||||
SND_SOC_DAPM_PGA("HPHR PA", CDC_A_RX_HPH_CNP_EN, 4, 0, NULL, 0), |
||||
SND_SOC_DAPM_MUX("HPHR", SND_SOC_NOPM, 0, 0, &hphr_mux), |
||||
SND_SOC_DAPM_MIXER("HPHR DAC", CDC_A_RX_HPH_R_PA_DAC_CTL, 3, 0, NULL, |
||||
0), |
||||
SND_SOC_DAPM_MIXER("SPK DAC", SND_SOC_NOPM, 0, 0, |
||||
spkr_switch, ARRAY_SIZE(spkr_switch)), |
||||
|
||||
/* Speaker */ |
||||
SND_SOC_DAPM_OUTPUT("SPK_OUT"), |
||||
SND_SOC_DAPM_PGA_E("SPK PA", CDC_A_SPKR_DRV_CTL, |
||||
6, 0, NULL, 0, |
||||
pm8916_wcd_analog_enable_spk_pa, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_REGULATOR_SUPPLY("vdd-micbias", 0, 0), |
||||
SND_SOC_DAPM_SUPPLY("CP", CDC_A_NCP_EN, 0, 0, NULL, 0), |
||||
|
||||
SND_SOC_DAPM_SUPPLY("DAC_REF", CDC_A_RX_COM_BIAS_DAC, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("RX_BIAS", CDC_A_RX_COM_BIAS_DAC, 7, 0, NULL, 0), |
||||
|
||||
/* TX */ |
||||
SND_SOC_DAPM_SUPPLY("MIC BIAS Internal1", CDC_A_MICB_1_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_micbias_int1, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_SUPPLY("MIC BIAS Internal2", CDC_A_MICB_2_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_micbias_int2, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_POST_PMD), |
||||
|
||||
SND_SOC_DAPM_SUPPLY("MIC BIAS External1", CDC_A_MICB_1_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_micbias_ext1, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_SUPPLY("MIC BIAS External2", CDC_A_MICB_2_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_micbias_ext2, |
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
||||
|
||||
SND_SOC_DAPM_ADC_E("ADC1", NULL, CDC_A_TX_1_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_adc, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_ADC_E("ADC2_INP2", NULL, CDC_A_TX_2_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_adc, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_ADC_E("ADC2_INP3", NULL, CDC_A_TX_3_EN, 7, 0, |
||||
pm8916_wcd_analog_enable_adc, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_POST_PMD), |
||||
|
||||
SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
|
||||
SND_SOC_DAPM_MUX("ADC2 MUX", SND_SOC_NOPM, 0, 0, &tx_adc2_mux), |
||||
SND_SOC_DAPM_MUX("RDAC2 MUX", SND_SOC_NOPM, 0, 0, &rdac2_mux), |
||||
|
||||
/* Analog path clocks */ |
||||
SND_SOC_DAPM_SUPPLY("EAR_HPHR_CLK", CDC_D_CDC_ANA_CLK_CTL, 0, 0, NULL, |
||||
0), |
||||
SND_SOC_DAPM_SUPPLY("EAR_HPHL_CLK", CDC_D_CDC_ANA_CLK_CTL, 1, 0, NULL, |
||||
0), |
||||
SND_SOC_DAPM_SUPPLY("SPKR_CLK", CDC_D_CDC_ANA_CLK_CTL, 4, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("TXA_CLK25", CDC_D_CDC_ANA_CLK_CTL, 5, 0, NULL, 0), |
||||
|
||||
/* Digital path clocks */ |
||||
|
||||
SND_SOC_DAPM_SUPPLY("RXD1_CLK", CDC_D_CDC_DIG_CLK_CTL, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("RXD2_CLK", CDC_D_CDC_DIG_CLK_CTL, 1, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("RXD3_CLK", CDC_D_CDC_DIG_CLK_CTL, 2, 0, NULL, 0), |
||||
|
||||
SND_SOC_DAPM_SUPPLY("TXD_CLK", CDC_D_CDC_DIG_CLK_CTL, 4, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("NCP_CLK", CDC_D_CDC_DIG_CLK_CTL, 6, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("RXD_PDM_CLK", CDC_D_CDC_DIG_CLK_CTL, 7, 0, NULL, |
||||
0), |
||||
|
||||
/* System Clock source */ |
||||
SND_SOC_DAPM_SUPPLY("A_MCLK", CDC_D_CDC_TOP_CLK_CTL, 2, 0, NULL, 0), |
||||
/* TX ADC and RX DAC Clock source. */ |
||||
SND_SOC_DAPM_SUPPLY("A_MCLK2", CDC_D_CDC_TOP_CLK_CTL, 3, 0, NULL, 0), |
||||
}; |
||||
|
||||
static struct regmap *pm8916_get_regmap(struct device *dev) |
||||
{ |
||||
return dev_get_regmap(dev->parent, NULL); |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_startup(struct snd_pcm_substream *substream, |
||||
struct snd_soc_dai *dai) |
||||
{ |
||||
snd_soc_update_bits(dai->codec, CDC_D_CDC_RST_CTL, |
||||
RST_CTL_DIG_SW_RST_N_MASK, |
||||
RST_CTL_DIG_SW_RST_N_REMOVE_RESET); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void pm8916_wcd_analog_shutdown(struct snd_pcm_substream *substream, |
||||
struct snd_soc_dai *dai) |
||||
{ |
||||
snd_soc_update_bits(dai->codec, CDC_D_CDC_RST_CTL, |
||||
RST_CTL_DIG_SW_RST_N_MASK, 0); |
||||
} |
||||
|
||||
static struct snd_soc_dai_ops pm8916_wcd_analog_dai_ops = { |
||||
.startup = pm8916_wcd_analog_startup, |
||||
.shutdown = pm8916_wcd_analog_shutdown, |
||||
}; |
||||
|
||||
static struct snd_soc_dai_driver pm8916_wcd_analog_dai[] = { |
||||
[0] = { |
||||
.name = "pm8916_wcd_analog_pdm_rx", |
||||
.id = 0, |
||||
.playback = { |
||||
.stream_name = "PDM Playback", |
||||
.rates = MSM8916_WCD_ANALOG_RATES, |
||||
.formats = MSM8916_WCD_ANALOG_FORMATS, |
||||
.channels_min = 1, |
||||
.channels_max = 3, |
||||
}, |
||||
.ops = &pm8916_wcd_analog_dai_ops, |
||||
}, |
||||
[1] = { |
||||
.name = "pm8916_wcd_analog_pdm_tx", |
||||
.id = 1, |
||||
.capture = { |
||||
.stream_name = "PDM Capture", |
||||
.rates = MSM8916_WCD_ANALOG_RATES, |
||||
.formats = MSM8916_WCD_ANALOG_FORMATS, |
||||
.channels_min = 1, |
||||
.channels_max = 4, |
||||
}, |
||||
.ops = &pm8916_wcd_analog_dai_ops, |
||||
}, |
||||
}; |
||||
|
||||
static struct snd_soc_codec_driver pm8916_wcd_analog = { |
||||
.probe = pm8916_wcd_analog_probe, |
||||
.remove = pm8916_wcd_analog_remove, |
||||
.get_regmap = pm8916_get_regmap, |
||||
.component_driver = { |
||||
.controls = pm8916_wcd_analog_snd_controls, |
||||
.num_controls = ARRAY_SIZE(pm8916_wcd_analog_snd_controls), |
||||
.dapm_widgets = pm8916_wcd_analog_dapm_widgets, |
||||
.num_dapm_widgets = ARRAY_SIZE(pm8916_wcd_analog_dapm_widgets), |
||||
.dapm_routes = pm8916_wcd_analog_audio_map, |
||||
.num_dapm_routes = ARRAY_SIZE(pm8916_wcd_analog_audio_map), |
||||
}, |
||||
}; |
||||
|
||||
static int pm8916_wcd_analog_parse_dt(struct device *dev, |
||||
struct pm8916_wcd_analog_priv *priv) |
||||
{ |
||||
|
||||
if (of_property_read_bool(dev->of_node, "qcom,micbias1-ext-cap")) |
||||
priv->micbias1_cap_mode = MICB_1_EN_EXT_BYP_CAP; |
||||
else |
||||
priv->micbias1_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; |
||||
|
||||
if (of_property_read_bool(dev->of_node, "qcom,micbias2-ext-cap")) |
||||
priv->micbias2_cap_mode = MICB_1_EN_EXT_BYP_CAP; |
||||
else |
||||
priv->micbias2_cap_mode = MICB_1_EN_NO_EXT_BYP_CAP; |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_spmi_probe(struct platform_device *pdev) |
||||
{ |
||||
struct pm8916_wcd_analog_priv *priv; |
||||
struct device *dev = &pdev->dev; |
||||
int ret, i; |
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
||||
if (!priv) |
||||
return -ENOMEM; |
||||
|
||||
ret = pm8916_wcd_analog_parse_dt(dev, priv); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
priv->mclk = devm_clk_get(dev, "mclk"); |
||||
if (IS_ERR(priv->mclk)) { |
||||
dev_err(dev, "failed to get mclk\n"); |
||||
return PTR_ERR(priv->mclk); |
||||
} |
||||
|
||||
for (i = 0; i < ARRAY_SIZE(supply_names); i++) |
||||
priv->supplies[i].supply = supply_names[i]; |
||||
|
||||
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies), |
||||
priv->supplies); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to get regulator supplies %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
ret = clk_prepare_enable(priv->mclk); |
||||
if (ret < 0) { |
||||
dev_err(dev, "failed to enable mclk %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
dev_set_drvdata(dev, priv); |
||||
|
||||
return snd_soc_register_codec(dev, &pm8916_wcd_analog, |
||||
pm8916_wcd_analog_dai, |
||||
ARRAY_SIZE(pm8916_wcd_analog_dai)); |
||||
} |
||||
|
||||
static int pm8916_wcd_analog_spmi_remove(struct platform_device *pdev) |
||||
{ |
||||
struct pm8916_wcd_analog_priv *priv = dev_get_drvdata(&pdev->dev); |
||||
|
||||
snd_soc_unregister_codec(&pdev->dev); |
||||
clk_disable_unprepare(priv->mclk); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct of_device_id pm8916_wcd_analog_spmi_match_table[] = { |
||||
{ .compatible = "qcom,pm8916-wcd-analog-codec", }, |
||||
{ } |
||||
}; |
||||
|
||||
static struct platform_driver pm8916_wcd_analog_spmi_driver = { |
||||
.driver = { |
||||
.name = "qcom,pm8916-wcd-spmi-codec", |
||||
.of_match_table = pm8916_wcd_analog_spmi_match_table, |
||||
}, |
||||
.probe = pm8916_wcd_analog_spmi_probe, |
||||
.remove = pm8916_wcd_analog_spmi_remove, |
||||
}; |
||||
|
||||
module_platform_driver(pm8916_wcd_analog_spmi_driver); |
||||
|
||||
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); |
||||
MODULE_DESCRIPTION("PMIC PM8916 WCD Analog Codec driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
@ -0,0 +1,923 @@ |
||||
/* Copyright (c) 2016, The Linux Foundation. All rights reserved.
|
||||
* |
||||
* This program is free software; you can redistribute it and/or modify |
||||
* it under the terms of the GNU General Public License version 2 and |
||||
* only version 2 as published by the Free Software Foundation. |
||||
* |
||||
* This program is distributed in the hope that it will be useful, |
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of |
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
||||
* GNU General Public License for more details. |
||||
*/ |
||||
|
||||
#include <linux/module.h> |
||||
#include <linux/err.h> |
||||
#include <linux/kernel.h> |
||||
#include <linux/delay.h> |
||||
#include <linux/types.h> |
||||
#include <linux/clk.h> |
||||
#include <linux/of.h> |
||||
#include <linux/platform_device.h> |
||||
#include <linux/regmap.h> |
||||
#include <linux/mfd/syscon.h> |
||||
#include <sound/soc.h> |
||||
#include <sound/pcm.h> |
||||
#include <sound/pcm_params.h> |
||||
#include <sound/tlv.h> |
||||
|
||||
#define LPASS_CDC_CLK_RX_RESET_CTL (0x000) |
||||
#define LPASS_CDC_CLK_TX_RESET_B1_CTL (0x004) |
||||
#define CLK_RX_RESET_B1_CTL_TX1_RESET_MASK BIT(0) |
||||
#define CLK_RX_RESET_B1_CTL_TX2_RESET_MASK BIT(1) |
||||
#define LPASS_CDC_CLK_DMIC_B1_CTL (0x008) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_MASK GENMASK(3, 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV2 (0x0 << 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3 (0x1 << 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV4 (0x2 << 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV6 (0x3 << 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_SEL_DIV16 (0x4 << 1) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_EN_MASK BIT(0) |
||||
#define DMIC_B1_CTL_DMIC0_CLK_EN_ENABLE BIT(0) |
||||
|
||||
#define LPASS_CDC_CLK_RX_I2S_CTL (0x00C) |
||||
#define RX_I2S_CTL_RX_I2S_MODE_MASK BIT(5) |
||||
#define RX_I2S_CTL_RX_I2S_MODE_16 BIT(5) |
||||
#define RX_I2S_CTL_RX_I2S_MODE_32 0 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_MASK GENMASK(2, 0) |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ 0x0 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ 0x1 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ 0x2 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ 0x3 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_96_KHZ 0x4 |
||||
#define RX_I2S_CTL_RX_I2S_FS_RATE_F_192_KHZ 0x5 |
||||
#define LPASS_CDC_CLK_TX_I2S_CTL (0x010) |
||||
#define TX_I2S_CTL_TX_I2S_MODE_MASK BIT(5) |
||||
#define TX_I2S_CTL_TX_I2S_MODE_16 BIT(5) |
||||
#define TX_I2S_CTL_TX_I2S_MODE_32 0 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_MASK GENMASK(2, 0) |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ 0x0 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ 0x1 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ 0x2 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ 0x3 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_96_KHZ 0x4 |
||||
#define TX_I2S_CTL_TX_I2S_FS_RATE_F_192_KHZ 0x5 |
||||
|
||||
#define LPASS_CDC_CLK_OTHR_RESET_B1_CTL (0x014) |
||||
#define LPASS_CDC_CLK_TX_CLK_EN_B1_CTL (0x018) |
||||
#define LPASS_CDC_CLK_OTHR_CTL (0x01C) |
||||
#define LPASS_CDC_CLK_RX_B1_CTL (0x020) |
||||
#define LPASS_CDC_CLK_MCLK_CTL (0x024) |
||||
#define MCLK_CTL_MCLK_EN_MASK BIT(0) |
||||
#define MCLK_CTL_MCLK_EN_ENABLE BIT(0) |
||||
#define MCLK_CTL_MCLK_EN_DISABLE 0 |
||||
#define LPASS_CDC_CLK_PDM_CTL (0x028) |
||||
#define LPASS_CDC_CLK_PDM_CTL_PDM_EN_MASK BIT(0) |
||||
#define LPASS_CDC_CLK_PDM_CTL_PDM_EN BIT(0) |
||||
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK BIT(1) |
||||
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB BIT(1) |
||||
#define LPASS_CDC_CLK_PDM_CTL_PDM_CLK_PDM_CLK 0 |
||||
|
||||
#define LPASS_CDC_CLK_SD_CTL (0x02C) |
||||
#define LPASS_CDC_RX1_B1_CTL (0x040) |
||||
#define LPASS_CDC_RX2_B1_CTL (0x060) |
||||
#define LPASS_CDC_RX3_B1_CTL (0x080) |
||||
#define LPASS_CDC_RX1_B2_CTL (0x044) |
||||
#define LPASS_CDC_RX2_B2_CTL (0x064) |
||||
#define LPASS_CDC_RX3_B2_CTL (0x084) |
||||
#define LPASS_CDC_RX1_B3_CTL (0x048) |
||||
#define LPASS_CDC_RX2_B3_CTL (0x068) |
||||
#define LPASS_CDC_RX3_B3_CTL (0x088) |
||||
#define LPASS_CDC_RX1_B4_CTL (0x04C) |
||||
#define LPASS_CDC_RX2_B4_CTL (0x06C) |
||||
#define LPASS_CDC_RX3_B4_CTL (0x08C) |
||||
#define LPASS_CDC_RX1_B5_CTL (0x050) |
||||
#define LPASS_CDC_RX2_B5_CTL (0x070) |
||||
#define LPASS_CDC_RX3_B5_CTL (0x090) |
||||
#define LPASS_CDC_RX1_B6_CTL (0x054) |
||||
#define RXn_B6_CTL_MUTE_MASK BIT(0) |
||||
#define RXn_B6_CTL_MUTE_ENABLE BIT(0) |
||||
#define RXn_B6_CTL_MUTE_DISABLE 0 |
||||
#define LPASS_CDC_RX2_B6_CTL (0x074) |
||||
#define LPASS_CDC_RX3_B6_CTL (0x094) |
||||
#define LPASS_CDC_RX1_VOL_CTL_B1_CTL (0x058) |
||||
#define LPASS_CDC_RX2_VOL_CTL_B1_CTL (0x078) |
||||
#define LPASS_CDC_RX3_VOL_CTL_B1_CTL (0x098) |
||||
#define LPASS_CDC_RX1_VOL_CTL_B2_CTL (0x05C) |
||||
#define LPASS_CDC_RX2_VOL_CTL_B2_CTL (0x07C) |
||||
#define LPASS_CDC_RX3_VOL_CTL_B2_CTL (0x09C) |
||||
#define LPASS_CDC_TOP_GAIN_UPDATE (0x0A0) |
||||
#define LPASS_CDC_TOP_CTL (0x0A4) |
||||
#define TOP_CTL_DIG_MCLK_FREQ_MASK BIT(0) |
||||
#define TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ 0 |
||||
#define TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ BIT(0) |
||||
|
||||
#define LPASS_CDC_DEBUG_DESER1_CTL (0x0E0) |
||||
#define LPASS_CDC_DEBUG_DESER2_CTL (0x0E4) |
||||
#define LPASS_CDC_DEBUG_B1_CTL_CFG (0x0E8) |
||||
#define LPASS_CDC_DEBUG_B2_CTL_CFG (0x0EC) |
||||
#define LPASS_CDC_DEBUG_B3_CTL_CFG (0x0F0) |
||||
#define LPASS_CDC_IIR1_GAIN_B1_CTL (0x100) |
||||
#define LPASS_CDC_IIR2_GAIN_B1_CTL (0x140) |
||||
#define LPASS_CDC_IIR1_GAIN_B2_CTL (0x104) |
||||
#define LPASS_CDC_IIR2_GAIN_B2_CTL (0x144) |
||||
#define LPASS_CDC_IIR1_GAIN_B3_CTL (0x108) |
||||
#define LPASS_CDC_IIR2_GAIN_B3_CTL (0x148) |
||||
#define LPASS_CDC_IIR1_GAIN_B4_CTL (0x10C) |
||||
#define LPASS_CDC_IIR2_GAIN_B4_CTL (0x14C) |
||||
#define LPASS_CDC_IIR1_GAIN_B5_CTL (0x110) |
||||
#define LPASS_CDC_IIR2_GAIN_B5_CTL (0x150) |
||||
#define LPASS_CDC_IIR1_GAIN_B6_CTL (0x114) |
||||
#define LPASS_CDC_IIR2_GAIN_B6_CTL (0x154) |
||||
#define LPASS_CDC_IIR1_GAIN_B7_CTL (0x118) |
||||
#define LPASS_CDC_IIR2_GAIN_B7_CTL (0x158) |
||||
#define LPASS_CDC_IIR1_GAIN_B8_CTL (0x11C) |
||||
#define LPASS_CDC_IIR2_GAIN_B8_CTL (0x15C) |
||||
#define LPASS_CDC_IIR1_CTL (0x120) |
||||
#define LPASS_CDC_IIR2_CTL (0x160) |
||||
#define LPASS_CDC_IIR1_GAIN_TIMER_CTL (0x124) |
||||
#define LPASS_CDC_IIR2_GAIN_TIMER_CTL (0x164) |
||||
#define LPASS_CDC_IIR1_COEF_B1_CTL (0x128) |
||||
#define LPASS_CDC_IIR2_COEF_B1_CTL (0x168) |
||||
#define LPASS_CDC_IIR1_COEF_B2_CTL (0x12C) |
||||
#define LPASS_CDC_IIR2_COEF_B2_CTL (0x16C) |
||||
#define LPASS_CDC_CONN_RX1_B1_CTL (0x180) |
||||
#define LPASS_CDC_CONN_RX1_B2_CTL (0x184) |
||||
#define LPASS_CDC_CONN_RX1_B3_CTL (0x188) |
||||
#define LPASS_CDC_CONN_RX2_B1_CTL (0x18C) |
||||
#define LPASS_CDC_CONN_RX2_B2_CTL (0x190) |
||||
#define LPASS_CDC_CONN_RX2_B3_CTL (0x194) |
||||
#define LPASS_CDC_CONN_RX3_B1_CTL (0x198) |
||||
#define LPASS_CDC_CONN_RX3_B2_CTL (0x19C) |
||||
#define LPASS_CDC_CONN_TX_B1_CTL (0x1A0) |
||||
#define LPASS_CDC_CONN_EQ1_B1_CTL (0x1A8) |
||||
#define LPASS_CDC_CONN_EQ1_B2_CTL (0x1AC) |
||||
#define LPASS_CDC_CONN_EQ1_B3_CTL (0x1B0) |
||||
#define LPASS_CDC_CONN_EQ1_B4_CTL (0x1B4) |
||||
#define LPASS_CDC_CONN_EQ2_B1_CTL (0x1B8) |
||||
#define LPASS_CDC_CONN_EQ2_B2_CTL (0x1BC) |
||||
#define LPASS_CDC_CONN_EQ2_B3_CTL (0x1C0) |
||||
#define LPASS_CDC_CONN_EQ2_B4_CTL (0x1C4) |
||||
#define LPASS_CDC_CONN_TX_I2S_SD1_CTL (0x1C8) |
||||
#define LPASS_CDC_TX1_VOL_CTL_TIMER (0x280) |
||||
#define LPASS_CDC_TX2_VOL_CTL_TIMER (0x2A0) |
||||
#define LPASS_CDC_TX1_VOL_CTL_GAIN (0x284) |
||||
#define LPASS_CDC_TX2_VOL_CTL_GAIN (0x2A4) |
||||
#define LPASS_CDC_TX1_VOL_CTL_CFG (0x288) |
||||
#define TX_VOL_CTL_CFG_MUTE_EN_MASK BIT(0) |
||||
#define TX_VOL_CTL_CFG_MUTE_EN_ENABLE BIT(0) |
||||
|
||||
#define LPASS_CDC_TX2_VOL_CTL_CFG (0x2A8) |
||||
#define LPASS_CDC_TX1_MUX_CTL (0x28C) |
||||
#define TX_MUX_CTL_CUT_OFF_FREQ_MASK GENMASK(5, 4) |
||||
#define TX_MUX_CTL_CUT_OFF_FREQ_SHIFT 4 |
||||
#define TX_MUX_CTL_CF_NEG_3DB_4HZ (0x0 << 4) |
||||
#define TX_MUX_CTL_CF_NEG_3DB_75HZ (0x1 << 4) |
||||
#define TX_MUX_CTL_CF_NEG_3DB_150HZ (0x2 << 4) |
||||
#define TX_MUX_CTL_HPF_BP_SEL_MASK BIT(3) |
||||
#define TX_MUX_CTL_HPF_BP_SEL_BYPASS BIT(3) |
||||
#define TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS 0 |
||||
|
||||
#define LPASS_CDC_TX2_MUX_CTL (0x2AC) |
||||
#define LPASS_CDC_TX1_CLK_FS_CTL (0x290) |
||||
#define LPASS_CDC_TX2_CLK_FS_CTL (0x2B0) |
||||
#define LPASS_CDC_TX1_DMIC_CTL (0x294) |
||||
#define LPASS_CDC_TX2_DMIC_CTL (0x2B4) |
||||
#define TXN_DMIC_CTL_CLK_SEL_MASK GENMASK(2, 0) |
||||
#define TXN_DMIC_CTL_CLK_SEL_DIV2 0x0 |
||||
#define TXN_DMIC_CTL_CLK_SEL_DIV3 0x1 |
||||
#define TXN_DMIC_CTL_CLK_SEL_DIV4 0x2 |
||||
#define TXN_DMIC_CTL_CLK_SEL_DIV6 0x3 |
||||
#define TXN_DMIC_CTL_CLK_SEL_DIV16 0x4 |
||||
|
||||
#define MSM8916_WCD_DIGITAL_RATES (SNDRV_PCM_RATE_8000 | \ |
||||
SNDRV_PCM_RATE_16000 | \
|
||||
SNDRV_PCM_RATE_32000 | \
|
||||
SNDRV_PCM_RATE_48000) |
||||
#define MSM8916_WCD_DIGITAL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE |\ |
||||
SNDRV_PCM_FMTBIT_S24_LE) |
||||
|
||||
struct msm8916_wcd_digital_priv { |
||||
struct clk *ahbclk, *mclk; |
||||
}; |
||||
|
||||
static const unsigned long rx_gain_reg[] = { |
||||
LPASS_CDC_RX1_VOL_CTL_B2_CTL, |
||||
LPASS_CDC_RX2_VOL_CTL_B2_CTL, |
||||
LPASS_CDC_RX3_VOL_CTL_B2_CTL, |
||||
}; |
||||
|
||||
static const unsigned long tx_gain_reg[] = { |
||||
LPASS_CDC_TX1_VOL_CTL_GAIN, |
||||
LPASS_CDC_TX2_VOL_CTL_GAIN, |
||||
}; |
||||
|
||||
static const char *const rx_mix1_text[] = { |
||||
"ZERO", "IIR1", "IIR2", "RX1", "RX2", "RX3" |
||||
}; |
||||
|
||||
static const char *const dec_mux_text[] = { |
||||
"ZERO", "ADC1", "ADC2", "ADC3", "DMIC1", "DMIC2" |
||||
}; |
||||
static const char *const rx_mix2_text[] = { "ZERO", "IIR1", "IIR2" }; |
||||
static const char *const adc2_mux_text[] = { "ZERO", "INP2", "INP3" }; |
||||
|
||||
/* RX1 MIX1 */ |
||||
static const struct soc_enum rx_mix1_inp_enum[] = { |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 0, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B1_CTL, 3, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX1_B2_CTL, 0, 6, rx_mix1_text), |
||||
}; |
||||
|
||||
/* RX1 MIX2 */ |
||||
static const struct soc_enum rx_mix2_inp1_chain_enum = SOC_ENUM_SINGLE( |
||||
LPASS_CDC_CONN_RX1_B3_CTL, 0, 3, rx_mix2_text); |
||||
|
||||
/* RX2 MIX1 */ |
||||
static const struct soc_enum rx2_mix1_inp_enum[] = { |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 3, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX2_B1_CTL, 0, 6, rx_mix1_text), |
||||
}; |
||||
|
||||
/* RX2 MIX2 */ |
||||
static const struct soc_enum rx2_mix2_inp1_chain_enum = SOC_ENUM_SINGLE( |
||||
LPASS_CDC_CONN_RX2_B3_CTL, 0, 3, rx_mix2_text); |
||||
|
||||
/* RX3 MIX1 */ |
||||
static const struct soc_enum rx3_mix1_inp_enum[] = { |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 3, 6, rx_mix1_text), |
||||
SOC_ENUM_SINGLE(LPASS_CDC_CONN_RX3_B1_CTL, 0, 6, rx_mix1_text), |
||||
}; |
||||
|
||||
/* DEC */ |
||||
static const struct soc_enum dec1_mux_enum = SOC_ENUM_SINGLE( |
||||
LPASS_CDC_CONN_TX_B1_CTL, 0, 6, dec_mux_text); |
||||
static const struct soc_enum dec2_mux_enum = SOC_ENUM_SINGLE( |
||||
LPASS_CDC_CONN_TX_B1_CTL, 3, 6, dec_mux_text); |
||||
|
||||
/* RDAC2 MUX */ |
||||
static const struct snd_kcontrol_new dec1_mux = SOC_DAPM_ENUM( |
||||
"DEC1 MUX Mux", dec1_mux_enum); |
||||
static const struct snd_kcontrol_new dec2_mux = SOC_DAPM_ENUM( |
||||
"DEC2 MUX Mux", dec2_mux_enum); |
||||
static const struct snd_kcontrol_new rx_mix1_inp1_mux = SOC_DAPM_ENUM( |
||||
"RX1 MIX1 INP1 Mux", rx_mix1_inp_enum[0]); |
||||
static const struct snd_kcontrol_new rx_mix1_inp2_mux = SOC_DAPM_ENUM( |
||||
"RX1 MIX1 INP2 Mux", rx_mix1_inp_enum[1]); |
||||
static const struct snd_kcontrol_new rx_mix1_inp3_mux = SOC_DAPM_ENUM( |
||||
"RX1 MIX1 INP3 Mux", rx_mix1_inp_enum[2]); |
||||
static const struct snd_kcontrol_new rx2_mix1_inp1_mux = SOC_DAPM_ENUM( |
||||
"RX2 MIX1 INP1 Mux", rx2_mix1_inp_enum[0]); |
||||
static const struct snd_kcontrol_new rx2_mix1_inp2_mux = SOC_DAPM_ENUM( |
||||
"RX2 MIX1 INP2 Mux", rx2_mix1_inp_enum[1]); |
||||
static const struct snd_kcontrol_new rx2_mix1_inp3_mux = SOC_DAPM_ENUM( |
||||
"RX2 MIX1 INP3 Mux", rx2_mix1_inp_enum[2]); |
||||
static const struct snd_kcontrol_new rx3_mix1_inp1_mux = SOC_DAPM_ENUM( |
||||
"RX3 MIX1 INP1 Mux", rx3_mix1_inp_enum[0]); |
||||
static const struct snd_kcontrol_new rx3_mix1_inp2_mux = SOC_DAPM_ENUM( |
||||
"RX3 MIX1 INP2 Mux", rx3_mix1_inp_enum[1]); |
||||
static const struct snd_kcontrol_new rx3_mix1_inp3_mux = SOC_DAPM_ENUM( |
||||
"RX3 MIX1 INP3 Mux", rx3_mix1_inp_enum[2]); |
||||
|
||||
/* Digital Gain control -38.4 dB to +38.4 dB in 0.3 dB steps */ |
||||
static const DECLARE_TLV_DB_SCALE(digital_gain, -3840, 30, 0); |
||||
|
||||
/* Cutoff Freq for High Pass Filter at -3dB */ |
||||
static const char * const hpf_cutoff_text[] = { |
||||
"4Hz", "75Hz", "150Hz", |
||||
}; |
||||
|
||||
static SOC_ENUM_SINGLE_DECL(tx1_hpf_cutoff_enum, LPASS_CDC_TX1_MUX_CTL, 4, |
||||
hpf_cutoff_text); |
||||
static SOC_ENUM_SINGLE_DECL(tx2_hpf_cutoff_enum, LPASS_CDC_TX2_MUX_CTL, 4, |
||||
hpf_cutoff_text); |
||||
|
||||
/* cut off for dc blocker inside rx chain */ |
||||
static const char * const dc_blocker_cutoff_text[] = { |
||||
"4Hz", "75Hz", "150Hz", |
||||
}; |
||||
|
||||
static SOC_ENUM_SINGLE_DECL(rx1_dcb_cutoff_enum, LPASS_CDC_RX1_B4_CTL, 0, |
||||
dc_blocker_cutoff_text); |
||||
static SOC_ENUM_SINGLE_DECL(rx2_dcb_cutoff_enum, LPASS_CDC_RX2_B4_CTL, 0, |
||||
dc_blocker_cutoff_text); |
||||
static SOC_ENUM_SINGLE_DECL(rx3_dcb_cutoff_enum, LPASS_CDC_RX3_B4_CTL, 0, |
||||
dc_blocker_cutoff_text); |
||||
|
||||
static const struct snd_kcontrol_new msm8916_wcd_digital_snd_controls[] = { |
||||
SOC_SINGLE_S8_TLV("RX1 Digital Volume", LPASS_CDC_RX1_VOL_CTL_B2_CTL, |
||||
-128, 127, digital_gain), |
||||
SOC_SINGLE_S8_TLV("RX2 Digital Volume", LPASS_CDC_RX2_VOL_CTL_B2_CTL, |
||||
-128, 127, digital_gain), |
||||
SOC_SINGLE_S8_TLV("RX3 Digital Volume", LPASS_CDC_RX3_VOL_CTL_B2_CTL, |
||||
-128, 127, digital_gain), |
||||
SOC_SINGLE_S8_TLV("TX1 Digital Volume", LPASS_CDC_TX1_VOL_CTL_GAIN, |
||||
-128, 127, digital_gain), |
||||
SOC_SINGLE_S8_TLV("TX2 Digital Volume", LPASS_CDC_TX2_VOL_CTL_GAIN, |
||||
-128, 127, digital_gain), |
||||
SOC_ENUM("TX1 HPF Cutoff", tx1_hpf_cutoff_enum), |
||||
SOC_ENUM("TX2 HPF Cutoff", tx2_hpf_cutoff_enum), |
||||
SOC_SINGLE("TX1 HPF Switch", LPASS_CDC_TX1_MUX_CTL, 3, 1, 0), |
||||
SOC_SINGLE("TX2 HPF Switch", LPASS_CDC_TX2_MUX_CTL, 3, 1, 0), |
||||
SOC_ENUM("RX1 DCB Cutoff", rx1_dcb_cutoff_enum), |
||||
SOC_ENUM("RX2 DCB Cutoff", rx2_dcb_cutoff_enum), |
||||
SOC_ENUM("RX3 DCB Cutoff", rx3_dcb_cutoff_enum), |
||||
SOC_SINGLE("RX1 DCB Switch", LPASS_CDC_RX1_B5_CTL, 2, 1, 0), |
||||
SOC_SINGLE("RX2 DCB Switch", LPASS_CDC_RX2_B5_CTL, 2, 1, 0), |
||||
SOC_SINGLE("RX3 DCB Switch", LPASS_CDC_RX3_B5_CTL, 2, 1, 0), |
||||
SOC_SINGLE("RX1 Mute Switch", LPASS_CDC_RX1_B6_CTL, 0, 1, 0), |
||||
SOC_SINGLE("RX2 Mute Switch", LPASS_CDC_RX2_B6_CTL, 0, 1, 0), |
||||
SOC_SINGLE("RX3 Mute Switch", LPASS_CDC_RX3_B6_CTL, 0, 1, 0), |
||||
}; |
||||
|
||||
static int msm8916_wcd_digital_enable_interpolator( |
||||
struct snd_soc_dapm_widget *w, |
||||
struct snd_kcontrol *kcontrol, |
||||
int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
/* apply the digital gain after the interpolator is enabled */ |
||||
usleep_range(10000, 10100); |
||||
snd_soc_write(codec, rx_gain_reg[w->shift], |
||||
snd_soc_read(codec, rx_gain_reg[w->shift])); |
||||
break; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static int msm8916_wcd_digital_enable_dec(struct snd_soc_dapm_widget *w, |
||||
struct snd_kcontrol *kcontrol, |
||||
int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
unsigned int decimator = w->shift + 1; |
||||
u16 dec_reset_reg, tx_vol_ctl_reg, tx_mux_ctl_reg; |
||||
u8 dec_hpf_cut_of_freq; |
||||
|
||||
dec_reset_reg = LPASS_CDC_CLK_TX_RESET_B1_CTL; |
||||
tx_vol_ctl_reg = LPASS_CDC_TX1_VOL_CTL_CFG + 32 * (decimator - 1); |
||||
tx_mux_ctl_reg = LPASS_CDC_TX1_MUX_CTL + 32 * (decimator - 1); |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_PRE_PMU: |
||||
/* Enable TX digital mute */ |
||||
snd_soc_update_bits(codec, tx_vol_ctl_reg, |
||||
TX_VOL_CTL_CFG_MUTE_EN_MASK, |
||||
TX_VOL_CTL_CFG_MUTE_EN_ENABLE); |
||||
dec_hpf_cut_of_freq = snd_soc_read(codec, tx_mux_ctl_reg) & |
||||
TX_MUX_CTL_CUT_OFF_FREQ_MASK; |
||||
dec_hpf_cut_of_freq >>= TX_MUX_CTL_CUT_OFF_FREQ_SHIFT; |
||||
if (dec_hpf_cut_of_freq != TX_MUX_CTL_CF_NEG_3DB_150HZ) { |
||||
/* set cut of freq to CF_MIN_3DB_150HZ (0x1) */ |
||||
snd_soc_update_bits(codec, tx_mux_ctl_reg, |
||||
TX_MUX_CTL_CUT_OFF_FREQ_MASK, |
||||
TX_MUX_CTL_CF_NEG_3DB_150HZ); |
||||
} |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMU: |
||||
/* enable HPF */ |
||||
snd_soc_update_bits(codec, tx_mux_ctl_reg, |
||||
TX_MUX_CTL_HPF_BP_SEL_MASK, |
||||
TX_MUX_CTL_HPF_BP_SEL_NO_BYPASS); |
||||
/* apply the digital gain after the decimator is enabled */ |
||||
snd_soc_write(codec, tx_gain_reg[w->shift], |
||||
snd_soc_read(codec, tx_gain_reg[w->shift])); |
||||
snd_soc_update_bits(codec, tx_vol_ctl_reg, |
||||
TX_VOL_CTL_CFG_MUTE_EN_MASK, 0); |
||||
break; |
||||
case SND_SOC_DAPM_PRE_PMD: |
||||
snd_soc_update_bits(codec, tx_vol_ctl_reg, |
||||
TX_VOL_CTL_CFG_MUTE_EN_MASK, |
||||
TX_VOL_CTL_CFG_MUTE_EN_ENABLE); |
||||
snd_soc_update_bits(codec, tx_mux_ctl_reg, |
||||
TX_MUX_CTL_HPF_BP_SEL_MASK, |
||||
TX_MUX_CTL_HPF_BP_SEL_BYPASS); |
||||
break; |
||||
case SND_SOC_DAPM_POST_PMD: |
||||
snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, |
||||
1 << w->shift); |
||||
snd_soc_update_bits(codec, dec_reset_reg, 1 << w->shift, 0x0); |
||||
snd_soc_update_bits(codec, tx_mux_ctl_reg, |
||||
TX_MUX_CTL_HPF_BP_SEL_MASK, |
||||
TX_MUX_CTL_HPF_BP_SEL_BYPASS); |
||||
snd_soc_update_bits(codec, tx_vol_ctl_reg, |
||||
TX_VOL_CTL_CFG_MUTE_EN_MASK, 0); |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int msm8916_wcd_digital_enable_dmic(struct snd_soc_dapm_widget *w, |
||||
struct snd_kcontrol *kcontrol, |
||||
int event) |
||||
{ |
||||
struct snd_soc_codec *codec = snd_soc_dapm_to_codec(w->dapm); |
||||
unsigned int dmic; |
||||
int ret; |
||||
/* get dmic number out of widget name */ |
||||
char *dmic_num = strpbrk(w->name, "12"); |
||||
|
||||
if (dmic_num == NULL) { |
||||
dev_err(codec->dev, "Invalid DMIC\n"); |
||||
return -EINVAL; |
||||
} |
||||
ret = kstrtouint(dmic_num, 10, &dmic); |
||||
if (ret < 0 || dmic > 2) { |
||||
dev_err(codec->dev, "Invalid DMIC line on the codec\n"); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
switch (event) { |
||||
case SND_SOC_DAPM_PRE_PMU: |
||||
snd_soc_update_bits(codec, LPASS_CDC_CLK_DMIC_B1_CTL, |
||||
DMIC_B1_CTL_DMIC0_CLK_SEL_MASK, |
||||
DMIC_B1_CTL_DMIC0_CLK_SEL_DIV3); |
||||
switch (dmic) { |
||||
case 1: |
||||
snd_soc_update_bits(codec, LPASS_CDC_TX1_DMIC_CTL, |
||||
TXN_DMIC_CTL_CLK_SEL_MASK, |
||||
TXN_DMIC_CTL_CLK_SEL_DIV3); |
||||
break; |
||||
case 2: |
||||
snd_soc_update_bits(codec, LPASS_CDC_TX2_DMIC_CTL, |
||||
TXN_DMIC_CTL_CLK_SEL_MASK, |
||||
TXN_DMIC_CTL_CLK_SEL_DIV3); |
||||
break; |
||||
} |
||||
break; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct snd_soc_dapm_widget msm8916_wcd_digital_dapm_widgets[] = { |
||||
/*RX stuff */ |
||||
SND_SOC_DAPM_AIF_IN("I2S RX1", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_IN("I2S RX2", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_IN("I2S RX3", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
|
||||
SND_SOC_DAPM_OUTPUT("PDM_RX1"), |
||||
SND_SOC_DAPM_OUTPUT("PDM_RX2"), |
||||
SND_SOC_DAPM_OUTPUT("PDM_RX3"), |
||||
|
||||
SND_SOC_DAPM_INPUT("LPASS_PDM_TX"), |
||||
|
||||
SND_SOC_DAPM_MIXER("RX1 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_MIXER("RX2 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_MIXER("RX3 MIX1", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
|
||||
/* Interpolator */ |
||||
SND_SOC_DAPM_MIXER_E("RX1 INT", LPASS_CDC_CLK_RX_B1_CTL, 0, 0, NULL, |
||||
0, msm8916_wcd_digital_enable_interpolator, |
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_MIXER_E("RX2 INT", LPASS_CDC_CLK_RX_B1_CTL, 1, 0, NULL, |
||||
0, msm8916_wcd_digital_enable_interpolator, |
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_MIXER_E("RX3 INT", LPASS_CDC_CLK_RX_B1_CTL, 2, 0, NULL, |
||||
0, msm8916_wcd_digital_enable_interpolator, |
||||
SND_SOC_DAPM_POST_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_MUX("RX1 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
||||
&rx_mix1_inp1_mux), |
||||
SND_SOC_DAPM_MUX("RX1 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
||||
&rx_mix1_inp2_mux), |
||||
SND_SOC_DAPM_MUX("RX1 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
||||
&rx_mix1_inp3_mux), |
||||
SND_SOC_DAPM_MUX("RX2 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
||||
&rx2_mix1_inp1_mux), |
||||
SND_SOC_DAPM_MUX("RX2 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
||||
&rx2_mix1_inp2_mux), |
||||
SND_SOC_DAPM_MUX("RX2 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
||||
&rx2_mix1_inp3_mux), |
||||
SND_SOC_DAPM_MUX("RX3 MIX1 INP1", SND_SOC_NOPM, 0, 0, |
||||
&rx3_mix1_inp1_mux), |
||||
SND_SOC_DAPM_MUX("RX3 MIX1 INP2", SND_SOC_NOPM, 0, 0, |
||||
&rx3_mix1_inp2_mux), |
||||
SND_SOC_DAPM_MUX("RX3 MIX1 INP3", SND_SOC_NOPM, 0, 0, |
||||
&rx3_mix1_inp3_mux), |
||||
|
||||
/* TX */ |
||||
SND_SOC_DAPM_MIXER("ADC1", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_MIXER("ADC2", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_MIXER("ADC3", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
|
||||
SND_SOC_DAPM_MUX_E("DEC1 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 0, 0, |
||||
&dec1_mux, msm8916_wcd_digital_enable_dec, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_MUX_E("DEC2 MUX", LPASS_CDC_CLK_TX_CLK_EN_B1_CTL, 1, 0, |
||||
&dec2_mux, msm8916_wcd_digital_enable_dec, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMU | |
||||
SND_SOC_DAPM_PRE_PMD | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_AIF_OUT("I2S TX1", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_OUT("I2S TX2", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
SND_SOC_DAPM_AIF_OUT("I2S TX3", NULL, 0, SND_SOC_NOPM, 0, 0), |
||||
|
||||
/* Digital Mic Inputs */ |
||||
SND_SOC_DAPM_ADC_E("DMIC1", NULL, SND_SOC_NOPM, 0, 0, |
||||
msm8916_wcd_digital_enable_dmic, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_ADC_E("DMIC2", NULL, SND_SOC_NOPM, 0, 0, |
||||
msm8916_wcd_digital_enable_dmic, |
||||
SND_SOC_DAPM_PRE_PMU | SND_SOC_DAPM_POST_PMD), |
||||
SND_SOC_DAPM_SUPPLY("DMIC_CLK", LPASS_CDC_CLK_DMIC_B1_CTL, 0, 0, |
||||
NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("RX_I2S_CLK", LPASS_CDC_CLK_RX_I2S_CTL, |
||||
4, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("TX_I2S_CLK", LPASS_CDC_CLK_TX_I2S_CTL, 4, 0, |
||||
NULL, 0), |
||||
|
||||
SND_SOC_DAPM_SUPPLY("MCLK", SND_SOC_NOPM, 0, 0, NULL, 0), |
||||
SND_SOC_DAPM_SUPPLY("PDM_CLK", LPASS_CDC_CLK_PDM_CTL, 0, 0, NULL, 0), |
||||
/* Connectivity Clock */ |
||||
SND_SOC_DAPM_SUPPLY_S("CDC_CONN", -2, LPASS_CDC_CLK_OTHR_CTL, 2, 0, |
||||
NULL, 0), |
||||
|
||||
}; |
||||
|
||||
static int msm8916_wcd_digital_get_clks(struct platform_device *pdev, |
||||
struct msm8916_wcd_digital_priv *priv) |
||||
{ |
||||
struct device *dev = &pdev->dev; |
||||
|
||||
priv->ahbclk = devm_clk_get(dev, "ahbix-clk"); |
||||
if (IS_ERR(priv->ahbclk)) { |
||||
dev_err(dev, "failed to get ahbix clk\n"); |
||||
return PTR_ERR(priv->ahbclk); |
||||
} |
||||
|
||||
priv->mclk = devm_clk_get(dev, "mclk"); |
||||
if (IS_ERR(priv->mclk)) { |
||||
dev_err(dev, "failed to get mclk\n"); |
||||
return PTR_ERR(priv->mclk); |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int msm8916_wcd_digital_codec_probe(struct snd_soc_codec *codec) |
||||
{ |
||||
struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(codec->dev); |
||||
|
||||
snd_soc_codec_set_drvdata(codec, priv); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int msm8916_wcd_digital_hw_params(struct snd_pcm_substream *substream, |
||||
struct snd_pcm_hw_params *params, |
||||
struct snd_soc_dai *dai) |
||||
{ |
||||
u8 tx_fs_rate; |
||||
u8 rx_fs_rate; |
||||
|
||||
switch (params_rate(params)) { |
||||
case 8000: |
||||
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_8_KHZ; |
||||
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_8_KHZ; |
||||
break; |
||||
case 16000: |
||||
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_16_KHZ; |
||||
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_16_KHZ; |
||||
break; |
||||
case 32000: |
||||
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_32_KHZ; |
||||
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_32_KHZ; |
||||
break; |
||||
case 48000: |
||||
tx_fs_rate = TX_I2S_CTL_TX_I2S_FS_RATE_F_48_KHZ; |
||||
rx_fs_rate = RX_I2S_CTL_RX_I2S_FS_RATE_F_48_KHZ; |
||||
break; |
||||
default: |
||||
dev_err(dai->codec->dev, "Invalid sampling rate %d\n", |
||||
params_rate(params)); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
switch (substream->stream) { |
||||
case SNDRV_PCM_STREAM_CAPTURE: |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL, |
||||
TX_I2S_CTL_TX_I2S_FS_RATE_MASK, tx_fs_rate); |
||||
break; |
||||
case SNDRV_PCM_STREAM_PLAYBACK: |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL, |
||||
RX_I2S_CTL_RX_I2S_FS_RATE_MASK, rx_fs_rate); |
||||
break; |
||||
default: |
||||
return -EINVAL; |
||||
} |
||||
|
||||
switch (params_format(params)) { |
||||
case SNDRV_PCM_FORMAT_S16_LE: |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL, |
||||
TX_I2S_CTL_TX_I2S_MODE_MASK, |
||||
TX_I2S_CTL_TX_I2S_MODE_16); |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL, |
||||
RX_I2S_CTL_RX_I2S_MODE_MASK, |
||||
RX_I2S_CTL_RX_I2S_MODE_16); |
||||
break; |
||||
case SNDRV_PCM_FORMAT_S24_LE: |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_TX_I2S_CTL, |
||||
TX_I2S_CTL_TX_I2S_MODE_MASK, |
||||
TX_I2S_CTL_TX_I2S_MODE_32); |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_RX_I2S_CTL, |
||||
RX_I2S_CTL_RX_I2S_MODE_MASK, |
||||
RX_I2S_CTL_RX_I2S_MODE_32); |
||||
break; |
||||
default: |
||||
dev_err(dai->dev, "%s: wrong format selected\n", __func__); |
||||
return -EINVAL; |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct snd_soc_dapm_route msm8916_wcd_digital_audio_map[] = { |
||||
|
||||
{"I2S RX1", NULL, "AIF1 Playback"}, |
||||
{"I2S RX2", NULL, "AIF1 Playback"}, |
||||
{"I2S RX3", NULL, "AIF1 Playback"}, |
||||
|
||||
{"AIF1 Capture", NULL, "I2S TX1"}, |
||||
{"AIF1 Capture", NULL, "I2S TX2"}, |
||||
{"AIF1 Capture", NULL, "I2S TX3"}, |
||||
|
||||
/* Decimator Inputs */ |
||||
{"DEC1 MUX", "DMIC1", "DMIC1"}, |
||||
{"DEC1 MUX", "DMIC2", "DMIC2"}, |
||||
{"DEC1 MUX", "ADC1", "ADC1"}, |
||||
{"DEC1 MUX", "ADC2", "ADC2"}, |
||||
{"DEC1 MUX", "ADC3", "ADC3"}, |
||||
{"DEC1 MUX", NULL, "CDC_CONN"}, |
||||
|
||||
{"DEC2 MUX", "DMIC1", "DMIC1"}, |
||||
{"DEC2 MUX", "DMIC2", "DMIC2"}, |
||||
{"DEC2 MUX", "ADC1", "ADC1"}, |
||||
{"DEC2 MUX", "ADC2", "ADC2"}, |
||||
{"DEC2 MUX", "ADC3", "ADC3"}, |
||||
{"DEC2 MUX", NULL, "CDC_CONN"}, |
||||
|
||||
{"DMIC1", NULL, "DMIC_CLK"}, |
||||
{"DMIC2", NULL, "DMIC_CLK"}, |
||||
|
||||
{"I2S TX1", NULL, "DEC1 MUX"}, |
||||
{"I2S TX2", NULL, "DEC2 MUX"}, |
||||
|
||||
{"I2S TX1", NULL, "TX_I2S_CLK"}, |
||||
{"I2S TX2", NULL, "TX_I2S_CLK"}, |
||||
|
||||
{"TX_I2S_CLK", NULL, "MCLK"}, |
||||
{"TX_I2S_CLK", NULL, "PDM_CLK"}, |
||||
|
||||
{"ADC1", NULL, "LPASS_PDM_TX"}, |
||||
{"ADC2", NULL, "LPASS_PDM_TX"}, |
||||
{"ADC3", NULL, "LPASS_PDM_TX"}, |
||||
|
||||
{"I2S RX1", NULL, "RX_I2S_CLK"}, |
||||
{"I2S RX2", NULL, "RX_I2S_CLK"}, |
||||
{"I2S RX3", NULL, "RX_I2S_CLK"}, |
||||
|
||||
{"RX_I2S_CLK", NULL, "PDM_CLK"}, |
||||
{"RX_I2S_CLK", NULL, "MCLK"}, |
||||
{"RX_I2S_CLK", NULL, "CDC_CONN"}, |
||||
|
||||
/* RX1 PATH.. */ |
||||
{"PDM_RX1", NULL, "RX1 INT"}, |
||||
{"RX1 INT", NULL, "RX1 MIX1"}, |
||||
|
||||
{"RX1 MIX1", NULL, "RX1 MIX1 INP1"}, |
||||
{"RX1 MIX1", NULL, "RX1 MIX1 INP2"}, |
||||
{"RX1 MIX1", NULL, "RX1 MIX1 INP3"}, |
||||
|
||||
{"RX1 MIX1 INP1", "RX1", "I2S RX1"}, |
||||
{"RX1 MIX1 INP1", "RX2", "I2S RX2"}, |
||||
{"RX1 MIX1 INP1", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX1 MIX1 INP2", "RX1", "I2S RX1"}, |
||||
{"RX1 MIX1 INP2", "RX2", "I2S RX2"}, |
||||
{"RX1 MIX1 INP2", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX1 MIX1 INP3", "RX1", "I2S RX1"}, |
||||
{"RX1 MIX1 INP3", "RX2", "I2S RX2"}, |
||||
{"RX1 MIX1 INP3", "RX3", "I2S RX3"}, |
||||
|
||||
/* RX2 PATH */ |
||||
{"PDM_RX2", NULL, "RX2 INT"}, |
||||
{"RX2 INT", NULL, "RX2 MIX1"}, |
||||
|
||||
{"RX2 MIX1", NULL, "RX2 MIX1 INP1"}, |
||||
{"RX2 MIX1", NULL, "RX2 MIX1 INP2"}, |
||||
{"RX2 MIX1", NULL, "RX2 MIX1 INP3"}, |
||||
|
||||
{"RX2 MIX1 INP1", "RX1", "I2S RX1"}, |
||||
{"RX2 MIX1 INP1", "RX2", "I2S RX2"}, |
||||
{"RX2 MIX1 INP1", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX2 MIX1 INP2", "RX1", "I2S RX1"}, |
||||
{"RX2 MIX1 INP2", "RX2", "I2S RX2"}, |
||||
{"RX2 MIX1 INP2", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX2 MIX1 INP3", "RX1", "I2S RX1"}, |
||||
{"RX2 MIX1 INP3", "RX2", "I2S RX2"}, |
||||
{"RX2 MIX1 INP3", "RX3", "I2S RX3"}, |
||||
|
||||
/* RX3 PATH */ |
||||
{"PDM_RX3", NULL, "RX3 INT"}, |
||||
{"RX3 INT", NULL, "RX3 MIX1"}, |
||||
|
||||
{"RX3 MIX1", NULL, "RX3 MIX1 INP1"}, |
||||
{"RX3 MIX1", NULL, "RX3 MIX1 INP2"}, |
||||
{"RX3 MIX1", NULL, "RX3 MIX1 INP3"}, |
||||
|
||||
{"RX3 MIX1 INP1", "RX1", "I2S RX1"}, |
||||
{"RX3 MIX1 INP1", "RX2", "I2S RX2"}, |
||||
{"RX3 MIX1 INP1", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX3 MIX1 INP2", "RX1", "I2S RX1"}, |
||||
{"RX3 MIX1 INP2", "RX2", "I2S RX2"}, |
||||
{"RX3 MIX1 INP2", "RX3", "I2S RX3"}, |
||||
|
||||
{"RX3 MIX1 INP3", "RX1", "I2S RX1"}, |
||||
{"RX3 MIX1 INP3", "RX2", "I2S RX2"}, |
||||
{"RX3 MIX1 INP3", "RX3", "I2S RX3"}, |
||||
|
||||
}; |
||||
|
||||
static int msm8916_wcd_digital_startup(struct snd_pcm_substream *substream, |
||||
struct snd_soc_dai *dai) |
||||
{ |
||||
struct snd_soc_codec *codec = dai->codec; |
||||
struct msm8916_wcd_digital_priv *msm8916_wcd; |
||||
unsigned long mclk_rate; |
||||
|
||||
msm8916_wcd = snd_soc_codec_get_drvdata(codec); |
||||
snd_soc_update_bits(codec, LPASS_CDC_CLK_MCLK_CTL, |
||||
MCLK_CTL_MCLK_EN_MASK, |
||||
MCLK_CTL_MCLK_EN_ENABLE); |
||||
snd_soc_update_bits(codec, LPASS_CDC_CLK_PDM_CTL, |
||||
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, |
||||
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_FB); |
||||
|
||||
mclk_rate = clk_get_rate(msm8916_wcd->mclk); |
||||
switch (mclk_rate) { |
||||
case 12288000: |
||||
snd_soc_update_bits(codec, LPASS_CDC_TOP_CTL, |
||||
TOP_CTL_DIG_MCLK_FREQ_MASK, |
||||
TOP_CTL_DIG_MCLK_FREQ_F_12_288MHZ); |
||||
break; |
||||
case 9600000: |
||||
snd_soc_update_bits(codec, LPASS_CDC_TOP_CTL, |
||||
TOP_CTL_DIG_MCLK_FREQ_MASK, |
||||
TOP_CTL_DIG_MCLK_FREQ_F_9_6MHZ); |
||||
break; |
||||
default: |
||||
dev_err(codec->dev, "Invalid mclk rate %ld\n", mclk_rate); |
||||
break; |
||||
} |
||||
return 0; |
||||
} |
||||
|
||||
static void msm8916_wcd_digital_shutdown(struct snd_pcm_substream *substream, |
||||
struct snd_soc_dai *dai) |
||||
{ |
||||
snd_soc_update_bits(dai->codec, LPASS_CDC_CLK_PDM_CTL, |
||||
LPASS_CDC_CLK_PDM_CTL_PDM_CLK_SEL_MASK, 0); |
||||
} |
||||
|
||||
static struct snd_soc_dai_ops msm8916_wcd_digital_dai_ops = { |
||||
.startup = msm8916_wcd_digital_startup, |
||||
.shutdown = msm8916_wcd_digital_shutdown, |
||||
.hw_params = msm8916_wcd_digital_hw_params, |
||||
}; |
||||
|
||||
static struct snd_soc_dai_driver msm8916_wcd_digital_dai[] = { |
||||
[0] = { |
||||
.name = "msm8916_wcd_digital_i2s_rx1", |
||||
.id = 0, |
||||
.playback = { |
||||
.stream_name = "AIF1 Playback", |
||||
.rates = MSM8916_WCD_DIGITAL_RATES, |
||||
.formats = MSM8916_WCD_DIGITAL_FORMATS, |
||||
.channels_min = 1, |
||||
.channels_max = 3, |
||||
}, |
||||
.ops = &msm8916_wcd_digital_dai_ops, |
||||
}, |
||||
[1] = { |
||||
.name = "msm8916_wcd_digital_i2s_tx1", |
||||
.id = 1, |
||||
.capture = { |
||||
.stream_name = "AIF1 Capture", |
||||
.rates = MSM8916_WCD_DIGITAL_RATES, |
||||
.formats = MSM8916_WCD_DIGITAL_FORMATS, |
||||
.channels_min = 1, |
||||
.channels_max = 4, |
||||
}, |
||||
.ops = &msm8916_wcd_digital_dai_ops, |
||||
}, |
||||
}; |
||||
|
||||
static struct snd_soc_codec_driver msm8916_wcd_digital = { |
||||
.probe = msm8916_wcd_digital_codec_probe, |
||||
.component_driver = { |
||||
.controls = msm8916_wcd_digital_snd_controls, |
||||
.num_controls = ARRAY_SIZE(msm8916_wcd_digital_snd_controls), |
||||
.dapm_widgets = msm8916_wcd_digital_dapm_widgets, |
||||
.num_dapm_widgets = |
||||
ARRAY_SIZE(msm8916_wcd_digital_dapm_widgets), |
||||
.dapm_routes = msm8916_wcd_digital_audio_map, |
||||
.num_dapm_routes = ARRAY_SIZE(msm8916_wcd_digital_audio_map), |
||||
}, |
||||
}; |
||||
|
||||
static const struct regmap_config msm8916_codec_regmap_config = { |
||||
.reg_bits = 32, |
||||
.reg_stride = 4, |
||||
.val_bits = 32, |
||||
.max_register = LPASS_CDC_TX2_DMIC_CTL, |
||||
.cache_type = REGCACHE_FLAT, |
||||
}; |
||||
|
||||
static int msm8916_wcd_digital_probe(struct platform_device *pdev) |
||||
{ |
||||
struct msm8916_wcd_digital_priv *priv; |
||||
struct device *dev = &pdev->dev; |
||||
void __iomem *base; |
||||
struct resource *mem_res; |
||||
struct regmap *digital_map; |
||||
int ret; |
||||
|
||||
priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); |
||||
if (!priv) |
||||
return -ENOMEM; |
||||
|
||||
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
base = devm_ioremap_resource(&pdev->dev, mem_res); |
||||
if (IS_ERR(base)) |
||||
return PTR_ERR(base); |
||||
|
||||
digital_map = |
||||
devm_regmap_init_mmio(&pdev->dev, base, |
||||
&msm8916_codec_regmap_config); |
||||
if (IS_ERR(digital_map)) |
||||
return PTR_ERR(digital_map); |
||||
|
||||
ret = msm8916_wcd_digital_get_clks(pdev, priv); |
||||
if (ret < 0) |
||||
return ret; |
||||
|
||||
ret = clk_prepare_enable(priv->ahbclk); |
||||
if (ret < 0) { |
||||
dev_err(dev, "failed to enable ahbclk %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
ret = clk_prepare_enable(priv->mclk); |
||||
if (ret < 0) { |
||||
dev_err(dev, "failed to enable mclk %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
dev_set_drvdata(dev, priv); |
||||
|
||||
return snd_soc_register_codec(dev, &msm8916_wcd_digital, |
||||
msm8916_wcd_digital_dai, |
||||
ARRAY_SIZE(msm8916_wcd_digital_dai)); |
||||
} |
||||
|
||||
static int msm8916_wcd_digital_remove(struct platform_device *pdev) |
||||
{ |
||||
struct msm8916_wcd_digital_priv *priv = dev_get_drvdata(&pdev->dev); |
||||
|
||||
snd_soc_unregister_codec(&pdev->dev); |
||||
clk_disable_unprepare(priv->mclk); |
||||
clk_disable_unprepare(priv->ahbclk); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct of_device_id msm8916_wcd_digital_match_table[] = { |
||||
{ .compatible = "qcom,msm8916-wcd-digital-codec" }, |
||||
{ } |
||||
}; |
||||
|
||||
MODULE_DEVICE_TABLE(of, msm8916_wcd_digital_match_table); |
||||
|
||||
static struct platform_driver msm8916_wcd_digital_driver = { |
||||
.driver = { |
||||
.name = "msm8916-wcd-digital-codec", |
||||
.of_match_table = msm8916_wcd_digital_match_table, |
||||
}, |
||||
.probe = msm8916_wcd_digital_probe, |
||||
.remove = msm8916_wcd_digital_remove, |
||||
}; |
||||
|
||||
module_platform_driver(msm8916_wcd_digital_driver); |
||||
|
||||
MODULE_AUTHOR("Srinivas Kandagatla <srinivas.kandagatla@linaro.org>"); |
||||
MODULE_DESCRIPTION("MSM8916 WCD Digital Codec driver"); |
||||
MODULE_LICENSE("GPL v2"); |
||||
Loading…
Reference in new issue