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@ -18,11 +18,17 @@ |
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#define STM32F4_RCC_AHB1_GPIOJ 9 |
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#define STM32F4_RCC_AHB1_GPIOK 10 |
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#define STM32F4_RCC_AHB1_CRC 12 |
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#define STM32F4_RCC_AHB1_BKPSRAM 18 |
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#define STM32F4_RCC_AHB1_CCMDATARAM 20 |
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#define STM32F4_RCC_AHB1_DMA1 21 |
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#define STM32F4_RCC_AHB1_DMA2 22 |
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#define STM32F4_RCC_AHB1_DMA2D 23 |
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#define STM32F4_RCC_AHB1_ETHMAC 25 |
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#define STM32F4_RCC_AHB1_OTGHS 29 |
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#define STM32F4_RCC_AHB1_ETHMACTX 26 |
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#define STM32F4_RCC_AHB1_ETHMACRX 27 |
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#define STM32F4_RCC_AHB1_ETHMACPTP 28 |
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#define STM32F4_RCC_AHB1_OTGHS 29 |
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#define STM32F4_RCC_AHB1_OTGHSULPI 30 |
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#define STM32F4_AHB1_RESET(bit) (STM32F4_RCC_AHB1_##bit + (0x10 * 8)) |
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#define STM32F4_AHB1_CLOCK(bit) (STM32F4_RCC_AHB1_##bit) |
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@ -40,6 +46,7 @@ |
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/* AHB3 */ |
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#define STM32F4_RCC_AHB3_FMC 0 |
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#define STM32F4_RCC_AHB3_QSPI 1 |
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#define STM32F4_AHB3_RESET(bit) (STM32F4_RCC_AHB3_##bit + (0x18 * 8)) |
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#define STM32F4_AHB3_CLOCK(bit) (STM32F4_RCC_AHB3_##bit + 0x40) |
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@ -79,7 +86,9 @@ |
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#define STM32F4_RCC_APB2_TIM8 1 |
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#define STM32F4_RCC_APB2_USART1 4 |
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#define STM32F4_RCC_APB2_USART6 5 |
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#define STM32F4_RCC_APB2_ADC 8 |
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#define STM32F4_RCC_APB2_ADC1 8 |
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#define STM32F4_RCC_APB2_ADC2 9 |
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#define STM32F4_RCC_APB2_ADC3 10 |
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#define STM32F4_RCC_APB2_SDIO 11 |
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#define STM32F4_RCC_APB2_SPI1 12 |
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#define STM32F4_RCC_APB2_SPI4 13 |
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@ -91,6 +100,7 @@ |
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#define STM32F4_RCC_APB2_SPI6 21 |
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#define STM32F4_RCC_APB2_SAI1 22 |
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#define STM32F4_RCC_APB2_LTDC 26 |
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#define STM32F4_RCC_APB2_DSI 27 |
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#define STM32F4_APB2_RESET(bit) (STM32F4_RCC_APB2_##bit + (0x24 * 8)) |
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#define STM32F4_APB2_CLOCK(bit) (STM32F4_RCC_APB2_##bit + 0xA0) |
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