@ -2389,6 +2389,29 @@ static const unsigned int msiof3_tx_pins[] = {
static const unsigned int msiof3_tx_mux [ ] = {
MSIOF3_TXD_MARK ,
} ;
/* - QSPI ------------------------------------------------------------------- */
static const unsigned int qspi_ctrl_pins [ ] = {
/* SPCLK, SSL */
RCAR_GP_PIN ( 1 , 4 ) , RCAR_GP_PIN ( 1 , 9 ) ,
} ;
static const unsigned int qspi_ctrl_mux [ ] = {
SPCLK_MARK , SSL_MARK ,
} ;
static const unsigned int qspi_data2_pins [ ] = {
/* MOSI_IO0, MISO_IO1 */
RCAR_GP_PIN ( 1 , 5 ) , RCAR_GP_PIN ( 1 , 6 ) ,
} ;
static const unsigned int qspi_data2_mux [ ] = {
MOSI_IO0_MARK , MISO_IO1_MARK ,
} ;
static const unsigned int qspi_data4_pins [ ] = {
/* MOSI_IO0, MISO_IO1, IO2, IO3 */
RCAR_GP_PIN ( 1 , 5 ) , RCAR_GP_PIN ( 1 , 6 ) , RCAR_GP_PIN ( 1 , 7 ) ,
RCAR_GP_PIN ( 1 , 8 ) ,
} ;
static const unsigned int qspi_data4_mux [ ] = {
MOSI_IO0_MARK , MISO_IO1_MARK , IO2_MARK , IO3_MARK ,
} ;
/* - SCIF0 ------------------------------------------------------------------ */
static const unsigned int scif0_data_pins [ ] = {
/* RX, TX */
@ -3678,6 +3701,9 @@ static const struct sh_pfc_pin_group pinmux_groups[] = {
SH_PFC_PIN_GROUP ( msiof3_ss2 ) ,
SH_PFC_PIN_GROUP ( msiof3_rx ) ,
SH_PFC_PIN_GROUP ( msiof3_tx ) ,
SH_PFC_PIN_GROUP ( qspi_ctrl ) ,
SH_PFC_PIN_GROUP ( qspi_data2 ) ,
SH_PFC_PIN_GROUP ( qspi_data4 ) ,
SH_PFC_PIN_GROUP ( scif0_data ) ,
SH_PFC_PIN_GROUP ( scif0_clk ) ,
SH_PFC_PIN_GROUP ( scif0_ctrl ) ,
@ -3978,6 +4004,12 @@ static const char * const msiof3_groups[] = {
" msiof3_tx " ,
} ;
static const char * const qspi_groups [ ] = {
" qspi_ctrl " ,
" qspi_data2 " ,
" qspi_data4 " ,
} ;
static const char * const scif0_groups [ ] = {
" scif0_data " ,
" scif0_clk " ,
@ -4222,6 +4254,7 @@ static const struct sh_pfc_function pinmux_functions[] = {
SH_PFC_FUNCTION ( msiof1 ) ,
SH_PFC_FUNCTION ( msiof2 ) ,
SH_PFC_FUNCTION ( msiof3 ) ,
SH_PFC_FUNCTION ( qspi ) ,
SH_PFC_FUNCTION ( scif0 ) ,
SH_PFC_FUNCTION ( scif1 ) ,
SH_PFC_FUNCTION ( scif2 ) ,