From 1fd3e5a7ba52eb133029a6f1e54f75e686944e9e Mon Sep 17 00:00:00 2001 From: Saurabh Sahu Date: Tue, 21 Apr 2020 17:21:24 +0530 Subject: [PATCH] ARM: dts: msm: Add clock nodes and GDSC for SDM429W Add the GCC, RPMCC, GCC-MDSS and DEBUGCC node and GDSCs for SDM429W. Change-Id: I9b3c4b0c150c46d0473de82880449ff438518404 Signed-off-by: Saurabh Sahu --- arch/arm64/boot/dts/qcom/sdm429-gdsc.dtsi | 77 +++++++++++++++ arch/arm64/boot/dts/qcom/sdm429.dtsi | 113 ++++++++++++++++++++++ 2 files changed, 190 insertions(+) create mode 100644 arch/arm64/boot/dts/qcom/sdm429-gdsc.dtsi diff --git a/arch/arm64/boot/dts/qcom/sdm429-gdsc.dtsi b/arch/arm64/boot/dts/qcom/sdm429-gdsc.dtsi new file mode 100644 index 000000000000..c0d9c832381c --- /dev/null +++ b/arch/arm64/boot/dts/qcom/sdm429-gdsc.dtsi @@ -0,0 +1,77 @@ +/* + * Copyright (c) 2020, The Linux Foundation. All rights reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 and + * only version 2 as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +&soc { + venus_gdsc: qcom,gdsc@184c018 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus"; + reg = <0x184c018 0x4>; + status = "disabled"; + }; + + venus_core0_gdsc: qcom,gdsc@184c028 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_venus_core0"; + reg = <0x184c028 0x4>; + status = "disabled"; + }; + + mdss_gdsc: qcom,gdsc@184d078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_mdss"; + reg = <0x184d078 0x4>; + status = "disabled"; + }; + + jpeg_gdsc: qcom,gdsc@185701c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_jpeg"; + reg = <0x185701c 0x4>; + status = "disabled"; + }; + + vfe_gdsc: qcom,gdsc@1858034 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe"; + reg = <0x1858034 0x4>; + status = "disabled"; + }; + + vfe1_gdsc: qcom,gdsc@185806c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_vfe1"; + reg = <0x185806c 0x4>; + status = "disabled"; + }; + + cpp_gdsc: qcom,gdsc@1858078 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_cpp"; + reg = <0x1858078 0x4>; + status = "disabled"; + }; + + oxili_gx_gdsc: qcom,gdsc@185901c { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_gx"; + reg = <0x185901c 0x4>; + status = "disabled"; + }; + + oxili_cx_gdsc: qcom,gdsc@1859044 { + compatible = "qcom,gdsc"; + regulator-name = "gdsc_oxili_cx"; + reg = <0x1859044 0x4>; + status = "disabled"; + }; +}; diff --git a/arch/arm64/boot/dts/qcom/sdm429.dtsi b/arch/arm64/boot/dts/qcom/sdm429.dtsi index 023c9e7a77f7..f6d599af5db6 100644 --- a/arch/arm64/boot/dts/qcom/sdm429.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm429.dtsi @@ -13,6 +13,8 @@ #include "skeleton64.dtsi" #include +#include +#include / { model = "Qualcomm Technologies, Inc. SDM429"; @@ -214,6 +216,45 @@ }; }; + clocks { + xo_board { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <19200000>; + clock-output-names = "xo_board"; + }; + }; + + rpmcc: qcom,rpmcc { + compatible = "qcom,rpmcc-sdm429w"; + #clock-cells = <1>; + }; + + gcc: qcom,gcc@1800000 { + compatible = "qcom,gcc-sdm429w", "syscon"; + reg = <0x1800000 0x80000>; + reg-names = "cc_base"; + vdd_cx-supply = <&VDD_CX_LEVEL>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "bi_tcxo"; + #clock-cells = <1>; + #reset-cells = <1>; + }; + + debugcc: qcom,cc-debug { + compatible = "qcom,debugcc-sdm429w"; + qcom,gcc = <&gcc>; + clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>; + clock-names = "xo_clk_src"; + #clock-cells = <1>; + }; + + gcc_mdss: qcom,gcc-mdss@1800000 { + compatible = "qcom,gcc-mdss-sdm429w"; + reg = <0x1800000 0x80000>; + #clock-cells = <1>; + }; + cpu-pmu { compatible = "arm,armv8-pmuv3"; interrupts = <1 7 0xff00>; @@ -321,3 +362,75 @@ thermal_zones: thermal-zones { }; }; + +#include "sdm429-gdsc.dtsi" + +&venus_gdsc { + clock-names = "bus_clk", "core_clk"; + clocks = <&gcc GCC_VENUS0_AXI_CLK>, + <&gcc GCC_VENUS0_VCODEC0_CLK>; + status = "ok"; +}; + +&venus_core0_gdsc { + qcom,support-hw-trigger; + clock-names ="core0_clk"; + clocks = <&gcc GCC_VENUS0_CORE0_VCODEC0_CLK>; + status = "okay"; +}; + +&mdss_gdsc { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_MDSS_MDP_CLK>, + <&gcc GCC_MDSS_AXI_CLK>; + qcom,disallow-clear; + status = "okay"; +}; + +&jpeg_gdsc { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_JPEG0_CLK>, + <&gcc GCC_CAMSS_JPEG_AXI_CLK>; + status = "okay"; +}; + +&vfe_gdsc { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE0_CLK>, + <&gcc GCC_CAMSS_VFE_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE0_CLK>; + status = "okay"; +}; + +&vfe1_gdsc { + clock-names = "core_clk", "bus_clk", "micro_clk", + "csi_clk"; + clocks = <&gcc GCC_CAMSS_VFE1_CLK>, + <&gcc GCC_CAMSS_VFE1_AXI_CLK>, + <&gcc GCC_CAMSS_MICRO_AHB_CLK>, + <&gcc GCC_CAMSS_CSI_VFE1_CLK>; + status = "okay"; +}; + +&cpp_gdsc { + clock-names = "core_clk", "bus_clk"; + clocks = <&gcc GCC_CAMSS_CPP_CLK>, + <&gcc GCC_CAMSS_CPP_AXI_CLK>; + status = "okay"; +}; + +&oxili_gx_gdsc { + clock-names = "core_root_clk"; + clocks =<&gcc GFX3D_CLK_SRC>; + qcom,enable-root-clk; + qcom,clk-dis-wait-val = <0x5>; + status = "okay"; +}; + +&oxili_cx_gdsc { + clock-names = "core_clk"; + clocks = <&gcc GCC_OXILI_GFX3D_CLK>; + status = "okay"; +};