diff --git a/drivers/mmc/host/Kconfig b/drivers/mmc/host/Kconfig
index f361eed35180..f6299ddb0e85 100644
--- a/drivers/mmc/host/Kconfig
+++ b/drivers/mmc/host/Kconfig
@@ -930,3 +930,9 @@ config MMC_CQ_HCI_CRYPTO_QTI
 	 Enable Vendor Crypto Engine Support in CQHCI
 	 Enabling this allows kernel to use CQHCI crypto operations defined
 	 and implemented by QTI.
+
+config MMC_QTI_NONCMDQ_ICE
+	bool "Vendor support Legacy Inline Crypto Engine"
+	default n
+	help
+	Enable to allow use of Legacy Inline Crypto Engine i.e ICE < 3.0.
diff --git a/drivers/mmc/host/cmdq_hci-crypto-qti.c b/drivers/mmc/host/cmdq_hci-crypto-qti.c
index f16f07a0fbac..5d9b06c236b3 100644
--- a/drivers/mmc/host/cmdq_hci-crypto-qti.c
+++ b/drivers/mmc/host/cmdq_hci-crypto-qti.c
@@ -185,6 +185,63 @@ enum blk_crypto_mode_num cmdq_blk_crypto_qti_mode_num_for_alg_dusize(
 	return BLK_ENCRYPTION_MODE_INVALID;
 }
 
+#if IS_ENABLED(CONFIG_MMC_QTI_NONCMDQ_ICE)
+int cmdq_host_init_crypto_qti_spec(struct cmdq_host *host,
+				    const struct keyslot_mgmt_ll_ops *ksm_ops)
+{
+	int err = 0;
+	unsigned int crypto_modes_supported[BLK_ENCRYPTION_MODE_MAX];
+	enum blk_crypto_mode_num blk_mode_num;
+
+	host->crypto_capabilities.reg_val = LEGACY_ICE_CAP_VAL;
+	host->crypto_cfg_register = (u32)host->icemmio;
+	host->crypto_cap_array =
+		devm_kcalloc(mmc_dev(host->mmc),
+				host->crypto_capabilities.num_crypto_cap,
+				sizeof(host->crypto_cap_array[0]), GFP_KERNEL);
+	if (!host->crypto_cap_array) {
+		err = -ENOMEM;
+		pr_err("%s failed to allocate memory\n", __func__);
+		goto out;
+	}
+	memset(crypto_modes_supported, 0, sizeof(crypto_modes_supported));
+
+	host->crypto_cap_array[CRYPTO_ICE_INDEX].algorithm_id =
+		CMDQ_CRYPTO_ALG_AES_XTS;
+	host->crypto_cap_array[CRYPTO_ICE_INDEX].key_size =
+		CMDQ_CRYPTO_KEY_SIZE_256;
+
+	blk_mode_num = cmdq_blk_crypto_qti_mode_num_for_alg_dusize(
+			host->crypto_cap_array[CRYPTO_ICE_INDEX].algorithm_id,
+			host->crypto_cap_array[CRYPTO_ICE_INDEX].key_size);
+
+	crypto_modes_supported[blk_mode_num] |= CRYPTO_CDU_SIZE * 512;
+
+	host->ksm = keyslot_manager_create(cmdq_num_keyslots(host), ksm_ops,
+			BLK_CRYPTO_FEATURE_STANDARD_KEYS |
+			BLK_CRYPTO_FEATURE_WRAPPED_KEYS,
+			crypto_modes_supported, host);
+
+	if (!host->ksm) {
+		err = -ENOMEM;
+		goto out;
+	}
+	keyslot_manager_set_max_dun_bytes(host->ksm, sizeof(u32));
+
+	/*
+	 * In case host controller supports cryptographic operations
+	 * then, it uses 128bit task descriptor. Upper 64 bits of task
+	 * descriptor would be used to pass crypto specific informaton.
+	 */
+	host->caps |= CMDQ_TASK_DESC_SZ_128;
+
+	return 0;
+out:
+	/* Indicate that init failed by setting crypto_capabilities to 0 */
+	host->crypto_capabilities.reg_val = 0;
+	return err;
+}
+#else
 int cmdq_host_init_crypto_qti_spec(struct cmdq_host *host,
 				    const struct keyslot_mgmt_ll_ops *ksm_ops)
 {
@@ -266,6 +323,7 @@ out:
 	host->crypto_capabilities.reg_val = 0;
 	return err;
 }
+#endif
 
 int cmdq_crypto_qti_init_crypto(struct cmdq_host *host,
 				const struct keyslot_mgmt_ll_ops *ksm_ops)
diff --git a/drivers/mmc/host/cmdq_hci-crypto-qti.h b/drivers/mmc/host/cmdq_hci-crypto-qti.h
index b186a9aa9d8a..a8682599b384 100644
--- a/drivers/mmc/host/cmdq_hci-crypto-qti.h
+++ b/drivers/mmc/host/cmdq_hci-crypto-qti.h
@@ -15,6 +15,12 @@
 
 #include "cmdq_hci-crypto.h"
 
+#if IS_ENABLED(CONFIG_MMC_QTI_NONCMDQ_ICE)
+#define CRYPTO_CDU_SIZE 0xFF
+#define CRYPTO_ICE_INDEX 3
+#define LEGACY_ICE_CAP_VAL 0x50001F06
+#endif
+
 void cmdq_crypto_qti_enable(struct cmdq_host *host);
 
 void cmdq_crypto_qti_disable(struct cmdq_host *host);
diff --git a/drivers/soc/qcom/crypto-qti-ice-regs.h b/drivers/soc/qcom/crypto-qti-ice-regs.h
index d9e4cf2ad75f..81c98c487427 100644
--- a/drivers/soc/qcom/crypto-qti-ice-regs.h
+++ b/drivers/soc/qcom/crypto-qti-ice-regs.h
@@ -16,7 +16,11 @@
 #include <linux/io.h>
 
 /* Register bits for ICE version */
+#if IS_ENABLED(CONFIG_MMC_QTI_NONCMDQ_ICE)
+#define ICE_CORE_CURRENT_MAJOR_VERSION 0x02
+#else
 #define ICE_CORE_CURRENT_MAJOR_VERSION 0x03
+#endif
 
 #define ICE_CORE_STEP_REV_MASK		0xFFFF
 #define ICE_CORE_STEP_REV		0 /* bit 15-0 */