@ -115,6 +115,29 @@ static int ksz9021rn_phy_fixup(struct phy_device *phydev)
return 0 ;
}
static int ar8031_phy_fixup ( struct phy_device * dev )
{
u16 val ;
/* To enable AR8031 output a 125MHz clk from CLK_25M */
phy_write ( dev , 0xd , 0x7 ) ;
phy_write ( dev , 0xe , 0x8016 ) ;
phy_write ( dev , 0xd , 0x4007 ) ;
val = phy_read ( dev , 0xe ) ;
val & = 0xffe3 ;
val | = 0x18 ;
phy_write ( dev , 0xe , val ) ;
/* introduce tx clock delay */
phy_write ( dev , 0x1d , 0x5 ) ;
val = phy_read ( dev , 0x1e ) ;
val | = 0x0100 ;
phy_write ( dev , 0x1e , val ) ;
return 0 ;
}
static void __init imx6q_sabrelite_cko1_setup ( void )
{
struct clk * cko1_sel , * ahb , * cko1 ;
@ -139,11 +162,15 @@ put_clk:
clk_put ( cko1 ) ;
}
# define PHY_ID_AR8031 0x004dd074
static void __init imx6q_enet_phy_init ( void )
{
if ( IS_BUILTIN ( CONFIG_PHYLIB ) ) {
phy_register_fixup_for_uid ( PHY_ID_KSZ9021 , MICREL_PHY_ID_MASK ,
ksz9021rn_phy_fixup ) ;
phy_register_fixup_for_uid ( PHY_ID_AR8031 , 0xffffffff ,
ar8031_phy_fixup ) ;
}
}