Add mdss node and supporting dt files for qcs405 which is used by display framebuffer driver. Change-Id: Id5380ab67dde7b99b2920eac94e1bc560fd5ad77 Signed-off-by: Jayant Shekhar <jshekhar@codeaurora.org> Signed-off-by: Narender Ankam <nankam@codeaurora.org> Signed-off-by: Abhijith Desai <desaia@codeaurora.org>tirimbino
Jayant Shekhar
7 years ago
committed by
Abhijith Desai
parent
04fcfa38d4
commit
11f5d82599
@ -0,0 +1,99 @@ |
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/* Copyright (c) 2014-2018, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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&mdss_mdp { |
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dsi_hx8394d_720_vid: qcom,mdss_dsi_hx8394d_720p_video { |
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qcom,mdss-dsi-panel-name = "hx8394d 720p video mode dsi panel"; |
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qcom,mdss-dsi-panel-type = "dsi_video_mode"; |
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qcom,mdss-dsi-panel-framerate = <60>; |
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qcom,mdss-dsi-virtual-channel-id = <0>; |
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qcom,mdss-dsi-stream = <0>; |
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qcom,mdss-dsi-panel-width = <720>; |
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qcom,mdss-dsi-panel-height = <1280>; |
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qcom,mdss-dsi-h-front-porch = <52>; |
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qcom,mdss-dsi-h-back-porch = <100>; |
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qcom,mdss-dsi-h-pulse-width = <24>; |
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qcom,mdss-dsi-h-sync-skew = <0>; |
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qcom,mdss-dsi-v-back-porch = <20>; |
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qcom,mdss-dsi-v-front-porch = <8>; |
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qcom,mdss-dsi-v-pulse-width = <4>; |
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qcom,mdss-dsi-h-left-border = <0>; |
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qcom,mdss-dsi-h-right-border = <0>; |
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qcom,mdss-dsi-v-top-border = <0>; |
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qcom,mdss-dsi-v-bottom-border = <0>; |
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qcom,mdss-dsi-bpp = <24>; |
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qcom,mdss-dsi-underflow-color = <0xff>; |
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qcom,mdss-dsi-border-color = <0>; |
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qcom,mdss-dsi-on-command = [ |
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39 01 00 00 00 00 04 b9 ff 83 94 |
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39 01 00 00 00 00 03 ba 33 83 |
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39 01 00 00 00 00 10 b1 6c 12 12 |
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37 04 11 f1 80 ec 94 23 80 c0 |
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d2 18 |
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39 01 00 00 00 00 0c b2 00 64 0e |
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0d 32 23 08 08 1c 4d 00 |
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39 01 00 00 00 00 0d b4 00 ff 03 |
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50 03 50 03 50 01 6a 01 6a |
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39 01 00 00 00 00 02 bc 07 |
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39 01 00 00 00 00 04 bf 41 0e 01 |
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39 01 00 00 00 00 1f d3 00 07 00 |
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00 00 10 00 32 10 05 00 00 32 |
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10 00 00 00 32 10 00 00 00 36 |
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03 09 09 37 00 00 37 |
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39 01 00 00 00 00 2d d5 02 03 00 |
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01 06 07 04 05 20 21 22 23 18 |
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18 18 18 18 18 18 18 18 18 18 |
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18 18 18 18 18 18 18 18 18 18 |
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18 18 18 18 18 24 25 18 18 19 |
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19 |
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39 01 00 00 00 00 2d d6 05 04 07 |
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06 01 00 03 02 23 22 21 20 18 |
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18 18 18 18 18 58 58 18 18 18 |
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18 18 18 18 18 18 18 18 18 18 |
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18 18 18 18 18 25 24 19 19 18 |
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18 |
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39 01 00 00 00 00 02 cc 09 |
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39 01 00 00 00 00 03 c0 30 14 |
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39 01 00 00 00 00 05 c7 00 c0 40 c0 |
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39 01 00 00 00 00 03 b6 43 43 |
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05 01 00 00 c8 00 02 11 00 |
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05 01 00 00 0a 00 02 29 00 |
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]; |
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qcom,mdss-dsi-off-command = [05 01 00 00 00 00 02 28 00 |
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05 01 00 00 00 00 02 10 00]; |
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qcom,mdss-dsi-on-command-state = "dsi_lp_mode"; |
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qcom,mdss-dsi-off-command-state = "dsi_hs_mode"; |
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qcom,mdss-dsi-h-sync-pulse = <1>; |
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qcom,mdss-dsi-traffic-mode = "burst_mode"; |
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qcom,mdss-dsi-bllp-eof-power-mode; |
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qcom,mdss-dsi-bllp-power-mode; |
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qcom,mdss-dsi-lane-0-state; |
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qcom,mdss-dsi-lane-1-state; |
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qcom,mdss-dsi-lane-2-state; |
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qcom,mdss-dsi-lane-3-state; |
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qcom,mdss-dsi-panel-timings = [ |
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79 1a 12 00 3e 42 |
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16 1e 15 03 04 00 |
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]; |
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qcom,mdss-dsi-t-clk-post = <0x04>; |
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qcom,mdss-dsi-t-clk-pre = <0x1b>; |
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qcom,mdss-dsi-bl-min-level = <1>; |
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qcom,mdss-dsi-bl-max-level = <4095>; |
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qcom,mdss-dsi-dma-trigger = "trigger_sw"; |
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qcom,mdss-dsi-mdp-trigger = "none"; |
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qcom,mdss-dsi-bl-pmic-control-type = "bl_ctrl_wled"; |
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qcom,mdss-dsi-reset-sequence = <1 20>, <0 1>, <1 20>; |
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qcom,mdss-pan-physical-width-dimension = <59>; |
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qcom,mdss-pan-physical-height-dimension = <104>; |
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|
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}; |
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}; |
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@ -0,0 +1,30 @@ |
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/* Copyright (c) 2018, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include "dsi-panel-hx8394d-720p-video.dtsi" |
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|
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&soc { |
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dsi_panel_pwr_supply: dsi_panel_pwr_supply { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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qcom,panel-supply-entry@0 { |
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reg = <1>; |
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qcom,supply-name = "vddio"; |
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qcom,supply-min-voltage = <1704000>; |
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qcom,supply-max-voltage = <1896000>; |
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qcom,supply-enable-load = <100000>; |
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qcom,supply-disable-load = <100>; |
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}; |
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|
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}; |
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}; |
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@ -0,0 +1,332 @@ |
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/* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 and |
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* only version 2 as published by the Free Software Foundation. |
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* |
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* This program is distributed in the hope that it will be useful, |
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* but WITHOUT ANY WARRANTY; without even the implied warranty of |
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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* GNU General Public License for more details. |
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*/ |
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|
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#include <dt-bindings/clock/mdss-28nm-pll-clk.h> |
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|
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&soc { |
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mdss_mdp: qcom,mdss_mdp@1a00000 { |
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compatible = "qcom,mdss_mdp"; |
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reg = <0x01a00000 0x90000>, |
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<0x01ab0000 0x1040>; |
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reg-names = "mdp_phys", "vbif_phys"; |
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interrupts = <0 72 0>; |
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vdd-supply = <&gdsc_mdss>; |
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|
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/* Bus Scale Settings */ |
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qcom,msm-bus,name = "mdss_mdp"; |
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qcom,msm-bus,num-cases = <3>; |
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qcom,msm-bus,num-paths = <1>; |
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qcom,msm-bus,vectors-KBps = |
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<22 512 0 0>, |
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<22 512 0 6400000>, |
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<22 512 0 6400000>; |
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|
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/* Fudge factors */ |
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qcom,mdss-ab-factor = <1 1>; /* 1 time */ |
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qcom,mdss-ib-factor = <1 1>; /* 1 time */ |
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qcom,mdss-clk-factor = <105 100>; /* 1.05 times */ |
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|
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qcom,max-mixer-width = <2048>; |
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qcom,max-pipe-width = <2048>; |
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|
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/* VBIF QoS remapper settings*/ |
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qcom,mdss-vbif-qos-rt-setting = <1 2 2 2>; |
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qcom,mdss-vbif-qos-nrt-setting = <1 1 1 1>; |
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|
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qcom,mdss-has-panic-ctrl; |
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qcom,mdss-per-pipe-panic-luts = <0x000f>, |
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<0x0>, |
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<0xfffc>, |
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<0x0>; |
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|
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qcom,mdss-mdp-reg-offset = <0x00001000>; |
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qcom,max-bandwidth-low-kbps = <1800000>; |
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qcom,max-bandwidth-high-kbps = <1800000>; |
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qcom,max-bandwidth-per-pipe-kbps = <1000000>; |
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|
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/* Bandwidth limit settings */ |
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qcom,max-bw-settings = <1 3100000>, /* Default */ |
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<2 1700000>; /* Camera */ |
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|
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qcom,max-clk-rate = <320000000>; |
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qcom,mdss-default-ot-rd-limit = <32>; |
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qcom,mdss-default-ot-wr-limit = <16>; |
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|
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qcom,mdss-pipe-vig-off = <0x00005000>; |
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qcom,mdss-pipe-rgb-off = <0x00015000 0x00017000>; |
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qcom,mdss-pipe-dma-off = <0x00025000>; |
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qcom,mdss-pipe-cursor-off = <0x00035000>; |
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|
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qcom,mdss-pipe-vig-xin-id = <0>; |
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qcom,mdss-pipe-rgb-xin-id = <1 5>; |
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qcom,mdss-pipe-dma-xin-id = <2>; |
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qcom,mdss-pipe-cursor-xin-id = <7>; |
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|
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/* Offsets relative to "mdp_phys + mdp-reg-offset" address */ |
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qcom,mdss-pipe-vig-clk-ctrl-offsets = <0x2AC 0 0>; |
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qcom,mdss-pipe-rgb-clk-ctrl-offsets = <0x2AC 4 8>, |
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<0x2B4 4 8>; |
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qcom,mdss-pipe-dma-clk-ctrl-offsets = <0x2AC 8 12>; |
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qcom,mdss-pipe-cursor-clk-ctrl-offsets = <0x3A8 16 15>; |
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|
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|
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qcom,mdss-ctl-off = <0x00002000 0x00002200 0x00002400 |
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0x00002600 0x00002800>; |
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qcom,mdss-mixer-intf-off = <0x00045000 0x00046000>; |
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qcom,mdss-dspp-off = <0x00055000>; |
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qcom,mdss-wb-off = <0x00066000>; |
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qcom,mdss-intf-off = <0x00000000 0x0006B800 |
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0x00000000 0x0006C800>; |
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qcom,mdss-pingpong-off = <0x00071000 0x00071800>; |
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qcom,mdss-wfd-mode = "intf"; |
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qcom,mdss-has-decimation; |
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qcom,mdss-has-non-scalar-rgb; |
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qcom,mdss-has-rotator-downscale; |
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qcom,mdss-rot-downscale-min = <2>; |
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qcom,mdss-rot-downscale-max = <16>; |
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qcom,mdss-idle-power-collapse-enabled; |
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qcom,mdss-rot-block-size = <64>; |
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clocks = <&clock_gcc GCC_MDSS_AHB_CLK>, |
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<&clock_gcc GCC_MDSS_AXI_CLK>, |
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<&clock_gcc GCC_MDSS_MDP_CLK>, |
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<&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, |
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<&clock_gcc GCC_MDSS_VSYNC_CLK>, |
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<&clock_gcc GCC_BIMC_MDSS_CLK>; |
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clock-names = "iface_clk", "bus_clk", "core_clk_src", |
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"core_clk", "vsync_clk", "bimc_clk"; |
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|
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qcom,mdp-settings = <0x0506c 0x00000000>, |
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<0x1506c 0x00000000>, |
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<0x1706c 0x00000000>, |
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<0x2506c 0x00000000>; |
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|
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qcom,regs-dump-mdp = <0x01000 0x01454>, |
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<0x02000 0x02064>, |
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<0x02200 0x02264>, |
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<0x02400 0x02464>, |
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<0x05000 0x05150>, |
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<0x05200 0x05230>, |
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<0x15000 0x15150>, |
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<0x17000 0x17150>, |
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<0x25000 0x25150>, |
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<0x35000 0x35150>, |
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<0x45000 0x452bc>, |
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<0x46000 0x462bc>, |
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<0x55000 0x5522c>, |
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<0x65000 0x652c0>, |
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<0x66000 0x662c0>, |
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<0x6b800 0x6ba68>, |
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<0x6c800 0x6c268>, |
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<0x71000 0x710d4>, |
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<0x71800 0x718d4>; |
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qcom,regs-dump-names-mdp = "MDP", |
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"CTL_0", "CTL_1", "CTL_2", |
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"VIG0_SSPP", "VIG0", |
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"RGB0_SSPP", "RGB1_SSPP", |
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"DMA0_SSPP", |
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"CURSOR0_SSPP", |
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"LAYER_0", "LAYER_1", |
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"DSPP_0", |
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"WB_0", "WB_2", |
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"INTF_1", "INTF_3", |
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"PP_0", "PP_1"; |
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|
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/* buffer parameters to calculate prefill bandwidth */ |
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qcom,mdss-prefill-outstanding-buffer-bytes = <0>; |
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qcom,mdss-prefill-y-buffer-bytes = <0>; |
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qcom,mdss-prefill-scaler-buffer-lines-bilinear = <2>; |
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qcom,mdss-prefill-scaler-buffer-lines-caf = <4>; |
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qcom,mdss-prefill-post-scaler-buffer-pixels = <2048>; |
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qcom,mdss-prefill-pingpong-buffer-pixels = <4096>; |
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qcom,mdss-pp-offsets { |
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qcom,mdss-sspp-mdss-igc-lut-off = <0x2000>; |
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qcom,mdss-sspp-vig-pcc-off = <0x1780>; |
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qcom,mdss-sspp-rgb-pcc-off = <0x380>; |
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qcom,mdss-sspp-dma-pcc-off = <0x380>; |
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qcom,mdss-lm-pgc-off = <0x3C0>; |
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qcom,mdss-dspp-pcc-off = <0x1700>; |
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qcom,mdss-dspp-pgc-off = <0x17C0>; |
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}; |
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qcom,mdss-reg-bus { |
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/* Reg Bus Scale Settings */ |
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qcom,msm-bus,name = "mdss_reg"; |
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qcom,msm-bus,num-cases = <4>; |
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qcom,msm-bus,num-paths = <1>; |
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qcom,msm-bus,active-only; |
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qcom,msm-bus,vectors-KBps = |
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<1 590 0 0>, |
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<1 590 0 76800>, |
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<1 590 0 160000>, |
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<1 590 0 320000>; |
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}; |
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|
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qcom,mdss-hw-rt-bus { |
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/* Bus Scale Settings */ |
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qcom,msm-bus,name = "mdss_hw_rt"; |
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qcom,msm-bus,num-cases = <2>; |
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qcom,msm-bus,num-paths = <1>; |
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qcom,msm-bus,vectors-KBps = |
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<22 512 0 0>, |
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<22 512 0 1000>; |
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}; |
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|
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smmu_mdp_unsec: qcom,smmu_mdp_unsec_cb { |
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compatible = "qcom,smmu_mdp_unsec"; |
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iommus = <&apps_smmu 0xC00 0>; /* For NS ctx bank */ |
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}; |
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|
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mdss_fb0: qcom,mdss_fb_primary { |
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cell-index = <0>; |
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compatible = "qcom,mdss-fb"; |
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}; |
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|
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mdss_fb1: qcom,mdss_fb_wfd { |
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cell-index = <1>; |
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compatible = "qcom,mdss-fb"; |
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}; |
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|
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mdss_fb2: qcom,mdss_fb_secondary { |
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cell-index = <2>; |
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compatible = "qcom,mdss-fb"; |
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}; |
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}; |
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|
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mdss_dsi: qcom,mdss_dsi@0 { |
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compatible = "qcom,mdss-dsi"; |
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hw-config = "single_dsi"; |
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#address-cells = <1>; |
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#size-cells = <1>; |
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gdsc-supply = <&gdsc_mdss>; |
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vdda-1p2-supply = <&pms405_l4>; |
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vdda-1p8-supply = <&pms405_l5>; |
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|
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/* Bus Scale Settings */ |
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qcom,msm-bus,name = "mdss_dsi"; |
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qcom,msm-bus,num-cases = <2>; |
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qcom,msm-bus,num-paths = <1>; |
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qcom,msm-bus,vectors-KBps = |
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<22 512 0 0>, |
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<22 512 0 1000>; |
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|
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ranges = <0x1a94000 0x1a94000 0x300 |
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0x1a94400 0x1a94400 0x280 |
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0x1a94b80 0x1a94b80 0x30 |
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0x193e000 0x193e000 0x30 |
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0x1a96000 0x1a96000 0x300 |
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0x1a96400 0x1a96400 0x280 |
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0x1a96b80 0x1a96b80 0x30 |
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0x193e000 0x193e000 0x30>; |
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|
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clocks = <&clock_gcc_mdss MDSS_MDP_VOTE_CLK>, |
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<&clock_gcc GCC_MDSS_AHB_CLK>, |
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<&clock_gcc GCC_MDSS_AXI_CLK>, |
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<&mdss_dsi0_pll BYTECLK_SRC_0_CLK>, |
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<&mdss_dsi0_pll PCLK_SRC_0_CLK>; |
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clock-names = "mdp_core_clk", "iface_clk", "bus_clk", |
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"ext_byte0_clk", "ext_pixel0_clk"; |
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|
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qcom,mmss-ulp-clamp-ctrl-offset = <0x20>; |
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qcom,mmss-phyreset-ctrl-offset = <0x24>; |
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|
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qcom,mdss-fb-map-prim = <&mdss_fb0>; |
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qcom,mdss-fb-map-sec = <&mdss_fb2>; |
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/*qcom,mdss-fb-map = <&mdss_fb0>;*/ |
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qcom,core-supply-entries { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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qcom,core-supply-entry@0 { |
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reg = <0>; |
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qcom,supply-name = "gdsc"; |
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qcom,supply-min-voltage = <0>; |
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qcom,supply-max-voltage = <0>; |
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qcom,supply-enable-load = <0>; |
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qcom,supply-disable-load = <0>; |
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}; |
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}; |
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|
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qcom,ctrl-supply-entries { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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qcom,ctrl-supply-entry@0 { |
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reg = <0>; |
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qcom,supply-name = "vdda-1p2"; |
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qcom,supply-min-voltage = <1200000>; |
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qcom,supply-max-voltage = <1200000>; |
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qcom,supply-enable-load = <100000>; |
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qcom,supply-disable-load = <100>; |
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qcom,supply-post-on-sleep = <20>; |
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}; |
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}; |
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|
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qcom,phy-supply-entries { |
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#address-cells = <1>; |
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#size-cells = <0>; |
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|
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qcom,phy-supply-entry@0 { |
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reg = <0>; |
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qcom,supply-name = "vdda-1p8"; |
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qcom,supply-min-voltage = <1800000>; |
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qcom,supply-max-voltage = <1800000>; |
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qcom,supply-enable-load = <100000>; |
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qcom,supply-disable-load = <100>; |
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}; |
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}; |
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|
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mdss_dsi0: qcom,mdss_dsi_ctrl0@1a94000 { |
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compatible = "qcom,mdss-dsi-ctrl"; |
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label = "MDSS DSI CTRL->0"; |
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cell-index = <0>; |
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reg = <0x1a94000 0x300>, |
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<0x1a94400 0x280>, |
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<0x1a94b80 0x30>, |
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<0x193e000 0x30>; |
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reg-names = "dsi_ctrl", "dsi_phy", |
||||
"dsi_phy_regulator", "mmss_misc_phys"; |
||||
|
||||
qcom,timing-db-mode; |
||||
qcom,mdss-mdp = <&mdss_mdp>; |
||||
vddio-supply = <&pms405_l6>; |
||||
|
||||
clocks = <&clock_gcc_mdss GCC_MDSS_BYTE0_CLK>, |
||||
<&clock_gcc_mdss GCC_MDSS_PCLK0_CLK>, |
||||
<&clock_gcc GCC_MDSS_ESC0_CLK>, |
||||
<&clock_gcc_mdss BYTE0_CLK_SRC>, |
||||
<&clock_gcc_mdss PCLK0_CLK_SRC>; |
||||
clock-names = "byte_clk", "pixel_clk", "core_clk", |
||||
"byte_clk_rcg", "pixel_clk_rcg"; |
||||
|
||||
qcom,platform-strength-ctrl = [ff 06]; |
||||
qcom,platform-bist-ctrl = [00 00 b1 ff 00 00]; |
||||
qcom,platform-regulator-settings = [03 08 07 00 |
||||
20 07 01]; |
||||
qcom,platform-lane-config = [01 c0 00 00 00 00 00 01 97 |
||||
01 c0 00 00 05 00 00 01 97 |
||||
01 c0 00 00 0a 00 00 01 97 |
||||
01 c0 00 00 0f 00 00 01 97 |
||||
00 40 00 00 00 00 00 01 ff]; |
||||
}; |
||||
}; |
||||
|
||||
qcom,mdss_wb_panel { |
||||
compatible = "qcom,mdss_wb"; |
||||
qcom,mdss_pan_res = <640 640>; |
||||
qcom,mdss_pan_bpp = <24>; |
||||
qcom,mdss-fb-map = <&mdss_fb1>; |
||||
}; |
||||
|
||||
}; |
||||
Loading…
Reference in new issue