@ -2924,16 +2924,11 @@ struct clk tegra_list_clks[] = {
PERIPH_CLK ( " i2c3 " , " tegra-i2c.2 " , NULL , 67 , 0x1b8 , 26000000 , mux_pllp_clkm , MUX | DIV_U16 | PERIPH_ON_APB ) ,
PERIPH_CLK ( " i2c4 " , " tegra-i2c.3 " , NULL , 103 , 0x3c4 , 26000000 , mux_pllp_clkm , MUX | DIV_U16 | PERIPH_ON_APB ) ,
PERIPH_CLK ( " i2c5 " , " tegra-i2c.4 " , NULL , 47 , 0x128 , 26000000 , mux_pllp_clkm , MUX | DIV_U16 | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarta " , " tegra_uart.0 " , NULL , 6 , 0x178 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartb " , " tegra_uart.1 " , NULL , 7 , 0x17c , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartc " , " tegra_uart.2 " , NULL , 55 , 0x1a0 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartd " , " tegra_uart.3 " , NULL , 65 , 0x1c0 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarte " , " tegra_uart.4 " , NULL , 66 , 0x1c4 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarta_dbg " , " serial8250.0 " , " uarta " , 6 , 0x178 , 800000000 , mux_pllp_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartb_dbg " , " serial8250.0 " , " uartb " , 7 , 0x17c , 800000000 , mux_pllp_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartc_dbg " , " serial8250.0 " , " uartc " , 55 , 0x1a0 , 800000000 , mux_pllp_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartd_dbg " , " serial8250.0 " , " uartd " , 65 , 0x1c0 , 800000000 , mux_pllp_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarte_dbg " , " serial8250.0 " , " uarte " , 66 , 0x1c4 , 800000000 , mux_pllp_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarta " , " tegra-uart.0 " , NULL , 6 , 0x178 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartb " , " tegra-uart.1 " , NULL , 7 , 0x17c , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartc " , " tegra-uart.2 " , NULL , 55 , 0x1a0 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uartd " , " tegra-uart.3 " , NULL , 65 , 0x1c0 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK ( " uarte " , " tegra-uart.4 " , NULL , 66 , 0x1c4 , 800000000 , mux_pllp_pllc_pllm_clkm , MUX | DIV_U71 | DIV_U71_UART | PERIPH_ON_APB ) ,
PERIPH_CLK_EX ( " vi " , " tegra_camera " , " vi " , 20 , 0x148 , 425000000 , mux_pllm_pllc_pllp_plla , MUX | DIV_U71 | DIV_U71_INT , & tegra_vi_clk_ops ) ,
PERIPH_CLK ( " 3d " , " 3d " , NULL , 24 , 0x158 , 520000000 , mux_pllm_pllc_pllp_plla , MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET ) ,
PERIPH_CLK ( " 3d2 " , " 3d2 " , NULL , 98 , 0x3b0 , 520000000 , mux_pllm_pllc_pllp_plla , MUX | DIV_U71 | DIV_U71_INT | DIV_U71_IDLE | PERIPH_MANUAL_RESET ) ,
@ -2983,6 +2978,11 @@ struct clk tegra_list_clks[] = {
* table under two names .
*/
struct clk_duplicate tegra_clk_duplicates [ ] = {
CLK_DUPLICATE ( " uarta " , " serial8250.0 " , NULL ) ,
CLK_DUPLICATE ( " uartb " , " serial8250.1 " , NULL ) ,
CLK_DUPLICATE ( " uartc " , " serial8250.2 " , NULL ) ,
CLK_DUPLICATE ( " uartd " , " serial8250.3 " , NULL ) ,
CLK_DUPLICATE ( " uarte " , " serial8250.4 " , NULL ) ,
CLK_DUPLICATE ( " usbd " , " utmip-pad " , NULL ) ,
CLK_DUPLICATE ( " usbd " , " tegra-ehci.0 " , NULL ) ,
CLK_DUPLICATE ( " usbd " , " tegra-otg " , NULL ) ,