Merge remote-tracking branches 'spi/topic/armada', 'spi/topic/ath79', 'spi/topic/atmel' and 'spi/topic/axi' into spi-next
Mark Brown
8 years ago
commit
0afa0724df
@ -0,0 +1,25 @@ |
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* Marvell Armada 3700 SPI Controller |
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|
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Required Properties: |
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|
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- compatible: should be "marvell,armada-3700-spi" |
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- reg: physical base address of the controller and length of memory mapped |
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region. |
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- interrupts: The interrupt number. The interrupt specifier format depends on |
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the interrupt controller and of its driver. |
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- clocks: Must contain the clock source, usually from the North Bridge clocks. |
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- num-cs: The number of chip selects that is supported by this SPI Controller |
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- #address-cells: should be 1. |
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- #size-cells: should be 0. |
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|
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Example: |
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|
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spi0: spi@10600 { |
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compatible = "marvell,armada-3700-spi"; |
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#address-cells = <1>; |
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#size-cells = <0>; |
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reg = <0x10600 0x5d>; |
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clocks = <&nb_perih_clk 7>; |
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interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>; |
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num-cs = <4>; |
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}; |
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@ -0,0 +1,923 @@ |
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/*
|
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* Marvell Armada-3700 SPI controller driver |
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* |
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* Copyright (C) 2016 Marvell Ltd. |
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* |
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* Author: Wilson Ding <dingwei@marvell.com> |
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* Author: Romain Perier <romain.perier@free-electrons.com> |
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* |
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* This program is free software; you can redistribute it and/or modify |
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* it under the terms of the GNU General Public License version 2 as |
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* published by the Free Software Foundation. |
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*/ |
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|
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#include <linux/clk.h> |
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#include <linux/completion.h> |
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#include <linux/delay.h> |
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#include <linux/err.h> |
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#include <linux/interrupt.h> |
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#include <linux/io.h> |
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#include <linux/kernel.h> |
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#include <linux/module.h> |
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#include <linux/of.h> |
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#include <linux/of_irq.h> |
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#include <linux/of_device.h> |
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#include <linux/pinctrl/consumer.h> |
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#include <linux/spi/spi.h> |
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|
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#define DRIVER_NAME "armada_3700_spi" |
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|
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#define A3700_SPI_TIMEOUT 10 |
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|
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/* SPI Register Offest */ |
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#define A3700_SPI_IF_CTRL_REG 0x00 |
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#define A3700_SPI_IF_CFG_REG 0x04 |
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#define A3700_SPI_DATA_OUT_REG 0x08 |
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#define A3700_SPI_DATA_IN_REG 0x0C |
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#define A3700_SPI_IF_INST_REG 0x10 |
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#define A3700_SPI_IF_ADDR_REG 0x14 |
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#define A3700_SPI_IF_RMODE_REG 0x18 |
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#define A3700_SPI_IF_HDR_CNT_REG 0x1C |
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#define A3700_SPI_IF_DIN_CNT_REG 0x20 |
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#define A3700_SPI_IF_TIME_REG 0x24 |
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#define A3700_SPI_INT_STAT_REG 0x28 |
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#define A3700_SPI_INT_MASK_REG 0x2C |
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|
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/* A3700_SPI_IF_CTRL_REG */ |
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#define A3700_SPI_EN BIT(16) |
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#define A3700_SPI_ADDR_NOT_CONFIG BIT(12) |
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#define A3700_SPI_WFIFO_OVERFLOW BIT(11) |
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#define A3700_SPI_WFIFO_UNDERFLOW BIT(10) |
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#define A3700_SPI_RFIFO_OVERFLOW BIT(9) |
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#define A3700_SPI_RFIFO_UNDERFLOW BIT(8) |
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#define A3700_SPI_WFIFO_FULL BIT(7) |
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#define A3700_SPI_WFIFO_EMPTY BIT(6) |
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#define A3700_SPI_RFIFO_FULL BIT(5) |
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#define A3700_SPI_RFIFO_EMPTY BIT(4) |
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#define A3700_SPI_WFIFO_RDY BIT(3) |
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#define A3700_SPI_RFIFO_RDY BIT(2) |
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#define A3700_SPI_XFER_RDY BIT(1) |
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#define A3700_SPI_XFER_DONE BIT(0) |
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|
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/* A3700_SPI_IF_CFG_REG */ |
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#define A3700_SPI_WFIFO_THRS BIT(28) |
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#define A3700_SPI_RFIFO_THRS BIT(24) |
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#define A3700_SPI_AUTO_CS BIT(20) |
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#define A3700_SPI_DMA_RD_EN BIT(18) |
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#define A3700_SPI_FIFO_MODE BIT(17) |
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#define A3700_SPI_SRST BIT(16) |
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#define A3700_SPI_XFER_START BIT(15) |
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#define A3700_SPI_XFER_STOP BIT(14) |
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#define A3700_SPI_INST_PIN BIT(13) |
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#define A3700_SPI_ADDR_PIN BIT(12) |
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#define A3700_SPI_DATA_PIN1 BIT(11) |
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#define A3700_SPI_DATA_PIN0 BIT(10) |
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#define A3700_SPI_FIFO_FLUSH BIT(9) |
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#define A3700_SPI_RW_EN BIT(8) |
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#define A3700_SPI_CLK_POL BIT(7) |
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#define A3700_SPI_CLK_PHA BIT(6) |
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#define A3700_SPI_BYTE_LEN BIT(5) |
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#define A3700_SPI_CLK_PRESCALE BIT(0) |
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#define A3700_SPI_CLK_PRESCALE_MASK (0x1f) |
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|
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#define A3700_SPI_WFIFO_THRS_BIT 28 |
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#define A3700_SPI_RFIFO_THRS_BIT 24 |
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#define A3700_SPI_FIFO_THRS_MASK 0x7 |
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|
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#define A3700_SPI_DATA_PIN_MASK 0x3 |
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|
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/* A3700_SPI_IF_HDR_CNT_REG */ |
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#define A3700_SPI_DUMMY_CNT_BIT 12 |
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#define A3700_SPI_DUMMY_CNT_MASK 0x7 |
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#define A3700_SPI_RMODE_CNT_BIT 8 |
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#define A3700_SPI_RMODE_CNT_MASK 0x3 |
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#define A3700_SPI_ADDR_CNT_BIT 4 |
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#define A3700_SPI_ADDR_CNT_MASK 0x7 |
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#define A3700_SPI_INSTR_CNT_BIT 0 |
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#define A3700_SPI_INSTR_CNT_MASK 0x3 |
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|
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/* A3700_SPI_IF_TIME_REG */ |
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#define A3700_SPI_CLK_CAPT_EDGE BIT(7) |
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|
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/* Flags and macros for struct a3700_spi */ |
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#define A3700_INSTR_CNT 1 |
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#define A3700_ADDR_CNT 3 |
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#define A3700_DUMMY_CNT 1 |
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|
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struct a3700_spi { |
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struct spi_master *master; |
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void __iomem *base; |
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struct clk *clk; |
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unsigned int irq; |
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unsigned int flags; |
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bool xmit_data; |
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const u8 *tx_buf; |
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u8 *rx_buf; |
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size_t buf_len; |
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u8 byte_len; |
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u32 wait_mask; |
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struct completion done; |
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u32 addr_cnt; |
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u32 instr_cnt; |
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size_t hdr_cnt; |
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}; |
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|
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static u32 spireg_read(struct a3700_spi *a3700_spi, u32 offset) |
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{ |
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return readl(a3700_spi->base + offset); |
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} |
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|
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static void spireg_write(struct a3700_spi *a3700_spi, u32 offset, u32 data) |
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{ |
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writel(data, a3700_spi->base + offset); |
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} |
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|
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static void a3700_spi_auto_cs_unset(struct a3700_spi *a3700_spi) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~A3700_SPI_AUTO_CS; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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|
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static void a3700_spi_activate_cs(struct a3700_spi *a3700_spi, unsigned int cs) |
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{ |
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u32 val; |
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|
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val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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val |= (A3700_SPI_EN << cs); |
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spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); |
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} |
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|
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static void a3700_spi_deactivate_cs(struct a3700_spi *a3700_spi, |
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unsigned int cs) |
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{ |
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u32 val; |
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|
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val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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val &= ~(A3700_SPI_EN << cs); |
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spireg_write(a3700_spi, A3700_SPI_IF_CTRL_REG, val); |
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} |
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|
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static int a3700_spi_pin_mode_set(struct a3700_spi *a3700_spi, |
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unsigned int pin_mode) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~(A3700_SPI_INST_PIN | A3700_SPI_ADDR_PIN); |
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val &= ~(A3700_SPI_DATA_PIN0 | A3700_SPI_DATA_PIN1); |
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switch (pin_mode) { |
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case 1: |
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break; |
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case 2: |
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val |= A3700_SPI_DATA_PIN0; |
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break; |
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case 4: |
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val |= A3700_SPI_DATA_PIN1; |
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break; |
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default: |
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dev_err(&a3700_spi->master->dev, "wrong pin mode %u", pin_mode); |
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return -EINVAL; |
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} |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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return 0; |
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} |
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|
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static void a3700_spi_fifo_mode_set(struct a3700_spi *a3700_spi) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val |= A3700_SPI_FIFO_MODE; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_mode_set(struct a3700_spi *a3700_spi, |
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unsigned int mode_bits) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (mode_bits & SPI_CPOL) |
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val |= A3700_SPI_CLK_POL; |
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else |
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val &= ~A3700_SPI_CLK_POL; |
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if (mode_bits & SPI_CPHA) |
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val |= A3700_SPI_CLK_PHA; |
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else |
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val &= ~A3700_SPI_CLK_PHA; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_clock_set(struct a3700_spi *a3700_spi, |
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unsigned int speed_hz, u16 mode) |
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{ |
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u32 val; |
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u32 prescale; |
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prescale = DIV_ROUND_UP(clk_get_rate(a3700_spi->clk), speed_hz); |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val = val & ~A3700_SPI_CLK_PRESCALE_MASK; |
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val = val | (prescale & A3700_SPI_CLK_PRESCALE_MASK); |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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if (prescale <= 2) { |
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val = spireg_read(a3700_spi, A3700_SPI_IF_TIME_REG); |
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val |= A3700_SPI_CLK_CAPT_EDGE; |
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spireg_write(a3700_spi, A3700_SPI_IF_TIME_REG, val); |
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} |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~(A3700_SPI_CLK_POL | A3700_SPI_CLK_PHA); |
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if (mode & SPI_CPOL) |
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val |= A3700_SPI_CLK_POL; |
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if (mode & SPI_CPHA) |
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val |= A3700_SPI_CLK_PHA; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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static void a3700_spi_bytelen_set(struct a3700_spi *a3700_spi, unsigned int len) |
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{ |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (len == 4) |
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val |= A3700_SPI_BYTE_LEN; |
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else |
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val &= ~A3700_SPI_BYTE_LEN; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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|
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a3700_spi->byte_len = len; |
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} |
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|
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static int a3700_spi_fifo_flush(struct a3700_spi *a3700_spi) |
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{ |
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int timeout = A3700_SPI_TIMEOUT; |
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u32 val; |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val |= A3700_SPI_FIFO_FLUSH; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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|
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while (--timeout) { |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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if (!(val & A3700_SPI_FIFO_FLUSH)) |
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return 0; |
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udelay(1); |
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} |
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return -ETIMEDOUT; |
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} |
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|
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static int a3700_spi_init(struct a3700_spi *a3700_spi) |
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{ |
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struct spi_master *master = a3700_spi->master; |
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u32 val; |
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int i, ret = 0; |
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|
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/* Reset SPI unit */ |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val |= A3700_SPI_SRST; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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udelay(A3700_SPI_TIMEOUT); |
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~A3700_SPI_SRST; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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|
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/* Disable AUTO_CS and deactivate all chip-selects */ |
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a3700_spi_auto_cs_unset(a3700_spi); |
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for (i = 0; i < master->num_chipselect; i++) |
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a3700_spi_deactivate_cs(a3700_spi, i); |
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|
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/* Enable FIFO mode */ |
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a3700_spi_fifo_mode_set(a3700_spi); |
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|
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/* Set SPI mode */ |
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a3700_spi_mode_set(a3700_spi, master->mode_bits); |
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|
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/* Reset counters */ |
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spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, 0); |
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|
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/* Mask the interrupts and clear cause bits */ |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, ~0U); |
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return ret; |
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} |
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|
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static irqreturn_t a3700_spi_interrupt(int irq, void *dev_id) |
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{ |
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struct spi_master *master = dev_id; |
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struct a3700_spi *a3700_spi; |
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u32 cause; |
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|
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a3700_spi = spi_master_get_devdata(master); |
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|
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/* Get interrupt causes */ |
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cause = spireg_read(a3700_spi, A3700_SPI_INT_STAT_REG); |
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|
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if (!cause || !(a3700_spi->wait_mask & cause)) |
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return IRQ_NONE; |
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|
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/* mask and acknowledge the SPI interrupts */ |
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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spireg_write(a3700_spi, A3700_SPI_INT_STAT_REG, cause); |
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|
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/* Wake up the transfer */ |
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if (a3700_spi->wait_mask & cause) |
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complete(&a3700_spi->done); |
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return IRQ_HANDLED; |
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} |
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|
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static bool a3700_spi_wait_completion(struct spi_device *spi) |
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{ |
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struct a3700_spi *a3700_spi; |
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unsigned int timeout; |
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unsigned int ctrl_reg; |
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unsigned long timeout_jiffies; |
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|
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a3700_spi = spi_master_get_devdata(spi->master); |
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|
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/* SPI interrupt is edge-triggered, which means an interrupt will
|
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* be generated only when detecting a specific status bit changed |
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* from '0' to '1'. So when we start waiting for a interrupt, we |
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* need to check status bit in control reg first, if it is already 1, |
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* then we do not need to wait for interrupt |
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*/ |
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ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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if (a3700_spi->wait_mask & ctrl_reg) |
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return true; |
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|
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reinit_completion(&a3700_spi->done); |
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|
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, |
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a3700_spi->wait_mask); |
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|
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timeout_jiffies = msecs_to_jiffies(A3700_SPI_TIMEOUT); |
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timeout = wait_for_completion_timeout(&a3700_spi->done, |
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timeout_jiffies); |
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|
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a3700_spi->wait_mask = 0; |
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|
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if (timeout) |
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return true; |
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|
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/* there might be the case that right after we checked the
|
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* status bits in this routine and before start to wait for |
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* interrupt by wait_for_completion_timeout, the interrupt |
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* happens, to avoid missing it we need to double check |
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* status bits in control reg, if it is already 1, then |
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* consider that we have the interrupt successfully and |
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* return true. |
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*/ |
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ctrl_reg = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
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if (a3700_spi->wait_mask & ctrl_reg) |
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return true; |
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|
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spireg_write(a3700_spi, A3700_SPI_INT_MASK_REG, 0); |
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|
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return true; |
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} |
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|
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static bool a3700_spi_transfer_wait(struct spi_device *spi, |
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unsigned int bit_mask) |
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{ |
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struct a3700_spi *a3700_spi; |
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|
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a3700_spi = spi_master_get_devdata(spi->master); |
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a3700_spi->wait_mask = bit_mask; |
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|
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return a3700_spi_wait_completion(spi); |
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} |
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|
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static void a3700_spi_fifo_thres_set(struct a3700_spi *a3700_spi, |
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unsigned int bytes) |
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{ |
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u32 val; |
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|
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val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
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val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_RFIFO_THRS_BIT); |
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val |= (bytes - 1) << A3700_SPI_RFIFO_THRS_BIT; |
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val &= ~(A3700_SPI_FIFO_THRS_MASK << A3700_SPI_WFIFO_THRS_BIT); |
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val |= (7 - bytes) << A3700_SPI_WFIFO_THRS_BIT; |
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spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
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} |
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|
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static void a3700_spi_transfer_setup(struct spi_device *spi, |
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struct spi_transfer *xfer) |
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{ |
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struct a3700_spi *a3700_spi; |
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unsigned int byte_len; |
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|
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a3700_spi = spi_master_get_devdata(spi->master); |
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|
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a3700_spi_clock_set(a3700_spi, xfer->speed_hz, spi->mode); |
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|
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byte_len = xfer->bits_per_word >> 3; |
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|
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a3700_spi_fifo_thres_set(a3700_spi, byte_len); |
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} |
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|
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static void a3700_spi_set_cs(struct spi_device *spi, bool enable) |
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{ |
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struct a3700_spi *a3700_spi = spi_master_get_devdata(spi->master); |
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|
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if (!enable) |
||||
a3700_spi_activate_cs(a3700_spi, spi->chip_select); |
||||
else |
||||
a3700_spi_deactivate_cs(a3700_spi, spi->chip_select); |
||||
} |
||||
|
||||
static void a3700_spi_header_set(struct a3700_spi *a3700_spi) |
||||
{ |
||||
u32 instr_cnt = 0, addr_cnt = 0, dummy_cnt = 0; |
||||
u32 val = 0; |
||||
|
||||
/* Clear the header registers */ |
||||
spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, 0); |
||||
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, 0); |
||||
spireg_write(a3700_spi, A3700_SPI_IF_RMODE_REG, 0); |
||||
|
||||
/* Set header counters */ |
||||
if (a3700_spi->tx_buf) { |
||||
if (a3700_spi->buf_len <= a3700_spi->instr_cnt) { |
||||
instr_cnt = a3700_spi->buf_len; |
||||
} else if (a3700_spi->buf_len <= (a3700_spi->instr_cnt + |
||||
a3700_spi->addr_cnt)) { |
||||
instr_cnt = a3700_spi->instr_cnt; |
||||
addr_cnt = a3700_spi->buf_len - instr_cnt; |
||||
} else if (a3700_spi->buf_len <= a3700_spi->hdr_cnt) { |
||||
instr_cnt = a3700_spi->instr_cnt; |
||||
addr_cnt = a3700_spi->addr_cnt; |
||||
/* Need to handle the normal write case with 1 byte
|
||||
* data |
||||
*/ |
||||
if (!a3700_spi->tx_buf[instr_cnt + addr_cnt]) |
||||
dummy_cnt = a3700_spi->buf_len - instr_cnt - |
||||
addr_cnt; |
||||
} |
||||
val |= ((instr_cnt & A3700_SPI_INSTR_CNT_MASK) |
||||
<< A3700_SPI_INSTR_CNT_BIT); |
||||
val |= ((addr_cnt & A3700_SPI_ADDR_CNT_MASK) |
||||
<< A3700_SPI_ADDR_CNT_BIT); |
||||
val |= ((dummy_cnt & A3700_SPI_DUMMY_CNT_MASK) |
||||
<< A3700_SPI_DUMMY_CNT_BIT); |
||||
} |
||||
spireg_write(a3700_spi, A3700_SPI_IF_HDR_CNT_REG, val); |
||||
|
||||
/* Update the buffer length to be transferred */ |
||||
a3700_spi->buf_len -= (instr_cnt + addr_cnt + dummy_cnt); |
||||
|
||||
/* Set Instruction */ |
||||
val = 0; |
||||
while (instr_cnt--) { |
||||
val = (val << 8) | a3700_spi->tx_buf[0]; |
||||
a3700_spi->tx_buf++; |
||||
} |
||||
spireg_write(a3700_spi, A3700_SPI_IF_INST_REG, val); |
||||
|
||||
/* Set Address */ |
||||
val = 0; |
||||
while (addr_cnt--) { |
||||
val = (val << 8) | a3700_spi->tx_buf[0]; |
||||
a3700_spi->tx_buf++; |
||||
} |
||||
spireg_write(a3700_spi, A3700_SPI_IF_ADDR_REG, val); |
||||
} |
||||
|
||||
static int a3700_is_wfifo_full(struct a3700_spi *a3700_spi) |
||||
{ |
||||
u32 val; |
||||
|
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
||||
return (val & A3700_SPI_WFIFO_FULL); |
||||
} |
||||
|
||||
static int a3700_spi_fifo_write(struct a3700_spi *a3700_spi) |
||||
{ |
||||
u32 val; |
||||
int i = 0; |
||||
|
||||
while (!a3700_is_wfifo_full(a3700_spi) && a3700_spi->buf_len) { |
||||
val = 0; |
||||
if (a3700_spi->buf_len >= 4) { |
||||
val = cpu_to_le32(*(u32 *)a3700_spi->tx_buf); |
||||
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, val); |
||||
|
||||
a3700_spi->buf_len -= 4; |
||||
a3700_spi->tx_buf += 4; |
||||
} else { |
||||
/*
|
||||
* If the remained buffer length is less than 4-bytes, |
||||
* we should pad the write buffer with all ones. So that |
||||
* it avoids overwrite the unexpected bytes following |
||||
* the last one. |
||||
*/ |
||||
val = GENMASK(31, 0); |
||||
while (a3700_spi->buf_len) { |
||||
val &= ~(0xff << (8 * i)); |
||||
val |= *a3700_spi->tx_buf++ << (8 * i); |
||||
i++; |
||||
a3700_spi->buf_len--; |
||||
|
||||
spireg_write(a3700_spi, A3700_SPI_DATA_OUT_REG, |
||||
val); |
||||
} |
||||
break; |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int a3700_is_rfifo_empty(struct a3700_spi *a3700_spi) |
||||
{ |
||||
u32 val = spireg_read(a3700_spi, A3700_SPI_IF_CTRL_REG); |
||||
|
||||
return (val & A3700_SPI_RFIFO_EMPTY); |
||||
} |
||||
|
||||
static int a3700_spi_fifo_read(struct a3700_spi *a3700_spi) |
||||
{ |
||||
u32 val; |
||||
|
||||
while (!a3700_is_rfifo_empty(a3700_spi) && a3700_spi->buf_len) { |
||||
val = spireg_read(a3700_spi, A3700_SPI_DATA_IN_REG); |
||||
if (a3700_spi->buf_len >= 4) { |
||||
u32 data = le32_to_cpu(val); |
||||
memcpy(a3700_spi->rx_buf, &data, 4); |
||||
|
||||
a3700_spi->buf_len -= 4; |
||||
a3700_spi->rx_buf += 4; |
||||
} else { |
||||
/*
|
||||
* When remain bytes is not larger than 4, we should |
||||
* avoid memory overwriting and just write the left rx |
||||
* buffer bytes. |
||||
*/ |
||||
while (a3700_spi->buf_len) { |
||||
*a3700_spi->rx_buf = val & 0xff; |
||||
val >>= 8; |
||||
|
||||
a3700_spi->buf_len--; |
||||
a3700_spi->rx_buf++; |
||||
} |
||||
} |
||||
} |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static void a3700_spi_transfer_abort_fifo(struct a3700_spi *a3700_spi) |
||||
{ |
||||
int timeout = A3700_SPI_TIMEOUT; |
||||
u32 val; |
||||
|
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
val |= A3700_SPI_XFER_STOP; |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
|
||||
while (--timeout) { |
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
if (!(val & A3700_SPI_XFER_START)) |
||||
break; |
||||
udelay(1); |
||||
} |
||||
|
||||
a3700_spi_fifo_flush(a3700_spi); |
||||
|
||||
val &= ~A3700_SPI_XFER_STOP; |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
} |
||||
|
||||
static int a3700_spi_prepare_message(struct spi_master *master, |
||||
struct spi_message *message) |
||||
{ |
||||
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
||||
struct spi_device *spi = message->spi; |
||||
int ret; |
||||
|
||||
ret = clk_enable(a3700_spi->clk); |
||||
if (ret) { |
||||
dev_err(&spi->dev, "failed to enable clk with error %d\n", ret); |
||||
return ret; |
||||
} |
||||
|
||||
/* Flush the FIFOs */ |
||||
ret = a3700_spi_fifo_flush(a3700_spi); |
||||
if (ret) |
||||
return ret; |
||||
|
||||
a3700_spi_bytelen_set(a3700_spi, 4); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static int a3700_spi_transfer_one(struct spi_master *master, |
||||
struct spi_device *spi, |
||||
struct spi_transfer *xfer) |
||||
{ |
||||
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
||||
int ret = 0, timeout = A3700_SPI_TIMEOUT; |
||||
unsigned int nbits = 0; |
||||
u32 val; |
||||
|
||||
a3700_spi_transfer_setup(spi, xfer); |
||||
|
||||
a3700_spi->tx_buf = xfer->tx_buf; |
||||
a3700_spi->rx_buf = xfer->rx_buf; |
||||
a3700_spi->buf_len = xfer->len; |
||||
|
||||
/* SPI transfer headers */ |
||||
a3700_spi_header_set(a3700_spi); |
||||
|
||||
if (xfer->tx_buf) |
||||
nbits = xfer->tx_nbits; |
||||
else if (xfer->rx_buf) |
||||
nbits = xfer->rx_nbits; |
||||
|
||||
a3700_spi_pin_mode_set(a3700_spi, nbits); |
||||
|
||||
if (xfer->rx_buf) { |
||||
/* Set read data length */ |
||||
spireg_write(a3700_spi, A3700_SPI_IF_DIN_CNT_REG, |
||||
a3700_spi->buf_len); |
||||
/* Start READ transfer */ |
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
val &= ~A3700_SPI_RW_EN; |
||||
val |= A3700_SPI_XFER_START; |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
} else if (xfer->tx_buf) { |
||||
/* Start Write transfer */ |
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
val |= (A3700_SPI_XFER_START | A3700_SPI_RW_EN); |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
|
||||
/*
|
||||
* If there are data to be written to the SPI device, xmit_data |
||||
* flag is set true; otherwise the instruction in SPI_INSTR does |
||||
* not require data to be written to the SPI device, then |
||||
* xmit_data flag is set false. |
||||
*/ |
||||
a3700_spi->xmit_data = (a3700_spi->buf_len != 0); |
||||
} |
||||
|
||||
while (a3700_spi->buf_len) { |
||||
if (a3700_spi->tx_buf) { |
||||
/* Wait wfifo ready */ |
||||
if (!a3700_spi_transfer_wait(spi, |
||||
A3700_SPI_WFIFO_RDY)) { |
||||
dev_err(&spi->dev, |
||||
"wait wfifo ready timed out\n"); |
||||
ret = -ETIMEDOUT; |
||||
goto error; |
||||
} |
||||
/* Fill up the wfifo */ |
||||
ret = a3700_spi_fifo_write(a3700_spi); |
||||
if (ret) |
||||
goto error; |
||||
} else if (a3700_spi->rx_buf) { |
||||
/* Wait rfifo ready */ |
||||
if (!a3700_spi_transfer_wait(spi, |
||||
A3700_SPI_RFIFO_RDY)) { |
||||
dev_err(&spi->dev, |
||||
"wait rfifo ready timed out\n"); |
||||
ret = -ETIMEDOUT; |
||||
goto error; |
||||
} |
||||
/* Drain out the rfifo */ |
||||
ret = a3700_spi_fifo_read(a3700_spi); |
||||
if (ret) |
||||
goto error; |
||||
} |
||||
} |
||||
|
||||
/*
|
||||
* Stop a write transfer in fifo mode: |
||||
* - wait all the bytes in wfifo to be shifted out |
||||
* - set XFER_STOP bit |
||||
* - wait XFER_START bit clear |
||||
* - clear XFER_STOP bit |
||||
* Stop a read transfer in fifo mode: |
||||
* - the hardware is to reset the XFER_START bit |
||||
* after the number of bytes indicated in DIN_CNT |
||||
* register |
||||
* - just wait XFER_START bit clear |
||||
*/ |
||||
if (a3700_spi->tx_buf) { |
||||
if (a3700_spi->xmit_data) { |
||||
/*
|
||||
* If there are data written to the SPI device, wait |
||||
* until SPI_WFIFO_EMPTY is 1 to wait for all data to |
||||
* transfer out of write FIFO. |
||||
*/ |
||||
if (!a3700_spi_transfer_wait(spi, |
||||
A3700_SPI_WFIFO_EMPTY)) { |
||||
dev_err(&spi->dev, "wait wfifo empty timed out\n"); |
||||
return -ETIMEDOUT; |
||||
} |
||||
} else { |
||||
/*
|
||||
* If the instruction in SPI_INSTR does not require data |
||||
* to be written to the SPI device, wait until SPI_RDY |
||||
* is 1 for the SPI interface to be in idle. |
||||
*/ |
||||
if (!a3700_spi_transfer_wait(spi, A3700_SPI_XFER_RDY)) { |
||||
dev_err(&spi->dev, "wait xfer ready timed out\n"); |
||||
return -ETIMEDOUT; |
||||
} |
||||
} |
||||
|
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
val |= A3700_SPI_XFER_STOP; |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
} |
||||
|
||||
while (--timeout) { |
||||
val = spireg_read(a3700_spi, A3700_SPI_IF_CFG_REG); |
||||
if (!(val & A3700_SPI_XFER_START)) |
||||
break; |
||||
udelay(1); |
||||
} |
||||
|
||||
if (timeout == 0) { |
||||
dev_err(&spi->dev, "wait transfer start clear timed out\n"); |
||||
ret = -ETIMEDOUT; |
||||
goto error; |
||||
} |
||||
|
||||
val &= ~A3700_SPI_XFER_STOP; |
||||
spireg_write(a3700_spi, A3700_SPI_IF_CFG_REG, val); |
||||
goto out; |
||||
|
||||
error: |
||||
a3700_spi_transfer_abort_fifo(a3700_spi); |
||||
out: |
||||
spi_finalize_current_transfer(master); |
||||
|
||||
return ret; |
||||
} |
||||
|
||||
static int a3700_spi_unprepare_message(struct spi_master *master, |
||||
struct spi_message *message) |
||||
{ |
||||
struct a3700_spi *a3700_spi = spi_master_get_devdata(master); |
||||
|
||||
clk_disable(a3700_spi->clk); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static const struct of_device_id a3700_spi_dt_ids[] = { |
||||
{ .compatible = "marvell,armada-3700-spi", .data = NULL }, |
||||
{}, |
||||
}; |
||||
|
||||
MODULE_DEVICE_TABLE(of, a3700_spi_dt_ids); |
||||
|
||||
static int a3700_spi_probe(struct platform_device *pdev) |
||||
{ |
||||
struct device *dev = &pdev->dev; |
||||
struct device_node *of_node = dev->of_node; |
||||
struct resource *res; |
||||
struct spi_master *master; |
||||
struct a3700_spi *spi; |
||||
u32 num_cs = 0; |
||||
int ret = 0; |
||||
|
||||
master = spi_alloc_master(dev, sizeof(*spi)); |
||||
if (!master) { |
||||
dev_err(dev, "master allocation failed\n"); |
||||
ret = -ENOMEM; |
||||
goto out; |
||||
} |
||||
|
||||
if (of_property_read_u32(of_node, "num-cs", &num_cs)) { |
||||
dev_err(dev, "could not find num-cs\n"); |
||||
ret = -ENXIO; |
||||
goto error; |
||||
} |
||||
|
||||
master->bus_num = pdev->id; |
||||
master->dev.of_node = of_node; |
||||
master->mode_bits = SPI_MODE_3; |
||||
master->num_chipselect = num_cs; |
||||
master->bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(32); |
||||
master->prepare_message = a3700_spi_prepare_message; |
||||
master->transfer_one = a3700_spi_transfer_one; |
||||
master->unprepare_message = a3700_spi_unprepare_message; |
||||
master->set_cs = a3700_spi_set_cs; |
||||
master->flags = SPI_MASTER_HALF_DUPLEX; |
||||
master->mode_bits |= (SPI_RX_DUAL | SPI_RX_DUAL | |
||||
SPI_RX_QUAD | SPI_TX_QUAD); |
||||
|
||||
platform_set_drvdata(pdev, master); |
||||
|
||||
spi = spi_master_get_devdata(master); |
||||
memset(spi, 0, sizeof(struct a3700_spi)); |
||||
|
||||
spi->master = master; |
||||
spi->instr_cnt = A3700_INSTR_CNT; |
||||
spi->addr_cnt = A3700_ADDR_CNT; |
||||
spi->hdr_cnt = A3700_INSTR_CNT + A3700_ADDR_CNT + |
||||
A3700_DUMMY_CNT; |
||||
|
||||
res = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
||||
spi->base = devm_ioremap_resource(dev, res); |
||||
if (IS_ERR(spi->base)) { |
||||
ret = PTR_ERR(spi->base); |
||||
goto error; |
||||
} |
||||
|
||||
spi->irq = platform_get_irq(pdev, 0); |
||||
if (spi->irq < 0) { |
||||
dev_err(dev, "could not get irq: %d\n", spi->irq); |
||||
ret = -ENXIO; |
||||
goto error; |
||||
} |
||||
|
||||
init_completion(&spi->done); |
||||
|
||||
spi->clk = devm_clk_get(dev, NULL); |
||||
if (IS_ERR(spi->clk)) { |
||||
dev_err(dev, "could not find clk: %ld\n", PTR_ERR(spi->clk)); |
||||
goto error; |
||||
} |
||||
|
||||
ret = clk_prepare(spi->clk); |
||||
if (ret) { |
||||
dev_err(dev, "could not prepare clk: %d\n", ret); |
||||
goto error; |
||||
} |
||||
|
||||
ret = a3700_spi_init(spi); |
||||
if (ret) |
||||
goto error_clk; |
||||
|
||||
ret = devm_request_irq(dev, spi->irq, a3700_spi_interrupt, 0, |
||||
dev_name(dev), master); |
||||
if (ret) { |
||||
dev_err(dev, "could not request IRQ: %d\n", ret); |
||||
goto error_clk; |
||||
} |
||||
|
||||
ret = devm_spi_register_master(dev, master); |
||||
if (ret) { |
||||
dev_err(dev, "Failed to register master\n"); |
||||
goto error_clk; |
||||
} |
||||
|
||||
return 0; |
||||
|
||||
error_clk: |
||||
clk_disable_unprepare(spi->clk); |
||||
error: |
||||
spi_master_put(master); |
||||
out: |
||||
return ret; |
||||
} |
||||
|
||||
static int a3700_spi_remove(struct platform_device *pdev) |
||||
{ |
||||
struct spi_master *master = platform_get_drvdata(pdev); |
||||
struct a3700_spi *spi = spi_master_get_devdata(master); |
||||
|
||||
clk_unprepare(spi->clk); |
||||
spi_master_put(master); |
||||
|
||||
return 0; |
||||
} |
||||
|
||||
static struct platform_driver a3700_spi_driver = { |
||||
.driver = { |
||||
.name = DRIVER_NAME, |
||||
.owner = THIS_MODULE, |
||||
.of_match_table = of_match_ptr(a3700_spi_dt_ids), |
||||
}, |
||||
.probe = a3700_spi_probe, |
||||
.remove = a3700_spi_remove, |
||||
}; |
||||
|
||||
module_platform_driver(a3700_spi_driver); |
||||
|
||||
MODULE_DESCRIPTION("Armada-3700 SPI driver"); |
||||
MODULE_AUTHOR("Wilson Ding <dingwei@marvell.com>"); |
||||
MODULE_LICENSE("GPL"); |
||||
MODULE_ALIAS("platform:" DRIVER_NAME); |
||||
Loading…
Reference in new issue