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#ifndef _MVME147HW_H_
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#define _MVME147HW_H_
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#include <asm/irq.h>
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typedef struct {
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unsigned char
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ctrl,
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bcd_sec,
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bcd_min,
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bcd_hr,
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bcd_dow,
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bcd_dom,
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bcd_mth,
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bcd_year;
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} MK48T02;
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#define RTC_WRITE 0x80
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#define RTC_READ 0x40
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#define RTC_STOP 0x20
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#define m147_rtc ((MK48T02 * volatile)0xfffe07f8)
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struct pcc_regs {
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volatile u_long dma_tadr;
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volatile u_long dma_dadr;
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volatile u_long dma_bcr;
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volatile u_long dma_hr;
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volatile u_short t1_preload;
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volatile u_short t1_count;
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volatile u_short t2_preload;
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volatile u_short t2_count;
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volatile u_char t1_int_cntrl;
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volatile u_char t1_cntrl;
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volatile u_char t2_int_cntrl;
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volatile u_char t2_cntrl;
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volatile u_char ac_fail;
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volatile u_char watchdog;
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volatile u_char lpt_intr;
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volatile u_char lpt_cntrl;
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volatile u_char dma_intr;
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volatile u_char dma_cntrl;
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volatile u_char bus_error;
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volatile u_char dma_status;
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volatile u_char abort;
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volatile u_char ta_fnctl;
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volatile u_char serial_cntrl;
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volatile u_char general_cntrl;
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volatile u_char lan_cntrl;
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volatile u_char general_status;
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volatile u_char scsi_interrupt;
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volatile u_char slave;
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volatile u_char soft1_cntrl;
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volatile u_char int_base;
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volatile u_char soft2_cntrl;
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volatile u_char revision_level;
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volatile u_char lpt_data;
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volatile u_char lpt_status;
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};
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#define m147_pcc ((struct pcc_regs * volatile)0xfffe1000)
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#define PCC_INT_ENAB 0x08
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#define PCC_TIMER_INT_CLR 0x80
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#define PCC_TIMER_PRELOAD 63936l
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#define PCC_LEVEL_ABORT 0x07
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#define PCC_LEVEL_SERIAL 0x04
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#define PCC_LEVEL_ETH 0x04
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#define PCC_LEVEL_TIMER1 0x04
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#define PCC_LEVEL_SCSI_PORT 0x04
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#define PCC_LEVEL_SCSI_DMA 0x04
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#define PCC_IRQ_AC_FAIL (IRQ_USER+0)
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#define PCC_IRQ_BERR (IRQ_USER+1)
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#define PCC_IRQ_ABORT (IRQ_USER+2)
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/* #define PCC_IRQ_SERIAL (IRQ_USER+3) */
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#define PCC_IRQ_PRINTER (IRQ_USER+7)
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#define PCC_IRQ_TIMER1 (IRQ_USER+8)
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#define PCC_IRQ_TIMER2 (IRQ_USER+9)
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#define PCC_IRQ_SOFTWARE1 (IRQ_USER+10)
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#define PCC_IRQ_SOFTWARE2 (IRQ_USER+11)
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#define M147_SCC_A_ADDR 0xfffe3002
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#define M147_SCC_B_ADDR 0xfffe3000
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#define M147_SCC_PCLK 5000000
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#define MVME147_IRQ_SCSI_PORT (IRQ_USER+0x45)
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#define MVME147_IRQ_SCSI_DMA (IRQ_USER+0x46)
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/* SCC interrupts, for MVME147 */
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#define MVME147_IRQ_TYPE_PRIO 0
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#define MVME147_IRQ_SCC_BASE (IRQ_USER+32)
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#define MVME147_IRQ_SCCB_TX (IRQ_USER+32)
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#define MVME147_IRQ_SCCB_STAT (IRQ_USER+34)
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#define MVME147_IRQ_SCCB_RX (IRQ_USER+36)
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#define MVME147_IRQ_SCCB_SPCOND (IRQ_USER+38)
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#define MVME147_IRQ_SCCA_TX (IRQ_USER+40)
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#define MVME147_IRQ_SCCA_STAT (IRQ_USER+42)
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#define MVME147_IRQ_SCCA_RX (IRQ_USER+44)
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#define MVME147_IRQ_SCCA_SPCOND (IRQ_USER+46)
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#define MVME147_LANCE_BASE 0xfffe1800
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#define MVME147_LANCE_IRQ (IRQ_USER+4)
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#define ETHERNET_ADDRESS 0xfffe0778
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#endif
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