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274 lines
8.4 KiB
274 lines
8.4 KiB
17 years ago
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/*
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* kvm_minstate.h: min save macros
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* Copyright (c) 2007, Intel Corporation.
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*
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* Xuefei Xu (Anthony Xu) (Anthony.xu@intel.com)
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* Xiantao Zhang (xiantao.zhang@intel.com)
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc., 59 Temple
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* Place - Suite 330, Boston, MA 02111-1307 USA.
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*
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*/
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#include <asm/asmmacro.h>
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#include <asm/types.h>
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#include <asm/kregs.h>
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#include "asm-offsets.h"
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#define KVM_MINSTATE_START_SAVE_MIN \
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mov ar.rsc = 0;/* set enforced lazy mode, pl 0, little-endian, loadrs=0 */\
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;; \
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mov.m r28 = ar.rnat; \
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addl r22 = VMM_RBS_OFFSET,r1; /* compute base of RBS */ \
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;; \
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lfetch.fault.excl.nt1 [r22]; \
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addl r1 = IA64_STK_OFFSET-VMM_PT_REGS_SIZE,r1; /* compute base of memory stack */ \
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mov r23 = ar.bspstore; /* save ar.bspstore */ \
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;; \
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mov ar.bspstore = r22; /* switch to kernel RBS */\
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;; \
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mov r18 = ar.bsp; \
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mov ar.rsc = 0x3; /* set eager mode, pl 0, little-endian, loadrs=0 */
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#define KVM_MINSTATE_END_SAVE_MIN \
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bsw.1; /* switch back to bank 1 (must be last in insn group) */\
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;;
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#define PAL_VSA_SYNC_READ \
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/* begin to call pal vps sync_read */ \
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add r25 = VMM_VPD_BASE_OFFSET, r21; \
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adds r20 = VMM_VCPU_VSA_BASE_OFFSET, r21; /* entry point */ \
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;; \
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ld8 r25 = [r25]; /* read vpd base */ \
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ld8 r20 = [r20]; \
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;; \
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add r20 = PAL_VPS_SYNC_READ,r20; \
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;; \
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{ .mii; \
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nop 0x0; \
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mov r24 = ip; \
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mov b0 = r20; \
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;; \
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}; \
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{ .mmb; \
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add r24 = 0x20, r24; \
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nop 0x0; \
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br.cond.sptk b0; /* call the service */ \
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;; \
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};
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#define KVM_MINSTATE_GET_CURRENT(reg) mov reg=r21
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/*
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* KVM_DO_SAVE_MIN switches to the kernel stacks (if necessary) and saves
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* the minimum state necessary that allows us to turn psr.ic back
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* on.
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*
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* Assumed state upon entry:
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* psr.ic: off
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* r31: contains saved predicates (pr)
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*
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* Upon exit, the state is as follows:
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* psr.ic: off
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* r2 = points to &pt_regs.r16
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* r8 = contents of ar.ccv
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* r9 = contents of ar.csd
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* r10 = contents of ar.ssd
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* r11 = FPSR_DEFAULT
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* r12 = kernel sp (kernel virtual address)
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* r13 = points to current task_struct (kernel virtual address)
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* p15 = TRUE if psr.i is set in cr.ipsr
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* predicate registers (other than p2, p3, and p15), b6, r3, r14, r15:
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* preserved
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*
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* Note that psr.ic is NOT turned on by this macro. This is so that
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* we can pass interruption state as arguments to a handler.
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*/
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#define PT(f) (VMM_PT_REGS_##f##_OFFSET)
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#define KVM_DO_SAVE_MIN(COVER,SAVE_IFS,EXTRA) \
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KVM_MINSTATE_GET_CURRENT(r16); /* M (or M;;I) */ \
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mov r27 = ar.rsc; /* M */ \
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mov r20 = r1; /* A */ \
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mov r25 = ar.unat; /* M */ \
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mov r29 = cr.ipsr; /* M */ \
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mov r26 = ar.pfs; /* I */ \
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mov r18 = cr.isr; \
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COVER; /* B;; (or nothing) */ \
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;; \
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tbit.z p0,p15 = r29,IA64_PSR_I_BIT; \
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mov r1 = r16; \
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/* mov r21=r16; */ \
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/* switch from user to kernel RBS: */ \
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;; \
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invala; /* M */ \
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SAVE_IFS; \
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;; \
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KVM_MINSTATE_START_SAVE_MIN \
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adds r17 = 2*L1_CACHE_BYTES,r1;/* cache-line size */ \
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adds r16 = PT(CR_IPSR),r1; \
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;; \
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lfetch.fault.excl.nt1 [r17],L1_CACHE_BYTES; \
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st8 [r16] = r29; /* save cr.ipsr */ \
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;; \
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lfetch.fault.excl.nt1 [r17]; \
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tbit.nz p15,p0 = r29,IA64_PSR_I_BIT; \
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mov r29 = b0 \
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;; \
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adds r16 = PT(R8),r1; /* initialize first base pointer */\
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adds r17 = PT(R9),r1; /* initialize second base pointer */\
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;; \
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.mem.offset 0,0; st8.spill [r16] = r8,16; \
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.mem.offset 8,0; st8.spill [r17] = r9,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r10,24; \
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.mem.offset 8,0; st8.spill [r17] = r11,24; \
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;; \
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mov r9 = cr.iip; /* M */ \
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mov r10 = ar.fpsr; /* M */ \
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;; \
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st8 [r16] = r9,16; /* save cr.iip */ \
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st8 [r17] = r30,16; /* save cr.ifs */ \
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sub r18 = r18,r22; /* r18=RSE.ndirty*8 */ \
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;; \
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st8 [r16] = r25,16; /* save ar.unat */ \
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st8 [r17] = r26,16; /* save ar.pfs */ \
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shl r18 = r18,16; /* calu ar.rsc used for "loadrs" */\
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;; \
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st8 [r16] = r27,16; /* save ar.rsc */ \
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st8 [r17] = r28,16; /* save ar.rnat */ \
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;; /* avoid RAW on r16 & r17 */ \
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st8 [r16] = r23,16; /* save ar.bspstore */ \
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st8 [r17] = r31,16; /* save predicates */ \
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;; \
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st8 [r16] = r29,16; /* save b0 */ \
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st8 [r17] = r18,16; /* save ar.rsc value for "loadrs" */\
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;; \
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.mem.offset 0,0; st8.spill [r16] = r20,16;/* save original r1 */ \
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.mem.offset 8,0; st8.spill [r17] = r12,16; \
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adds r12 = -16,r1; /* switch to kernel memory stack */ \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r13,16; \
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.mem.offset 8,0; st8.spill [r17] = r10,16; /* save ar.fpsr */\
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mov r13 = r21; /* establish `current' */ \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r15,16; \
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.mem.offset 8,0; st8.spill [r17] = r14,16; \
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;; \
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.mem.offset 0,0; st8.spill [r16] = r2,16; \
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.mem.offset 8,0; st8.spill [r17] = r3,16; \
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adds r2 = VMM_PT_REGS_R16_OFFSET,r1; \
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;; \
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adds r16 = VMM_VCPU_IIPA_OFFSET,r13; \
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adds r17 = VMM_VCPU_ISR_OFFSET,r13; \
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mov r26 = cr.iipa; \
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mov r27 = cr.isr; \
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;; \
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st8 [r16] = r26; \
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st8 [r17] = r27; \
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;; \
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EXTRA; \
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mov r8 = ar.ccv; \
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mov r9 = ar.csd; \
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mov r10 = ar.ssd; \
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movl r11 = FPSR_DEFAULT; /* L-unit */ \
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adds r17 = VMM_VCPU_GP_OFFSET,r13; \
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;; \
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ld8 r1 = [r17];/* establish kernel global pointer */ \
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;; \
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PAL_VSA_SYNC_READ \
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KVM_MINSTATE_END_SAVE_MIN
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/*
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* SAVE_REST saves the remainder of pt_regs (with psr.ic on).
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*
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* Assumed state upon entry:
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* psr.ic: on
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* r2: points to &pt_regs.f6
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* r3: points to &pt_regs.f7
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* r8: contents of ar.ccv
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* r9: contents of ar.csd
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* r10: contents of ar.ssd
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* r11: FPSR_DEFAULT
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*
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* Registers r14 and r15 are guaranteed not to be touched by SAVE_REST.
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*/
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#define KVM_SAVE_REST \
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.mem.offset 0,0; st8.spill [r2] = r16,16; \
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.mem.offset 8,0; st8.spill [r3] = r17,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r18,16; \
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.mem.offset 8,0; st8.spill [r3] = r19,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r20,16; \
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.mem.offset 8,0; st8.spill [r3] = r21,16; \
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mov r18=b6; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r22,16; \
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.mem.offset 8,0; st8.spill [r3] = r23,16; \
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mov r19 = b7; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r24,16; \
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.mem.offset 8,0; st8.spill [r3] = r25,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r26,16; \
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.mem.offset 8,0; st8.spill [r3] = r27,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r28,16; \
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.mem.offset 8,0; st8.spill [r3] = r29,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r30,16; \
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.mem.offset 8,0; st8.spill [r3] = r31,32; \
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;; \
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mov ar.fpsr = r11; \
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st8 [r2] = r8,8; \
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adds r24 = PT(B6)-PT(F7),r3; \
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adds r25 = PT(B7)-PT(F7),r3; \
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;; \
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st8 [r24] = r18,16; /* b6 */ \
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st8 [r25] = r19,16; /* b7 */ \
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adds r2 = PT(R4)-PT(F6),r2; \
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adds r3 = PT(R5)-PT(F7),r3; \
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;; \
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st8 [r24] = r9; /* ar.csd */ \
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st8 [r25] = r10; /* ar.ssd */ \
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;; \
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mov r18 = ar.unat; \
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adds r19 = PT(EML_UNAT)-PT(R4),r2; \
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;; \
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st8 [r19] = r18; /* eml_unat */ \
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#define KVM_SAVE_EXTRA \
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.mem.offset 0,0; st8.spill [r2] = r4,16; \
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.mem.offset 8,0; st8.spill [r3] = r5,16; \
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;; \
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.mem.offset 0,0; st8.spill [r2] = r6,16; \
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.mem.offset 8,0; st8.spill [r3] = r7; \
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;; \
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mov r26 = ar.unat; \
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;; \
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st8 [r2] = r26;/* eml_unat */ \
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#define KVM_SAVE_MIN_WITH_COVER KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs,)
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#define KVM_SAVE_MIN_WITH_COVER_R19 KVM_DO_SAVE_MIN(cover, mov r30 = cr.ifs, mov r15 = r19)
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#define KVM_SAVE_MIN KVM_DO_SAVE_MIN( , mov r30 = r0, )
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