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kernel_samsung_sm7125/arch/avr32/mach-at32ap/sdramc.h

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avr32: Power Management support ("standby" and "mem" modes) Implement Standby support. In this mode, we'll suspend all drivers, put the SDRAM in self-refresh mode and switch off the HSB bus ("frozen" mode.) Implement Suspend-to-mem support. In this mode, we suspend all drivers, put the SDRAM into self-refresh mode and switch off all internal clocks except the 32 kHz oscillator ("stop" mode.) The lowest-level suspend code runs from a small portion of SRAM allocated at startup time. This gets rid of a small potential race with the SDRAM where we might try to enter self-refresh mode in the middle of an icache burst. We also relocate all interrupt and exception handlers to SRAM during the small window when we enter and exit the low-power modes. We don't need to do any special tricks to start and stop the PLL. The main clock is automatically gated by hardware until the PLL is stable. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
17 years ago
/*
* Register definitions for the AT32AP SDRAM Controller
*
* Copyright (C) 2008 Atmel Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*/
/* Register offsets */
#define SDRAMC_MR 0x0000
#define SDRAMC_TR 0x0004
#define SDRAMC_CR 0x0008
#define SDRAMC_HSR 0x000c
#define SDRAMC_LPR 0x0010
#define SDRAMC_IER 0x0014
#define SDRAMC_IDR 0x0018
#define SDRAMC_IMR 0x001c
#define SDRAMC_ISR 0x0020
#define SDRAMC_MDR 0x0024
/* MR - Mode Register */
#define SDRAMC_MR_MODE_NORMAL ( 0 << 0)
#define SDRAMC_MR_MODE_NOP ( 1 << 0)
#define SDRAMC_MR_MODE_BANKS_PRECHARGE ( 2 << 0)
#define SDRAMC_MR_MODE_LOAD_MODE ( 3 << 0)
#define SDRAMC_MR_MODE_AUTO_REFRESH ( 4 << 0)
#define SDRAMC_MR_MODE_EXT_LOAD_MODE ( 5 << 0)
#define SDRAMC_MR_MODE_POWER_DOWN ( 6 << 0)
/* CR - Configuration Register */
#define SDRAMC_CR_NC_8_BITS ( 0 << 0)
#define SDRAMC_CR_NC_9_BITS ( 1 << 0)
#define SDRAMC_CR_NC_10_BITS ( 2 << 0)
#define SDRAMC_CR_NC_11_BITS ( 3 << 0)
#define SDRAMC_CR_NR_11_BITS ( 0 << 2)
#define SDRAMC_CR_NR_12_BITS ( 1 << 2)
#define SDRAMC_CR_NR_13_BITS ( 2 << 2)
#define SDRAMC_CR_NB_2_BANKS ( 0 << 4)
#define SDRAMC_CR_NB_4_BANKS ( 1 << 4)
#define SDRAMC_CR_CAS(x) ((x) << 5)
#define SDRAMC_CR_DBW_32_BITS ( 0 << 7)
#define SDRAMC_CR_DBW_16_BITS ( 1 << 7)
#define SDRAMC_CR_TWR(x) ((x) << 8)
#define SDRAMC_CR_TRC(x) ((x) << 12)
#define SDRAMC_CR_TRP(x) ((x) << 16)
#define SDRAMC_CR_TRCD(x) ((x) << 20)
#define SDRAMC_CR_TRAS(x) ((x) << 24)
#define SDRAMC_CR_TXSR(x) ((x) << 28)
/* HSR - High Speed Register */
#define SDRAMC_HSR_DA ( 1 << 0)
/* LPR - Low Power Register */
#define SDRAMC_LPR_LPCB_INHIBIT ( 0 << 0)
#define SDRAMC_LPR_LPCB_SELF_RFR ( 1 << 0)
#define SDRAMC_LPR_LPCB_PDOWN ( 2 << 0)
#define SDRAMC_LPR_LPCB_DEEP_PDOWN ( 3 << 0)
#define SDRAMC_LPR_PASR(x) ((x) << 4)
#define SDRAMC_LPR_TCSR(x) ((x) << 8)
#define SDRAMC_LPR_DS(x) ((x) << 10)
#define SDRAMC_LPR_TIMEOUT(x) ((x) << 12)
/* IER/IDR/IMR/ISR - Interrupt Enable/Disable/Mask/Status Register */
#define SDRAMC_ISR_RES ( 1 << 0)
/* MDR - Memory Device Register */
#define SDRAMC_MDR_MD_SDRAM ( 0 << 0)
#define SDRAMC_MDR_MD_LOW_PWR_SDRAM ( 1 << 0)
/* Register access macros */
#define sdramc_readl(reg) \
__raw_readl((void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)
#define sdramc_writel(reg, value) \
__raw_writel(value, (void __iomem __force *)SDRAMC_BASE + SDRAMC_##reg)