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88 lines
3.2 KiB
88 lines
3.2 KiB
20 years ago
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/*
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* ItLpRegSave.h
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* Copyright (C) 2001 Mike Corrigan IBM Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
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*/
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#ifndef _ITLPREGSAVE_H
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#define _ITLPREGSAVE_H
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//=====================================================================================
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//
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// This control block contains the data that is shared between PLIC
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// and the OS
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//
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//
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struct ItLpRegSave
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{
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u32 xDesc; // Eye catcher "LpRS" ebcdic 000-003
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u16 xSize; // Size of this class 004-005
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u8 xInUse; // Area is live 006-007
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u8 xRsvd1[9]; // Reserved 007-00F
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u8 xFixedRegSave[352]; // Fixed Register Save Area 010-16F
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u32 xCTRL; // Control Register 170-173
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u32 xDEC; // Decrementer 174-177
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u32 xFPSCR; // FP Status and Control Reg 178-17B
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u32 xPVR; // Processor Version Number 17C-17F
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u64 xMMCR0; // Monitor Mode Control Reg 0 180-187
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u32 xPMC1; // Perf Monitor Counter 1 188-18B
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u32 xPMC2; // Perf Monitor Counter 2 18C-18F
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u32 xPMC3; // Perf Monitor Counter 3 190-193
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u32 xPMC4; // Perf Monitor Counter 4 194-197
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u32 xPIR; // Processor ID Reg 198-19B
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u32 xMMCR1; // Monitor Mode Control Reg 1 19C-19F
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u32 xMMCRA; // Monitor Mode Control Reg A 1A0-1A3
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u32 xPMC5; // Perf Monitor Counter 5 1A4-1A7
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u32 xPMC6; // Perf Monitor Counter 6 1A8-1AB
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u32 xPMC7; // Perf Monitor Counter 7 1AC-1AF
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u32 xPMC8; // Perf Monitor Counter 8 1B0-1B3
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u32 xTSC; // Thread Switch Control 1B4-1B7
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u32 xTST; // Thread Switch Timeout 1B8-1BB
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u32 xRsvd; // Reserved 1BC-1BF
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u64 xACCR; // Address Compare Control Reg 1C0-1C7
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u64 xIMR; // Instruction Match Register 1C8-1CF
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u64 xSDR1; // Storage Description Reg 1 1D0-1D7
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u64 xSPRG0; // Special Purpose Reg General0 1D8-1DF
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u64 xSPRG1; // Special Purpose Reg General1 1E0-1E7
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u64 xSPRG2; // Special Purpose Reg General2 1E8-1EF
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u64 xSPRG3; // Special Purpose Reg General3 1F0-1F7
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u64 xTB; // Time Base Register 1F8-1FF
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u64 xFPR[32]; // Floating Point Registers 200-2FF
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u64 xMSR; // Machine State Register 300-307
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u64 xNIA; // Next Instruction Address 308-30F
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u64 xDABR; // Data Address Breakpoint Reg 310-317
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u64 xIABR; // Inst Address Breakpoint Reg 318-31F
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u64 xHID0; // HW Implementation Dependent0 320-327
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u64 xHID4; // HW Implementation Dependent4 328-32F
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u64 xSCOMd; // SCON Data Reg (SPRG4) 330-337
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u64 xSCOMc; // SCON Command Reg (SPRG5) 338-33F
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u64 xSDAR; // Sample Data Address Register 340-347
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u64 xSIAR; // Sample Inst Address Register 348-34F
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u8 xRsvd3[176]; // Reserved 350-3FF
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};
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#endif /* _ITLPREGSAVE_H */
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